Abstract: Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.

Abstract: A voltage sample and hold circuit for use as part of a low leakage charge pump circuit in a phase lock loop (PLL). During an inactive state of the charge pumping function, a MOSFET switch that normally connects the charge pump output to the loop filter preceding the voltage controlled oscillator (VCO) of the PLL is opened, e.g., for open loop modulation of the VCO. Meanwhile, the sample and hold circuit which has sampled the voltage at the input side of the MOSFET switch now maintains that voltage, thereby forcing a zero-voltage difference across the MOSFET switch. This zero-voltage difference virtually eliminates subthreshold leakage current through the MOSFET switch, thereby significantly reducing loss of charge in the loop filter due to such leakage current. This ensures a significantly more constant DC bias at the input to the VCO and, therefore, a more stable output center, or carrier, frequency from the PLL during open loop modulation.

Abstract: An analog voltage comparator for suppressing an input voltage offset is described. The voltage comparator includes: a first and a second input comparator, both operating in opposite phases, and third comparator coupled to the two input comparators. The circuit further includes a first switch connected a first capacitor coupled to a negative input of the first comparator and to the positive input of the second comparator for alternatively supplying either an input voltage Vi or a reference voltage Vref to the negative and positive input, respectively. It further includes a second capacitor between the positive input of the first comparator and the negative input of the second comparator; a second switch between the negative input and an output of the first comparator; and a third switch between the negative input and an output of the second comparator.

Abstract: A DC offset cancellation circuit receives two input signals. A first one of the input signals is amplified by an amplifier, and the amplified output signal of the amplifier is tracked and held during a first clock phase. Simultaneously, during the first clock phase, the second one of the input signals is tracked and held. During the second clock phase succeeding the first clock phase, the stored second one of the input signals is amplified by the same amplifier that was used to amplify the first one of the input signals. The amplified and stored first one of the input signals and the amplified second one of the input signals are summed during the second clock phase to remove any DC offset. The summed signals are sampled and held during the second clock phase. The offset of the summer circuit can be canceled by sequential digital processing.

Abstract: A linear ramp generating and control circuit finding particular applicability in a time interval measurement system. The linear ramp circuit includes a hold capacitor which may be linearly discharged during one operating mode of the circuit by coupling a constant current source to the capacitor. The voltage on the hold capacitor is linearly discharged away from a baseline voltage level to a data voltage level which is subsequently passed to an analog-to-digital converter of the time interval measurement system for further processing. The hold capacitor voltage is returned to the baseline voltage level during a recovery mode of circuit operation by a recovery or recharge network. The recharge network may include an active-feedback circuit which implements an approximately second-order voltage response to the hold capacitor during the recovery mode of operation.

Abstract: A sample and hold circuit having a single-ended input and a differential output. Switching circuitry operates to couple first and second input capacitors to the single-ended input and to a reference voltage, respectively, when in a sample mode. The switching circuitry also operates in the sample mode to connect a first pair of feedback capacitors between the inputs and outputs of a differential amplifier and to connect a second pair of capacitors between known reference voltages. During the hold mode, the switching circuitry causes the charge present on the input capacitors to be transferred equally to the second pair of feedback capacitors so that the output of the differential amplifier is a differential representation of the single-ended input.

Abstract: An integrated sample-and-hold S/H circuit includes a subthreshold conduction current compensation circuit for reducing undesired effects of subthreshold conduction current in a first field-effect transistor (FET) during the holding time. More particularly, the S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and the first FET. The first FET has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal. The control terminal is responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time and for disconnecting the input signal from the sampling capacitor during a holding time. The first FET preferably further includes a body which unfortunately creates a parasitic diode connected to the sampling capacitor.

Abstract: Heating elements and logic circuits are provided on the base board of a printing head, and noise inhibiting circuit having a hysteresis characteristic are provided between the logic circuits and the input terminals of the base board. The base board, heating elements, logic circuits and noise inhibiting circuits are fabricated by a semiconductor manufacturing process. Each noise inhibiting circuit applies an input signal that enters from an input pad to first and second gates constituted by two MOSFETs having threshold potentials that differ from each other. A flip-flop circuit set or rest by the outputs of the first and second gates is provided on the output side. The noise inhibiting circuit having the hysteresis characteristic is constructed between the threshold potential of the first gate and the threshold potential of the second gate.

Abstract: A MOS track-and-hold circuit incorporating cancellation of error due to switch feedthrough is described. To eliminate the channel charge feedthrough due to oxide capacitance, a switched capacitor source (22) is connected to be charged to a voltage V1 during the "hold" phase and between the input node (12) and the switch gate (17) to provide a voltage V1-Vin during the "track" phase. A dummy transistor (26) biased in an "off" condition has its drain connected to the holding capacitor (15) and its gate switched between ground and the output terminal (Vout which tracks Vin) to also cancel the feedthrough from the gate-drain overlap capacitance and any gate-drain parasitic capacitance.

Abstract: An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.

Abstract: An integrated circuit sample-and-hold (S/H) circuit includes an amplifier offset compensation circuit for compensating for the D.C. offset of a buffer amplifier. The amplifier offset compensation circuit may include an offset determining circuit for determining an offset voltage generated by the buffer amplifier, and an offset correction circuit for generating an offset correction signal and coupling the offset correction signal to the buffer amplifier. The S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and a first field-effect transistor (FET) formed on the substrate. The first FET may have a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the first sampling capacitor during a sampling time and for disconnecting the input signal from the first sampling capacitor during a holding time.

Abstract: In a switched-mode power supply, when the controller and the switching device are encapsulated together with a heat sink, in which the drain of the switching device is connected to the heat sink, the heat sink and the paths to the various pins of the controller forms various parasitic capacitances which, when the switching device switches injects inordinately large currents into the pins of the controller. In the case of the D.sub.MAG input, this may result in throwing the switched-mode power supply out of regulation. The sample-and-hold circuit connected to the D.sub.MAG input includes an additional comparator for comparing the current on the D.sub.MAG input to an extra large current. If the current on the D.sub.MAG input exceeds this extra large current, the sampling switch of the sample-and-hold circuit is held open while a clamp circuit is engaged on the D.sub.MAG input.

Abstract: An integrated S/H circuit includes a first field-effect transistor (FET) formed on a substrate with a sampling capacitor, and a buffer amplifier having an input connected to the sampling capacitor and an output connectable to the body of the first FET. The buffer amplifier thereby reduces undesired effects from a parasitic diode formed by the body and sampling capacitor. More particularly, the first FET preferably has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time, and for disconnecting the input signal from the sampling capacitor during a holding time. The circuit may include one or more switches for connecting the body of the first FET to the output of the buffer amplifier during the holding time to thereby apply a holding voltage from the sampling capacitor to the body of the first FET.

Abstract: A comparator (22) compares the output signal (Vout) supplied by an output amplifier (21) with an input signal (Vin). Dependent on the result of the comparison, it controls the conduction of one or the other of two sources (IGA, IGB) which supply opposite currents. Two complementary assemblies (A, B) each comprise a first transistor (T1A, T1B) and a second transistor (T2A, T2B). Each first transistor (T1A, T1B) has its base controlled by one of the current sources for charging a first capacitance (C1) connected to the output, and also controls the conduction of the corresponding second transistor. The bases of the second transistors (T2A, T2B) are jointly connected to the first capacitance (C1) and their emitters are jointly connected to the negative input of the output amplifier (21). The negative input of the output amplifier (21) is also connected to a reference voltage (Vref) via a resistor (20) and to the output (Vout) via a second capacitance (C2).

Abstract: A very low voltage sampling circuit which is capable of a full ranging output when powered with a very low voltage, e.g., of about 1 volt. A pre-charge circuit is combined with a sample and hold circuit to avoid the need for low threshold switching devices in the sampling circuit, thus avoiding output droop due to the increased leakage of low threshold devices. The pre-charge circuit is placed between the sample and hold circuit and an output of the sampling circuit to `boost` the voltage level of the output of the sample and hold circuit to above a predetermined threshold voltage level. The pre-charge circuit includes an output voltage boost capacitor which is charged before the hold cycle of the sampling circuit. The negative node of the output voltage boost capacitor is charged to a reference voltage, and the positive node is charged approximately to a level of the input signal itself.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A diode for passing the output of a differential amplifier to a holding capacitor is short-circuited in response to a first switching signal, thereby causing the holding capacitor to be discharged through the short-circuiting circuit under control of a second switching signal. The first and second switching signals are generated by delaying a reset signal. The first switching signal is terminated before the termination of the second switching signal.

Abstract: A sample-and-hold circuit is provided for a switched-mode power supply of the type having a transformer with a primary winding, an auxiliary winding and a secondary winding, with a switching transistor coupled in series with the primary winding and a sample-and-hold capacitor for storing a voltage proportional to an output voltage of the auxiliary winding and coupled to a controlled terminal of the switching transistor in a feedback loop which normally operates in a closed-loop mode for switchably regulating the power supply. To prevent the feedback loop from being driven to an open-loop or "stuck" mode of operation, a discharge capacitor is provided which is switchably coupled in parallel with the sample-and-hold capacitor to discharge excess voltage from the sample-and-hold capacitor and thereby restore the feedback loop to its normal closed-loop operating mode.

Abstract: A signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a time multiplexed integrating amplifier circuit in which the output circuit is a pipelined sample and hold circuit which provides time multiplexed input signal samples and the feedback integration capacitor is discharged between samples. At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.

Abstract: A correlated double sampling circuit comprising an input node comprising a first plate of input capacitor and an output node. A first plate of a feedback capacitor is connected to the output node and a second plate of the feedback capacitor is connected to a second plate of the input capacitor. An input transistor has a gate connected to the second plate of the input capacitor, a source connected to a first supply voltage rail, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. A reset transistor is connected between output node and the second plate of the input capacitor, and has a gate connected to a reset signal line.

Abstract: A circuit provides a restart signal to indicate a zero crossing of a continuous varying signal. A zero phase signal is generalized based on a zero crossing of the continuous varying signal. The continuous varying signal is sampled and held in accordance with the zero crossing. The continuous varying signal is converted to complementary signals, and these complementary signals are in turn converted to a signal appropriate for CMOS circuits.

Abstract: A signal integrator stabilization circuit comprises an operational amplifier functioning as a comparator. The circuit further comprises an attenuator in the amplifier's feedback, thereby generating a feedback signal which is sampled to produce a sampling signal. The integrator is driven with a preselected ratio of the feedback signal and the sampling signal to produce a stabilized output signal approaching a zero value which has a good DC stability without compromising the ability to accurately integrate high frequency signals.

Abstract: A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.

Abstract: A low-power differential switching amplifier (200, 210, 220, 230) is provided which utilizes a unique technique of generating interlaced ramps. The interlacing of the ramps causes the ramp discharge time to be effectively zero, which produces exceptionally accurate sawtooth waveforms with virtually no distortion. The timing of the differential switching amplifier circuitry can be synchronized with an external clock. A voltage null point is produced in the differential amplifier where zero voltage at the input of the amplifier produces essentially zero power dissipation within the load, even if the load is low-Q or substantially resistive. Also, by use of a phase balancing technique, residual errors resulting from component mismatches, which would otherwise have imposed power losses upon the load, are nulled out automatically during the operation of the amplifier.

Abstract: A source driver circuit device for decreasing a gap of output errors of a plurality of driver circuits which perform a serial/parallel conversion of a video signal, comprises a plurality of sample-and-hold circuits arranged in the order for sequentially sampling levels of an input video signal; a plurality of signal output circuits for respectively generating voltage outputs corresponding to holding levels of said plurality of sample-and-hold circuits; a plurality of reference level sample-and-hold circuits each of which is provided with each predetermined number of said sample-and-hold circuits, and for sampling a reference level; a plurality of sample value output circuits for respectively generating voltage outputs corresponding to holding levels of said plurality of reference level sample-and-hold circuits; and an output error correction circuit for performing an output level correction in each of said plurality of signal output circuits on the basis of a level difference between said reference level and

Abstract: A frequency-to-current converter includes several capacitances with capacitive values that are effectively multiplied. After each of a series of periodic pulses, the voltage on a "ramp" capacitance is charged to a starting voltage. Then, during the period preceding the subsequent pulse, the ramp capacitance is allowed to discharge at a discharge rate that is a function of a voltage on a discharge-current bias capacitance. At the end of the period, the voltage on the ramp capacitance is sampled and compared to a reference. If the voltage on the ramp capacitance is too low or too high, indicating a discharge current that is too high or too low, respectively, the bias voltage on the bias capacitance is adjusted to compensate for the error. In another embodiment, a small ramp capacitance is repetitively charged and discharged between two reference voltage levels using alternating charge and discharge current levels.

Abstract: A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both samples and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus.

Abstract: An active matrix liquid crystal drive circuit comprising an input-signal storage capacitor for storing an analog input signal, a differential amplifier which alternately presents a first operative state in which the output thereof is returned to the inverting input terminal thereof in a negative feedback manner and a second operative state in which the output is returned to the non-inverting input terminal thereof through a polarity inverting output buffer circuit in a negative feedback manner, and an output-voltage storage capacitor for storing an output voltage of the differential amplifier. In the first operative state, the voltage stored in the input-signal storage capacitor is applied to the non-inverting input terminal, and the output voltage which is returned to the inverting input terminal in a negative feedback manner is stored in the hold capacitor.

Abstract: A computational circuit which has a capacitive coupling for weighted addition. Addition is performed by the capacitive coupling. By connecting and disconnecting capacitances of the capacitive coupling, multiplication can be executed by changing the weights of the capacitors. An inverter with a feed back capacitance is connected to a computational circuit to improve the accuracy of the computation.Capacitances consist of unit capacitances of scattered distribution, so that the deviation of the capacities is minimized.

Abstract: A track-and-hold circuit that utilizes the negative of the input signal to improve tracking of the input signal during the track mode. By applying the negative of the input signal to an amplifier node to which the output signal is coupled, the output signal is forced to track the input signal in magnitude and polarity. Single-ended and fully differential embodiments of the circuit are disclosed, as well as embodiments using an operational amplifier and a cascode inverter amplifier. An improved switching scheme reduces delay in the transition from the hold mode to the track mode. A sample-and-hold circuit may be constructed from a pair of the track-and-hold circuits.

Abstract: A signal processing apparatus comprising a signal holding circuit to hold an input signal from a signal source, a coupling capacitor provided on the signal source side, a connecting circuit to selectively connect the coupling capacitor and the signal holding circuit, and an adding circuit to add the input signal from the signal source on the basis of the signal held in the signal holding circuit. The adding circuit includes a buffer circuit and a switch to selectively connect the buffer circuit and the output side of the coupling capacitor.

Abstract: A read channel especially suited for disk drives, the read channel having auto-zeroing and offset compensation operative with sufficient speed to allow powering-down much of the read channel electronics between servo fields when a read operation is not being executed, is disclosed. Auto-zeroing is accomplished by temporarily shorting what would have been the signal received from a pre-amplifier, and charging capacitors in feedback loops temporarily switched in-circuit in the various circuits being auto-zeroed. After auto-zeroing, any remaining offset, including that imposed by an analog-to-digital converter converting the analog read signal to digitized samples of the read signal, is removed by filtering the digitized read signal samples by a digital filter acting as a low pass filter (integrator and lossy integrator in the embodiment disclosed), and reconverting the digital output of the filter to analog form for subtraction from the input to the analog-to-digital converter.

Abstract: The signals to be measured are transformed in the system to discrete time digital signals by synchronous sampling. These digital signals are then processed by a digital signal processor for vector detection and for computing digital feedback sent to the sampling gates. The analyzer has improved characteristics in the area of linearity, drift and test port signal injection because of its highly optimized architecture based on synchronous sampling with digital feedback. It possesses unique characteristics such as the ability to tune to a harmonic or a subharmonic of the excitation frequency and a good sensitivity in a high impedance environment.

Abstract: A sample hold circuit comprises a first transistor having its base connected to an input terminal and its collector connected to a voltage supply terminal, series-connected first and second diodes having a cathode of the first diode connected to an emitter of the first transistor, a first constant current source having its one end connected to an anode of the second diode circuit and its other end connected to the voltage supply terminal, a first differential circuit including a first branch connected to the emitter of the first transistor and a second branch connected to the anode of the second diode, a third diode having its cathode connected to the anode of the second diode, a second transistor having its base connected to a connection node between the second diode and the third diode and its collector connected to the voltage supply terminal, a second differential circuit including a first branch connected to the voltage supply terminal and a second branch connected to an emitter of the second transistor,

Abstract: A sample circuit (10) maintains linear operation over frequency. A switchable diode bridge (12) passes the analog input signal when enabled to one terminal of a sample storage capacitor (14). The second terminal of the capacitor is coupled through a closed FET switch (16) to a reference node (18). Once the analog input signal is stored across the capacitor, the FET switch opens before the diode bridge disables. When the second terminal of the capacitor floats and prevents any further charge from altering the sample voltage across the capacitor. When the diode bridge is disabled, the sample voltage across the capacitor does not change. The sample voltage may be amplified and digitized for further processing in the cellular system.

Abstract: A sample-and-hold circuit comprises a first buffer stage, a first sampling switch, a sampling capacitor, and a feedback output amplifier for supplying a sampled output signal (Uout). The sampling capacitor is connected to an output of a second buffer stage, which has an input connected to earth. The output amplifier receives feedback via a third buffer stage and a second sampling switch and via a fourth buffer stage and a second sampling capacitor, which together with the first sampling switch are controlled by the same clock signal. The first sampling switch gives rise to clock feedthrough at the non-inverting input of the output amplifier. This clock feedthrough is cancelled by an equal clock feedthrough at the inverting input, so that the sampled output signal is freed from undesired clock feedthrough.

Abstract: A signal conditioning apparatus useful in applications, such as automotive applications, having a signal conditioning circuit capable of conditioning a sensor input signal and providing an output useful, for example, to a fuel-air mixture control system. The signal conditioning circuit employs an amplifier with a feedback impedance, NMOS and PMOS transistors, an input impedance, a detection impedance, input terminals coupled to a sensor. The sensor, such as an oxygen sensor, has a sensor output referenced to sensor ground and input terminals coupled to a power supply and power supply ground. The signal conditioning circuit utilizes switched impedances to provide an output voltage proportional to the differential voltage between the sensor output voltage and the sensor ground when an impedance between the signal conditioning circuit input terminals is low relative to the detection impedance.

Abstract: An improved sample and hold circuit utilizing a buffer circuit to reduce the effective resistance of the switches used to couple an input signal to storage capacitors. The effective resistance of the switches are reduced by placing the switches within the feedback path of the buffer. The buffer may be shared among multiple sample and hold circuits.

Abstract: A sample and hold circuit has an analog switch, a hold capacitor, a voltage-follower type operational amplifier, and a ringing cancel circuit. The ringing cancel circuit is interposed between a non-inverted input terminal of the operational amplifier and a signal ground so that the ringing cancel circuit is connected in parallel with the hold capacitor. The ringing cancel circuit is made up of a resistance and a capacitor connected in series with each other. With this arrangement, a high-speed, highly accurate, low power consumptive sample and hold circuit can be realized.

Abstract: Offset-compensated sample and hold arrangement to sample an input signal comprising at least an operational amplifier (A), a first capacitor (C1), a second capacitor (C2), a first switch (S110), a second switch (S211), a third switch (S210), a fourth switch (S111), a fifth switch (S120), a sixth switch (S121), a seventh switch (S220) and an eighth switch (S221), which switches capacitors and operational amplifier are interconnected in such a way and may be switched in such a way that during an offset-compensation phase the output voltage will only experience a very small voltage change.

Abstract: An input terminal is connected to bases of first and second transistors. Collectors of the first and fourth transistors are connected to a power-source terminal. Collectors of the second and third transistors are grounded. A base of the third transistor is connected to an emitter of the first transistor. A base of the fourth transistor is connected to an emitter of the second transistor. One terminal of the capacitor is grounded and the other terminal thereof is connected to emitters of the third and fourth transistors and an input of an output buffer whose output is connected to an output terminal. A collector of a fifth transistor is connected to the power-source terminal and a base thereof is connected to the output terminal. A collector of a sixth transistor is grounded and a base thereof is connected to the output terminal. A first constant-current source is connected to an emitter of the fifth transistor and a base of the fourth transistor.

Abstract: A discrete-time signal processing system includes a signal sampling circuit controlled by a sampling signal generator in which a clock signal is derived from an oscillation signal having a higher frequency by means of a switchable frequency divider which is driven by a sigma-delta modulator. By alternately switching from one dividend n to the other dividend n+1 and vice versa, an effective dividend m, where n.ltoreq.m.ltoreq.n+1, is realized, so that a very fine frequency tuning can take place. The use of the .SIGMA.-.DELTA. modulator is advantageous in that the frequency spectrum of the sampled signal is not corrupted by the frequency spectrum of the sampling signal (clock signal) generated by way of the switching frequency divider.

Abstract: The present invention is a closed loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals.

Abstract: A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output.

Abstract: An output circuit is intended to be connected to any one of the circuits of a positive logic and a negative logic without having to initialize such a device as a register connected thereto. The output circuit is arranged to output a signal from a first logic circuit to a second logic circuit so that the first logic circuit is connected to an internal input terminal and the second logic circuit is connected to an external output terminal of the output circuit. The output circuit includes a logic state checking unit, a state storing unit, and a logic converting unit. The logic state checking unit serves to check the logic state of the external output terminal when initializing the first logic circuit. The state storing unit stores the checked logic state. The logic converting unit serves to compare the stored logic state of the output terminal with a logic state of a signal at the input terminal sent from the first logic circuit and determine the logic level of a signal to be fed to the second logic circuit.

Abstract: A sample-and-hold circuit, capable of charging and discharging its holding capacitor quickly regardless of a voltage of an analog input signal and an output impedance of an analog driving source, includes a pre-sampling capacitor and at least one CMOS inverter. Before the holding capacitor holds the sampled signal, the pre-sampling capacitor stores the signal level of the analog input signal, and then the CMOS inverter charges and discharges the one side of the holding capacitor according to the stored voltage in the pre-sampling capacitor. Since the one side of the holding capacitor is charged and discharged by the CMOS inverter thus controlled, the sample-and-hold circuit can operate with high speed and handle a wide range of the analog input signal.