Abstract: The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.

Abstract: A power supply apparatus for a radio frequency power amplifier (RFPA) is provided, where the output end of a voltage controlled voltage source (VCVS) and the output ends of N current controlled current sources (CCCSs) are coupled in parallel to supply power to the RFPA. The apparatus further includes an nth sampling unit, configured to sample the sum of the output currents of the first (n?1) CCCSs and the VCVS to obtain an nth sampling signal; and an nth filtering unit, configured to filter the nth sampling signal according to a predefined nth passband and output the filtered nth sampling signal to an nth CCCS, thus controlling the output current of the nth CCCS. The nth passband is higher than an (n?1)th passband. The switching frequency of the nth CCCS is higher than the switching frequency of an (n?1)th CCCS. N is an integer greater than or equal to 2, and n is a positive integer smaller than or equal to N.

Abstract: Examples of systems and methods are provided for tracking-and-holding an input signal. The system may produce a pair of differential voltage outputs responsive to a pair of differential voltage inputs. The system may couple, in response to a clock signal, an input amplifier circuit to an output circuit or decouple the input amplifier circuit from the output circuit. The system may couple the input amplifier to an electrical ground. The system may track values of a pair of differential voltage outputs when a switching circuit is in a closed position and to hold the values of the pair of differential voltage outputs constant when the switching circuit is in an open position.

Abstract: For a semiconductor integrated circuit device such as AFE including a CDS amplifier, in case of excessive signal input to the CDS amplifier, a technique capable of preventing the response characteristic of the CDS amplifier from deteriorating is provided. In the AFE including the CDS amplifier, the CDS amplifier is prevented from becoming saturated by detecting an excessive signal input and triggering the reset of the CDS amplifier. Thereby, no abnormality occurs in the transient response of the CDS amplifier. Specifically, comparison of input signals to the CDS amplifier is performed by a comparator and the CDS amplifier is reset by a reset circuit (by fixing the input terminals of the CDS amplifier to a constant voltage) in case of excessive signal input, so that the CDS amplifier will not amplify excessive signal inputs.

Abstract: Provided is voltage/current conversion circuit including: first and second capacitors; first and second resistors each connected to input terminal; first and second current sources; third and fourth resistors connected to current sources; differential amplifier for controlling the current sources; control unit for performing control, in first state, the input terminal is connected to the first and second capacitors; one input of the differential amplifier is connected to the first resistor and output of the first current source; the other input of the differential amplifier is connected to the second resistor and output of the second current source, and in second state, the second capacitor is connected between the output of the first current source and the one input of the differential amplifier, the first capacitor is connected between the output of the second current source and the other input of the differential amplifier.

Abstract: Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal.

Abstract: A comparator includes a plurality of switches, a capacitor, an amplifier, and a latch. The switches provide an input signal during a first period and provide a reference signal during a second period. A first switch among the switches is composed of a first transistor. The capacitor receives the input signal during the first period and receives the reference signal during the second period. The amplifier is coupled to the capacitor for receiving a difference voltage between the input signal and the reference signal and amplifies the difference voltage during the second period to generate an amplified result. The determining circuit provides a digital signal according to the amplified result.

Abstract: Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.

Abstract: A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

Abstract: A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode.

Abstract: An interface circuit for a multi-differential embedded-clock channel for communicating data provides efficient utilization of the bandwidth of the channel. The interface circuit includes at least four first signals, at least four second signals, and a multi-differential amplifier. The multi-differential amplifier is coupled to the first and second signals. The multi-differential amplifier is adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals. Each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.

Abstract: A sample and hold circuit is disclosed that provides longer hold times. The sample and hold circuit can be used in a disc drive to provide improved read-to-write and write-to-read mode transitions. The sample and hold circuit has an input and an output, and includes at least one capacitive element for retaining a charge. The capacitive element is connected to a node between the input and the output. The sample and hold circuit includes at least one input switch to selectively connect the capacitive element to the input and at least one output switch to selectively connect the capacitive element to the output. In addition, an amplifier is connected to the node and has an offset voltage. In this manner, a voltage drop across at least one of the input and output switches is limited to the offset voltage.

Abstract: In a circuit arrangement including a sample-and-hold device, the sample-and-hold device includes a first, a second, a third and a fourth charge store, and also a first and a second input terminal for feeding in a differential input signal comprising a first and a second component. A differential output signal is output via a first and a second output terminal. The charge stores are charged with the first or the second component of the differential input signal in a first phase of a time segment. In a second phase of the time segment, the differential output signal is generated in a manner dependent on the charges of the first, second, third and fourth charge stores.

Abstract: There is provided a switched capacitor circuit and a pipeline A/D converter which are capable of suppressing electric power from being increased by utilizing a level-shift capacitor, even in a case where the switched capacitor circuit and the pipeline A/D converter are configured by utilizing a CLS technique. In the estimate phase, the capacitor Cc1 (level shift capacitor) is connected between the output terminal of the operational amplifier AMP2 and the inverting input terminal of the operational amplifier AMP2, so as to sample the output from the operational amplifier AMP2, and also to compensate the phase of the operational amplifier AMP2. Additionally, in the level shift phase, the capacitor Cc1 is connected between the output terminal of the operational amplifier 4 and the output terminal Vb, so as to be used to level-shift the output of the operational amplifier AMP2.

Abstract: Disclosed is a sample and hold circuit including a differential circuit, an amplifier stage and a sampling voltage supply circuit. The differential circuit includes first and second capacitance elements, electric charge of which is distributed by a first switch, a first MOS transistor having a gate connected via a second switch to one end of the first capacitance element and also connected via a third switch to an output terminal, and having a source connected to a first current source, a second MOS transistor having a gate connected to one end of the second capacitance element and having a source connected to a second current source and also connected via a forth switch to the source of the first MOS transistor, and a load circuit connected between the drains of the first and second MOS transistors and a terminal of a second power supply. The amplifier stage receives an output of the differential circuit and has an output connected to the output terminal.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A low-power switched-capacitor circuit is disclosed. The low-power switched-capacitor circuit includes a p-channel switched-capacitor integrator and an n-channel switched-capacitor integrator. The p-channel switched-capacitor integrator includes a first set of input transistors controlled by a first set of capacitors and switches. The n-channel switched-capacitor integrator includes a second set of input transistors controlled by a second set of capacitors and switches. The p-channel switched-capacitor integrator and the n-channel switched-capacitor integrator function together in a push-pull fashion such that a required transconductance as well as width and drain current of the first and second sets of input transistors are reduced by half of those in a conventional switch-capacitor circuit.

Abstract: A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier.

Abstract: A switched capacitor sample-and-hold circuit using a source grounded input operational amplifier, wherein a feed forward circuit or a feedback circuit is provided in the operational amplifier and connected to the feedback capacitor of the operational amplifier via switches, an input common voltage or a middle point voltage of outputs is detected, and a difference of the same from a reference voltage is previously charged in the feedback capacitor, thereby suppressing fluctuation of an output operation point at the time of amplification of the operational amplifier.

Abstract: A sample and hold circuit includes an op-amp, inverting-side capacitors, and non-inverting-side capacitors paired with the inverting-side capacitors. At least one capacitor pair serves as a feedback capacitor in a holding phase. A total capacitance of the inverting-side capacitors to which an input voltage is applied in a sampling phase is ?, a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is ?, a total capacitance of the inverting-side capacitors to which the input voltage is applied in a holding phase is ?, and a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is ?. ? is substantially different from ?. A total capacitance of a feedback capacitor pair is substantially equal to (?????+?)·(N/2), where N is a positive number.

Abstract: An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S1) coupled between the input node (Vin) and the sampling capacitor (C) for connecting the input node (Vin) to the sampling capacitor (C). There is also a voltage follower with an input coupled to the sampling capacitor (C). The first switch (S1) includes a first MOS transistor (NM1) coupled between the input node (Vin) and the sampling capacitor (C). The first MOS transistor has a bulk. The sample and hold stage is adapted to selectively couple the bulk to a node having a voltage level (V3) which is equal or close to the voltage level at the input node of the voltage follower.

Abstract: A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively.

Abstract: A track-and-hold peak detector circuit, which can operate at low input signal frequencies, includes a capacitor to hold a peak voltage of the input signal and logic circuitry that reduces an effect of leakage current into or out of the capacitor, and therefore, provides protection against self-switching of an output signal of the peak detector circuit.

Abstract: Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.

Abstract: Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

Abstract: A compensating circuit for calibrating reference voltage, which is coupled to an operation amplifier having an input end and an output end within a reference voltage driving circuit, is provided in the present invention. The compensating circuit comprises a first capacitor, a second capacitor, and a first switch. The first capacitor is utilized for storing the potential with respect to the reference voltage. The second capacitor is coupled to the operation amplifier for storing the potential difference between the input end and the output end of the operation amplifier. The first switch is electrically connecting to the first capacitor and the second capacitor. When turning on the first switch, the potentials stored in the first capacitor and the second capacitor are combined and input to the operation amplifier to have an output voltage level substantially identical to the reference voltage.

Abstract: A single-ended, non-differential switched capacitor circuit is disclosed which removes the effect of common mode noise. To this end, the circuit creates a capacitance divider using the sampling capacitors, Cs, to create a stable and noise-free common mode voltage (Vcom) signal. Once created, this Vcom signal is coupled across a large common mode capacitance, Ccom, which is preferably off chip, to further control its value. Thereafter, the voltage Vcom is preferably allowed to settle while the data is disconnected. In this way, the Vcom signal is not provided to the circuit, but instead is cleanly generated within the circuit itself when needed. Thereafter, the generated Vcom signal is paralleled with the integration capacitor, C1, to produce the non-differential output voltage Vout. Then, the sampling capacitors, Cs, are shorted to remove any charges stored on them and the process is repeated.

Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.

Abstract: Methods and apparatuses for detecting digital signals in high speed signaling systems. In at least one embodiment, at least one received input signal is combined with a plurality of predetermined reference signals according to a plurality of prior digital signal output states to generate a signal for detecting a present digital signal output state. In one aspect of the invention, a method for determining a digital signal state in a differential signaling system includes: comparing a first differential input signal to a second differential input signal; determining a prior digital signal output state; comparing the first differential input signal to one of a first reference voltage and a second reference voltage; comparing the second differential input signal to one of the first reference voltage and the second reference voltage; and determining a present digital signal output state from the prior digital signal output state and from all of the comparisons.

Abstract: An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost circuit to maintain the impedance of a sampling switch contained in a signal dependent boost switch substantially constant. The output of the second amplifier is sampled via the sampling switch, and the sample is stored in a storage element. The second amplifier drives a reduced load, and may be implemented as a low bandwidth, low power amplifier to reduce overall power consumption.

Abstract: A transistor switch circuit includes: a MOS transistor in which a channel is formed when a gate-source voltage is zero; and a voltage supply part which is connected to a gate of the MOS transistor to supply the gate with a voltage for turning off the MOS transistor.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: An analog signal transmission circuit includes a sampling switch supplied with an analog signal, a capacitor connected between an output side terminal of the sampling switch and a low-potential power supply, and a differential amplifier connected to an output side terminal of the sampling switch. The circuit samples the analog signal by turning on/off the sampling switch and outputs a signal achieved by amplifying an accumulation voltage of the capacitor in the differential amplifier. The differential amplifier has a differential input portion including a first transistor connected to a first terminal of the capacitor, a second transistor, a constant current source, and an actuating switch that is connected between the constant current source and the differential input portion. The analog signal transmission circuit further includes a pre-charge circuit that pre-charges a wire between the different input portion and the actuating switch.

Abstract: A signal sampling apparatus for generating an output signal according to an input signal is disclosed. The signal sampling system includes a sample and hold circuit and a gain controller. The sample and hold circuit is used for sampling the input signal to generate a sample signal in a sample mode, and the sample and hold circuit includes an amplifier having a gain for generating the output signal according to the sample signal in a hold mode. The gain controller is coupled to the amplifier for adjusting the gain in the sample mode.

Abstract: A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.

Abstract: An interface capable of suppressing parasitic capacitance effects includes an array of switches switched in response to a switching signal. The interface suppresses effects of parasitic capacitance included in a bus, which transmits a reset signal and an image signal output from an image sensor. The suppressed parasitic capacitance effects suppress distortion of a digital image signal.

Abstract: A sample-and-hold circuit including a first switch, a first capacitor and an amplifier is provided. The switch has a first terminal to receive the input signal and transmit it to a second terminal thereof in the sample period. The first terminal of the first capacitor couples to the second terminal of the first switch, and the second terminal of the first capacitor couples to a first voltage for storing the sampling result of the input signal. The amplifier couples to the second terminal of the first switch, wherein the amplifier is disabled in the sample period, and the amplifier is enabled to generate the output signal according to the sampling result in the hold period.

Abstract: A sample hold circuit includes an op-amp, first capacitors provided on an inverting side of the op-amp and second capacitors provided on a non-inverting side. The sample hold circuit is configured such that a total capacitance of the first and second capacitors to which an input voltage is applied in a sampling phase is equal to that of the first and second capacitors to which the input voltage is applied in a holding phase, a total capacitance of the first capacitors to which the input voltage is applied in the holding phase is equal to that of the second capacitors to which the input voltage is applied in the holding phase, and a total capacitance of the first capacitors to which the input voltage is applied in the sampling phase is different from that of the second capacitors to which the input voltage is applied in the sampling phase.

Abstract: A current monitoring circuit for DC-DC switching converters includes a track and latch comparator circuit (30) having a preamplifier (32) that is controlled independently of a latch circuit (34). The comparator is small and operates very fast and with improved sensitivity. For example, the preamplifier circuit is disabled when the latch stage is making its decision to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature speeds up the signal processing of the comparator and allows it to work in parallel with other circuits. The latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.

Abstract: A wide linear range peak detector including first and second peak detectors and a compensation circuit. The first peak detector receives an input signal and has an output providing a first peak signal approximation which approximates a peak level of the input signal. The first peak signal approximation includes a non-linear portion which is a function of the peak level of the input signal. The second peak detector also receives the input signal and has an output providing a second peak signal approximation. The compensation circuit uses the second peak signal approximation to provide a compensation signal which compensates the non-linear portion of the first peak signal approximation. In particular, the second peak signal is used to generate the compensation signal to approximate and cancel the non-linear portion.

Abstract: First and second analog switches are connected in series between first and second nodes. One terminal of a third analog switch is connected to a series connection node of the first and second analog switches. The other terminal of the third analog switch is supplied with a second voltage different from a first voltage applied to the first node. The third analog switch drives on when the first and second analog switches drive off, and outputs the second voltage to the series connection node of the first and second analog switches.

Abstract: Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an integration capacitor connected between the non-inverting input and the output. An input voltage is sampled at a first rate onto an input sampling capacitor and then charge is dumped from the input sampling capacitor to the non-inverting input of the amplifier at a second time and at the first rate. A reference voltage is sampled onto a feedback sampling capacitor at substantially the first rate, and charge stored on the feedback sampling capacitor is dumped to the non-inverting input of the amplifier at a second rate different than the first rate.

Abstract: A track and hold circuit (1) comprising:—a linear amplifier (2) receiving a differential analog signal (D+, D?) and being controlled by a first binary clock signal (H+) having a first phase,—the linear amplifier (2) providing a feed-forward input signal substantially equal with the differential analog signal (D+, D?) to a pseudo latch circuit (3) in the first phase of the first binary clock signal (H+), said pseudo latch circuit (3) being controlled by a second binary clock signal (H?) for memorizing the input signal and providing a differential output signal (LD+, LD?) substantially equal with the input signal during a second phase of the first binary clock signal (H?), the second binary clock signal being substantially in antiphase with the first binary clock signal (H+).

Abstract: A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull operation. According to some embodiments, the switched capacitor buffer displays an optimal combination of design simplicity, low power consumption and high-frequency response.

Abstract: A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provide the first and third comparator circuits with symmetrical offsets.

Abstract: A switched-capacitor circuit for sampling a pair of differential input signals includes a first bootstrapped switch and a first non-boosted switch connected in parallel between a first output terminal of an amplifier and a first feedback node of the switched-capacitor circuit to form a first feedback signal path and a second bootstrapped-switch and a second non-boosted switch connected in parallel between a second output terminal of the amplifier and a second feedback node of the switched-capacitor circuit to form a second feedback signal path. The first and second non-boosted switches are controlled by a first clock signal and the first and second bootstrapped switches are controlled by a second clock signal where the second clock signal is the first clock signal delayed by a predetermined amount.

Abstract: A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output stage and switchable bias current source. The first switch and the first capacitor are coupled in series between input signal and first voltage, and a common node is coupled to a first positive input terminal of the amplifier. The first switch is on during first period and off during second period. The second switch and the second capacitor are coupled in series between the input signal and second voltage, and a common node is coupled to a second positive input terminal of the amplifier. The second switch is on during second period and off during first period. The switchable bias current source biases the second input stage during first period, and switches to bias the first input stage during second period.

Abstract: A compensating circuit for calibrating reference voltage, which is coupled to an operation amplifier having an input end and an output end within a reference voltage driving circuit, is provided in the present invention. The compensating circuit comprises a first capacitor, a second capacitor, and a first switch. The first capacitor is utilized for storing the potential with respect to the reference voltage. The second capacitor is coupled to the operation amplifier for storing the potential difference between the input end and the output end of the operation amplifier. The first switch is electrically connecting to the first capacitor and the second capacitor. When turning on the first switch, the potentials stored in the first capacitor and the second capacitor are combined and input to the operation amplifier to have an output voltage level substantially identical to the reference voltage.

Abstract: The invention relates to an active current mode sampling circuit comprising an operational amplifier (103) and at least one switched capacitor (C2, C2a, C2b). In order to reduce the power consumption of such a circuit, first switching elements (S101a, S101b, S102a, S102b) switch the switched capacitor (C2, C2a, C2b) between an input and an output of the operational amplifier (103) during charging phases ?1. Further, second switching elements (S103a, S103b, S104a, S104b) connect the switched capacitor (C2, C2a, C2b) during discharging phases ?2 to a subsequent stage (104), in order to provide a charge of the switched capacitor (C2, C2a, C2b) to the subsequent stage (104). The invention relates equally to a device (107) comprising such a sampling circuit and to a method of operating such a sampling circuit.