Abstract: A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching between a fast clock signal input to the counter and a slow clock input to the counter. The counter is always on and increases its count by an appropriate rational number of counts representing fast clock cycles for every cycle of the fast clock while in a fast clock mode, and by an appropriate rational number of fast clock periods for every cycle of the slow clock signal while in a slow clock mode.

Abstract: An integrated circuit device includes at least a functional module arranged to receive a reference clock signal; a gating component configurable to perform gating of the reference clock signal; and a synchronization module. The synchronization module includes a trigger component arranged to receive a request for the functional module, the request being asynchronous with the reference clock signal, and to set an enable signal for the functional module in response to receiving the request therefor; and a synchronization component arranged to receive the enable signal, and in response to the enable signal being set to: configure the gating component to un-gate the reference clock signal; and synchronize an initial clock cycle of the reference clock signal received by the functional module following the reference clock signal being un-gated.

Abstract: A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.

Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Abstract: A pulse edge selection circuit includes an input stage which selects and passes one clock from among a plurality of clocks and an output stage which outputs the clock to an edge detection circuit. The output stage has a combination of a plurality of NOR gates and a plurality of NAND gates, which are connected alternately, both the NOR gates and NAND gates having a plurality of input terminals. If the edge detection circuit is a type which detects falling edges of clocks and generates a pulse which rises on the falling edge of a first clock and falls on the falling edge of a second clock, a NOR gate is used as an output gate which outputs the first clock and the second clock. On the other hand, if a pulse is generated on rising edges, a NAND gate is used as an output gate.

Abstract: A glitchless clock multiplexer controlled by an asynchronous select signal for use in GPS receivers is disclosed. A device in accordance with the present invention comprises a device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources.

Abstract: The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output command signal as its output. The apparatus further includes a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, the multiplexer being operable to route one of the first and second output command signals to its output in response to the control signal.

Abstract: Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

Abstract: An apparatus for interleaved phase shift clock synchronization includes a master clock generator and at least one slave clock generator. The master clock generator provides a ramp signal or reset signal for each slave clock generator to generate a clock synchronized with the clock of the master clock generator, and the master and slave clock generators have different reference voltages for generating clocks. Therefore, the clocks generated will be synchronized and interleaved phase with each other.

Abstract: A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

Abstract: Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.

Abstract: A method and apparatus for providing system clock failover using a one-shot circuit are disclosed. A process, in one embodiment, is able to detect a clock failure using a one-shot circuit, wherein the clock signals are generated by a first clock circuit. Upon generating a switching signal in response to the clock failure, a system reset signal is asserted for a predefined time period in accordance with the clock failure. After switching a second clock circuit to replace the first clock circuit, the process is capable of resuming the clock signals via the second clock circuit.

Abstract: This invention relates to a system for processing redundant signals, an associated method, as well as an aircraft comprising such a system, from a viewpoint of monitoring and passivation of erratic or oscillating failures affecting the sources of these redundant signals. The system comprises a module for calculation of a current useful signal from redundant signals; a monitoring/passivation module, able to detect an erroneous signal and to exclude the said erroneous signal from the calculation according to a criterion; and a means for toggling, as soon as an erroneous signal is detected, to a freeze mode freezing the output useful signal, and for returning, as soon as an erroneous signal no longer is detected, to a transmission mode where the current useful signal is transmitted as output useful signal.

Abstract: A large-scale integrated circuit according to the present invention includes a plurality of functional blocks for independently performing a signal processing operation, and a selection controlling circuit for generating a first control signal to select one of the plurality of functional blocks, in which the selection controlling circuit includes a control signal generating circuit for generating a second control signal for stopping the operation of its circuit, and the selection controlling circuit generates the first and the second control signals by a command from a different control circuit.

Abstract: A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least one clock selector circuit for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.

Abstract: A method of compensating clock skew may include generating (2M+1) detected values by applying (2M+1) delay clock signals to (2M+1) pieces of delay data, wherein M is a natural number, determining a dominant logic value based on a comparison of a number of logic high detected values and a number of logic low detected values from among the (2M+1) detected values, determining a median delay time based on a number of the (2M+1) detected values having the dominant logic value, and adjusting a phase of a clock signal using the median delay time.

Abstract: A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.

Abstract: Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid.

Abstract: A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply voltage to the drive circuit, selects the first voltage and, when supplying a power supply voltage to an internal device, selects the second voltage; and a step-up circuit that, when the first voltage selected by the selector is input, boosts the first voltage to a third voltage and outputs the third voltage as the power supply voltage to the drive circuit and, when the second voltage selected by the selector is inputted, boosts the second voltage to a fourth voltage and outputs the fourth voltage as the power supply voltage to the internal device.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A selector circuit for selecting and outputting plural pieces of output data from input data including plural bits, in which each of the pieces of the output data including plural bits is provided. The selector circuit includes plural first swap circuits, each of the bits of the input data being input to any of the plural first swap circuits, the plural first swap circuits being configured to reorder and output the input bits or output the input bits without reordering; a bus configured to transfer the bits output from the first swap circuits; and plural data field specifying circuits respectively configured to select and take out a predetermined number of continuous bits on the bus. Plural bits taken out by any of the data field specifying circuits are included in the respective pieces of the output data.

Abstract: A distributed signal multiplexer circuit programmably routes electronic signals. The circuit includes at least two distributor subcircuits. Each distributor subcircuit is configured to connect an input port to an output port through a switch, with a state of each switch being controlled by information received at a control port. The first and second distributor subcircuits are part of a first and second power domain, respectively. The distributed multiplexer circuit also includes an aggregator subcircuit. The aggregator subcircuit is configured to have a first input port connected with the output port of the first distributor subcircuit, a second input port connected to the output port of the second distributor subcircuit, and the output port signal being a signal selected from among the signals received at the input ports of the distributor subcircuits.

Abstract: There is provided a clock signal selection circuit including: a first AND circuit (AND_A1) outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit (AND_A2) outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal; a first flip-flop (FF_A2) inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal; and a second flip-flop (FF_B2) inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal.

Abstract: A frequency adjusting method of a CDR circuit and apparatus thereof are provided. The adjusting method is applied to a receiver apparatus connected to an outer apparatus. The outer apparatus, after actuated, sends out an outer data signal to the receiver apparatus according to its operational frequency and a PLL of the receiver apparatus outputs a transmitter clock according to an operational frequency of the receiver apparatus. The CDR circuit of the receiver apparatus generates a receiver clock according to the outer data signal. The CDR circuit is set in a phase mode such that the receiver clock follows transmitting frequency of the outer data signal. Then, a difference between frequencies of the receiver clock and the transmitter clock is checked. If the difference is larger than a threshold value, an operational frequency of the outer data signal is reduced.

Abstract: A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

Abstract: A voltage scale down circuit includes an input node configured to receive a voltage input within an input voltage range. At least two voltage followers are coupled to the input node. The voltage scale down circuit also includes at least two scalers. Each scaler is coupled to a respective voltage follower. An output node is coupled to the at least two scalers. Each voltage follower is configured to receive the voltage input. Each voltage follower is configured to supply a respective voltage for the voltage input within a narrower portion of the input voltage range. The output node is configured to supply a voltage output linearly related to the voltage input. An output voltage range of the voltage output is narrower than the input voltage range.

Abstract: An apparatus and for preventing a glitch in a clock switching circuit includes a select signal manager and a clock gate unit. The select signal manager generates a detect change signal, provides the detect change signal as an input signal for generating a clock gate signal to the clock gate unit, and changes a muxsel signal into a select signal using the clock gate signal to select a clock intending for switching. Upon receiving the detect change signal, the clock gate unit gates a received clock, generates the clock gate signal using a level of the detect change signal as an input signal, and provides the generated clock gate signal to the select signal manager.

Abstract: The present invention is directed to an integrated circuit device that includes a primary signal synthesizer configured to generate a free-running first digital frequency signal and at least one secondary signal synthesizer disposed in parallel with the primary signal synthesizer and configured to generate a free-running at least one second digital frequency signal. A switch element includes a first switch input coupled to the primary signal synthesizer and at least one second switch input coupled to the at least one secondary signal synthesizer. The switch element is configured to select a switch output that provides either the free-running first digital frequency signal or the free-running at least one second digital frequency signal based on a switch control input.

Abstract: A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.

Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

Abstract: Techniques, systems and apparatus are described for providing a voltage selection circuitry and a DC-to-DC converter having such voltage selection circuitry. The voltage selection circuitry includes a first terminal voltage sensing unit that senses a voltage of a first terminal and a second terminal voltage sensing unit that senses a voltage of a second terminal. The voltage selection circuitry also includes a comparison unit connected to the first terminal voltage sensing unit and the second terminal voltage sensing unit. The comparison unit compares the voltage of the first terminal with the voltage of the second terminal and outputs a comparison signal indicating a difference between the sensed voltages of the first and second terminals. The voltage selection circuitry includes a selection unit that selects a higher voltage from the sensed voltages of the first and second terminals in response to the comparison signal.

Abstract: Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

Abstract: Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output. For a limited period of time, a low phase output level is forced. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

Abstract: A switch circuit for switching two clock signals includes a clock generator, a flip-flop and a multiplexer. The clock generator is to generate a reference signal whose cycle is the lowest common multiple of the cycles of the two clock signals. The flip-flop is to generate a selecting signal by taking a control signal from system as an input signal and taking the reference signal as a timing trigger signal. The multiplexer can output a selected clock signal according to the selecting signal in which the selected clock signal and the switched clock signal are synchronous during their entire cycles.

Abstract: Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of the selected input clock signal. Toggle signals are used to control when the output clock signal is to toggle high or low. A latch holds the state of the output clock signal in its current state until changed by receipt of a toggle signal. Switching from use of a first clock signal to use of a second clock signal occurs regardless of whether the first input clock is operating. A delay is introduced that prevents glitches in the output clock signal that are less than one half clock period of the next selected input clock signal in duration.

Abstract: A pulse signal generating device includes: the plurality of encoders each of which outputs an encoder signal with a pulse period corresponding to the speed of an object to be detected; delay amount control unit that controls a relative delay amount with respect to a pulse signal for each of the plurality of pulse output signals output from the plurality of encoders; a detection unit that individually detects abnormalities in pulses of the plurality of encoder signals; a switching unit that performs switching to one pulse output signal, in which pulse abnormalities are not detected, of the plurality of pulse output signals; and a pulse generating unit that generates a pulse signal by delaying the one pulse output signal switched by the switching unit by the corresponding relative delay amount.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply control currents for adjusting a delay amount of the first delay element and a delay amount of the second delay element, and an output signal selecting section configured to select any one of an output signal from the first delay element and an output signal from the second delay element according to a selecting signal for selecting delay time of the input signal.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may calibrate the second clock signal relative to the first clock signal. The clock calibration unit may have a calibration output for outputting a calibrated clock signal. The clock circuit may include a switch unit connected to the first clock input and the calibration output. The switch unit can select a selected clock signal selected from the first clock signal and the calibrated signal. The switch unit has a switch output for outputting the selected clock signal. A switch control unit is connected to the switch unit for controlling which signal is selected based on a selection criterion and a clock circuit output is connected to the switch unit for outputting the selected clock signal.

Abstract: Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.

Abstract: A clock switching circuit comprises PLL circuits into which external clocks CLKT, CLKB are respectively input, a multiplexer for selecting and outputting either an output PLB of one PLL circuit or an inverted signal of an output PLT of the other PLL circuit, and a clock control circuit for subjecting the multiplexer to switching control on the basis of a Lock determination signal that is asynchronous with CLKB and PLB. When the Lock determination signal is input into the clock control circuit, the clock control circuit switches the output of the multiplexer in synchronization with an offset clock PLQB that is offset from the phase of PLB by a predetermined value.

Abstract: A digital signal multiplexor and multiplexing method are provided with which switching between different input signals is achieved without producing glitches in the output signal, even in the event of one or more of the input signals stopping and starting at unknown times.

Abstract: A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.

Abstract: A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal.

Abstract: Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

Abstract: A method and system is provided for clock input mode selection. When a signal provided on one of two clock input terminals is received, the received signal is considered in connection with a second input signal in order to determine whether the first input signal and the second input signal satisfy a pre-determined condition. Based on whether the pre-determined condition is met, a clock input mode is selected that indicates whether the clock input terminals provide a differential clock input or a single-ended digital clock input.

Abstract: A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.

Abstract: A apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

Abstract: There is provided a clock signal selection circuit including: a first AND circuit (AND_A1) outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit (AND_A2) outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal; a first flip-flop (FF_A2) inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal; and a second flip-flop (FF_B2) inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal.