Abstract: Systems, methods and apparatus for wireless charging are disclosed. A charging device has a resonant circuit comprising one or more transmitting coils, a driver circuit configured to provide a charging current to the resonant circuit, a zero-crossing detector configured to provide a zero-crossing signal that includes edges corresponding to transitions of a voltage measured across the resonant circuit through a zero volt level or corresponding to transitions of a current in the resonant circuit through a zero ampere level and an Amplitude Shift Keying demodulator. The demodulator may be configured to receive a plurality of samples of voltage or current in the resonant circuit captured at times determined by the edges included in the zero-crossing signal, and demodulate a modulated signal obtained from the charging current using the plurality of samples of voltage or current in the resonant circuit.

Abstract: A method for determining coarse carrier phase and frequency offsets of an initial block of received M-QAM symbols includes creating a grid of discrete candidate phase offset values and for each candidate value: applying the candidate value to each symbol, applying a respective hard decision to each applied symbol, and computing a figure of merit based thereon. The candidate value having the best figure of merit is selected as an initial phase offset estimate. An initial frequency offset estimate is computed using the symbols updated with the initial phase offset estimate, their respective hard decisions, and an approximation of the complex exponential function. To track carrier phase and frequency offsets associated with a series of symbol blocks, for each symbol of a current block, set a binary trust weight based on comparison of a computed parameter with a threshold and use the binary trust weights to compute a phase offset error and a frequency offset error for the current block.

Abstract: A receive device includes: a quadrature detector; and a first signal detector that detects whether a signal subjected to detection in the quadrature detector is a received signal. The first signal detector assigns the signal subjected to quadrature detection in the quadrature detector to an orthogonal plane divided into a plurality of quadrants and derives an amount of movement of the signal assigned between quadrants, integrates absolute values of derived amounts of movement over a predetermined period of time, and determines whether the signal subjected to quadrature detection is a received signal by comparing an integrated value derived from integration with a threshold value.

Abstract: A demodulator and method includes a plurality of correlation circuits, a result combining stage, and a time combining stage. The plurality of correlation circuits may be configured to output a plurality of correlation values that indicate a likelihood of whether a pattern of a buffered portion of an input data signal matches a first plurality of target frequency behavior patterns. The plurality of correlation circuits may be further configured to output a plurality of delayed correlation values that indicate a likelihood of whether a pattern of a delayed buffered portion of the input data signal matches a second plurality of target frequency behavior patterns, where both the buffered portion and the delayed buffered portion include a current symbol.

Abstract: A rectifier circuit includes an H-bridge circuit, and rectifies an AC current that flows through a reception antenna. A smoothing capacitor smoothes the output of the rectifier circuit. A demodulator demodulates an FSK-modulated electric power signal. A first comparator compares a voltage VAC1 at a first AC input terminal with a first threshold voltage VTH1, and generates a first detection signal. A second comparator compares a voltage VAC2 at a second AC input terminal with a second threshold voltage VTH2, and generates a second detection signal. A clock generating circuit generates a frequency detection clock CLK_OUT that transits according to a predetermined edge type of the first detection signal and a predetermined edge type of the second detection signal. A frequency detection circuit detects the frequency of the frequency detection clock.

Abstract: An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slicer by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a number of total bits and a number of erroneous bits based on the digital output signal and calculating a two-sided bit error ratio frequentist confidence interval (FCI) size from the measured bit error ratio. The measured bit error ratio is output in response to the two-sided bit error ratio FCI being less than or equal to a two-sided bit error ratio interval target size.

Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A channel state information feedback method and apparatus of a terminal (1200) is provided for measuring channel quality and reporting the measurement result to a base station (1300) in the mobile communication system supporting multi-carrier multiple access scheme such as Orthogonal Frequency Division Multiple Access (OFDMA).

Abstract: A method of recovering information encoded by a modulated sinusoidal waveform having first, second, third and fourth data notches at respective phase angles, where a power of the modulated sinusoidal waveform is reduced relative to a power of an unmodulated sinusoidal waveform within selected ones of the first, second, third and fourth data notches so as to encode input digital data. The method includes receiving the modulated sinusoidal waveform and generating digital values representing the modulated sinusoidal waveform. A digital representation of the unmodulated sinusoidal waveform is subtracted from the digital values in order to generate a received digital data sequence, which includes digital data notch values representative of the amplitude of the modulated sinusoidal waveform within the first, second, third and fourth data notches. The input digital data is then estimated based upon the digital data notch values.

Abstract: The techniques described herein relate to methods, apparatus, and computer readable media configured to decode modulated data. A modulated signal is received. A format of the modulated signal is determined, wherein the format can include a first format comprising a first type of modulated signal, or a second format comprising the first type of modulated signal and a second type of modulated signal that is different than the first type. The modulated signal is decoded by determining a frequency shift amount based on the format of the modulated signal, shifting a frequency band of the first type of modulated signal from an original position to a shifted position, thereby shifting a center frequency of the first type of modulated signal by the frequency shift amount, and filtering, based on the format of the modulated signal, signals outside of the frequency band of the shifted first type of modulated signal.

Abstract: The present technology relates to a signal processing apparatus and method which can suppress increase in power consumption. In an aspect of the present technology, control data, which is for controlling frequency modulation to a carrier signal using digital data to be transmitted, and for suppressing a time average of a fluctuation amount of a frequency modulation amount more than a case of controlling the frequency modulation to the carrier signal using the digital data is generated, the frequency modulation is performed to the carrier signal on the basis of the generated control data, and the carrier signal to which the frequency modulation is performed is transmitted as a transmission signal. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, or an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer which controls these.

Abstract: The present application provides a signal demodulation apparatus and method in a closed communication system. The signal demodulation apparatus includes: an analog voltage comparator, configured to convert a received modulated signal into a digital signal, and output the digital signal; and a sampling decider, configured to sample the received digital signal, and acquire a value represented by the digital signal according to a feature of a sampled digital signal to complete a signal demodulation. The present application improves signal-to-noise ratio of pressure detection, reduces power consumption and increases refresh rate. The apparatus and method according to the present application have the advantages of simple structure, easy to implement, small circuit area and low power consumption, and thus are suitable for a scenario imposing strict requirements on the power consumption and area, for example, a wearable device and the like.

Abstract: A method and a highway addressable remote transducer (HART) modem for modulating and demodulating an analog signal including a HART message are provided. With low power consumption, the less computationally intensive HART modem modulates the analog signal using a coherent 8-ary phase shift keying (C8PSK) technique with a predefined gray code lookup table and a pre-generated sample lookup table having phase modulated digital signals indexed by index vectors, and transmits a HART C8PSK analog signal to sensor devices. A C8PSK demodulator in the HART modem demodulates the HART C8PSK analog signal by performing coarse estimation and fine estimation of phase errors and by estimation of a timing offset using a decision estimator. An automatic modulation classifier of the C8PSK demodulator validates presence of the analog signal in a C8PSK protocol by determining signs of in-phase and quadrature phase signals corresponding to each subsequent processed digitized sample of the analog signal.

Abstract: In a transmission apparatus, a mapper maps frequency components of an analog signal at equally spaced discrete locations within a transmission frequency band, a time-division multiplexer time-division multiplexes the analog signal and a preamble signal to generate a transmission signal, the preamble signal being a digital signal whose frequency components are continuously mapped over the transmission frequency band, and a transmitter transmits the transmission signal, wherein an autocorrelation value of the transmission signal being to be used for timing synchronization at a reception apparatus that receives the transmission signal.

Abstract: A method of operating frequency shift keying (FSK) demodulator for demodulating symbols includes providing current and previous buffered portions of an input signal to correlation circuits of the FSK demodulator, where each buffered portion persists for a symbol duration time period. The correlation circuits output first correlation metrics that indicate a likelihood of whether the buffered portions match a respective target pattern. The first correlation metrics are combined into a set of first correlation results, which are delayed by at least the symbol duration time period. The current and next buffered portions are provided to the correlation circuits, which output second correlation metrics that are combined into a set of second correlation results. The set of second correlation results are combined with the delayed set of first correlation results to produce a demodulation decision that indicates a most likely symbol value encoded in the current buffered portion.

Abstract: Disclosed are a method and device for receiving a frequency-shift keying signal. The device for receiving a frequency-shift keying signal includes a front-end circuit, complex differential discriminators, and a recovery circuit. The front-end circuit receives a signal transmitted via a frequency-shift keying channel, and generates the baseband signal of the received signal. The complex differential discriminators have a plurality of orders and use the complex conjugate of the baseband signal of the received signal. The recovery circuit recovers symbols by applying a maximum likelihood sequence estimation (MLSE) technique to the output values of the complex differential discriminators having the plurality of orders.

Abstract: Disclosed are an apparatus and method for compressing continuous data. The apparatus for compressing continuous data may include a data generator configured to calculate differences between adjacent values in original continuous data and generate data based on the calculated differences.

Abstract: A system providing a spread spectrum and a narrowband data transmission may comprise a DSSS transmitter and a DSSS receiver. The DSSS transmitter may convert a bit succession (di) into a chip succession (sk) using a chip sequence (cj, cj?) and send a succession of impulses (s(t)) corresponding to the chip succession (sk). The DSSS receiver may receive impulses (s(t)) sent by the transmitter and filter the received impulses (r(t)) using a filter having an impulse response (x(t)) dependent on the chip sequence (cj, cj?). The chip sequence (cj) may be a spread sequence. The narrowband data transmission may use chip sequence (cj?) and a corresponding impulse response (x(t)) of the filter. The chip sequence (cj?) does not comprise a succession having two directly successive arithmetic sign changes and an arithmetic sign change does not occur after the first and before the last chip in the chip sequence (cj?).

Abstract: A non-transitory computer-readable recording medium on which a program is recorded for a causing a processor to execute a demodulation process. The demodulation process includes detecting a preamble of a wireless signal transmitted from a first transmission station by way of a short wavelength carrier wave, extracting a first signal superimposed on the short wavelength carrier wave, the first signal being extracted from a wireless signal that is identified in accordance with the detection of the preamble, extracting a second signal superimposed on a carrier wave transmitted from a second transmission station, and performing demodulation on a target demodulation signal obtained by superimposing the first signal on the second signal.

Abstract: A frequency shift keying (FSK) demodulator for demodulating symbols includes correlation circuits configured to output correlation metrics based on a buffered portion of an input signal as the input signal is continuously received by the FSK demodulator. The FSK demodulator also includes a result combining stage configured to output a set of first correlation results based on correlation metrics generated for a first portion of the input signal encoding a current symbol and at least one past symbol, and a set of second correlation results based on correlation metrics generated for a second portion of the input signal encoding the current symbol and at least one next symbol; and a time combining stage configured to combine a set of delayed first correlation results with the set of second correlation results to produce a demodulation decision that returns a most likely symbol value for the current symbol.

Abstract: A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.

Abstract: The embodiments described herein provide devices and methods to facilitate ripple control communication. Specifically, the embodiments provide devices and methods for decoding ripple control data from ripple signals, such as ripple signals that have been superimposed over power signals used to transmit power. These embodiments provide devices and methods that use band-pass filter, signal multiplier, fast and slow low-pass filters, and accumulate a difference between outputs of these slow and fast low-pass filters. This accumulated difference is then used to decode the ripple control data.

Abstract: A radio frequency (RF) front end having multiple low noise amplifiers modules is disclosed. In an exemplary embodiment, an apparatus includes at least one first stage amplifier configured to amplify received carrier signals to generate at least one first stage carrier group. Each first stage carrier group includes a respective portion of the carrier signals. The apparatus also includes second stage amplifiers configured to amplify the first stage carrier groups. Each second stage amplifier configured to amplify a respective first stage carrier group to generate two second stage output signals that may be output to different demodulation stages where each demodulation stage demodulates a selected carrier signal.

Abstract: A signal output circuit includes a signal correction circuit, having a clock signal input thereto, which corrects the clock signal to output the corrected signal, and a waveform shaping circuit that shapes a signal from the signal correction circuit. In the clock signal, pulses having a pulse width ? capable of being represented by a length of a time are periodically arranged with a period T, and the pulse width ? and the period T satisfy a relation of ?/T?0.5. The signal correction circuit attenuates a signal having a second frequency based on a time width of at least one of the pulse width ? and a pulse width T??, rather than a signal having a first frequency based on the period T.

Abstract: An embodiment communication system and method for using multiple-input multiple-output use. Kronecker model to determine a symbol coding formulation that achieves ergodic capacity for high signal-to-noise ratios (SNRs). The lower bound on this capacity is achieved by input signals in the form of the product of an isotropically distributed random Grassmannian component and a deterministic component comprising the eigenvectors and the inverse of the eigenvalues of the transmitter covariance matrix.

Abstract: Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

Abstract: An OOK modulation device according to the present inventive concept includes: an oscillator outputting a first frequency signal in which the frequency varies according to an input voltage; a frequency multiplier switching unit operating according to an OOK input data and switching on/off a second frequency signal that is obtained by multiplying the first frequency signal; and a switching amplifying unit amplifying and switching the second frequency signal according to the OOK input data to output an OOK modulation signal.

Abstract: Exemplary embodiments relates to a demodulator for frequency-shift keyed signals by using the Goertzel algorithm according to the general recursive calculating rule, where c re = 2 * cos ? ( 2 * ? * f g f s ) with the sampling frequency fs and the specified frequency fg. To reduce the mathematical complexity in feed-power-limited devices, it is proposed that the sampling frequency fs is an integral multiple of the frequency fg of a specified discrete spectral component.

Abstract: A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.

Abstract: A touch module having a dynamic capacitance matching mechanism, including: a comparator, having a first input end and a second input end, the second input end being coupled with a reference voltage; a touch capacitive circuit, having a variable touch capacitor, a voltage source, and a second output end, wherein the voltage source is used to perform a charging procedure on the variable touch capacitor, and the variable touch capacitor is coupled to the first input end of the comparator via the second output end after the charging procedure; and a transferred-charge-storing capacitive circuit, having a variable transferred-charge-storing capacitor and a third output end, wherein the variable transferred-charge-storing capacitor is used to couple with the first input end of the comparator via the third output end to perform a charge transfer procedure.

Abstract: Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.

Abstract: A method and apparatus for decoding binary frequency shift key signals in which an exclusive-OR of the sign of a real waveform with a sign of the imaginary waveform at a time shortly after the real (or, alternatively, the imaginary) waveform crosses zero is used to determine a bit represented by the signal. In some embodiments, particularly those in which the bit period is about one-half of the carrier signal frequency, both the real and imaginary waveforms are monitored to detect the zero crossing in order to account for the situation in which data transitions prevent zero-crossings on one of the waveforms.

Abstract: A receiving circuit, a transmitting circuit, a micro-controller, and a method for power line carrier communication. The receiving circuit includes: an analog amplifier, a receiving filter, an analog-to-digital converter, a digital mixer, a digital filter, and a digital demodulator connected successively. The transmitting circuit includes: a digital modulator, a gain controller, a digital-to-analog converter, a transmitting filter, and a transmitting amplifier connected successively. The micro-controller includes a central processor and the receiving circuit or the transmitting circuit. The method for power line carrier communication can be implemented based on the receiving circuit or the micro-controller.

Abstract: A wireless communications device includes a receiver, and a demodulator coupled downstream from the receiver and configured to use a continuous phase modulation (CPM) waveform to non-coherently demodulate a received signal. The demodulator is configured to generate waveform banks, each waveform bank having a respective different frequency offset associated therewith, determine a correlation output metric for each waveform bank, select a waveform bank for demodulating the received signal based upon the correlation output metrics of the waveform banks, and demodulate the received signal using the selected waveform bank and the associated frequency offset.

Abstract: A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled into the first intermediate signal processing path; a second amplifier coupled into the second intermediate signal processing path; and a chopper circuit coupled into the first intermediate signal processing path; wherein the chopper circuit is adapted to process the first intermediate signal in dependence on first baseband data; wherein the first amplifier is adapted to amplify the first intermediate signal processed by the chopper circuit in dependence on second baseband data; and wherein the second amplifier is adapted to amplify the second intermediate signal in dependence on the second baseband data.

Abstract: The radio transmitting apparatus includes a first initial phase value setting circuit that sets, in the first modulator, an initial value of the phase of the first modulated signal, which is a value at the start of the modulation according to the first modulation scheme. The radio transmitting apparatus includes a second initial phase value setting circuit that sets, in the second modulator, the phase stored in the phase storing circuit as an initial value of the phase of the second modulated signal, which is a value at the start of the modulation according to the second modulation scheme. The radio transmitting apparatus includes a signal gathering circuit that selects and outputs the first modulated signal output from the first modulator and then selects and outputs the second modulated signal output from the second modulator.

Abstract: An apparatus for providing a data encoding scheme may include an encoder. The encoder may be configured to determine, for a digital input value comprising a particular number of bits, whether more than half of the bits of the digital input value have a high value. The encoder may be further configured to encode the digital input value by inverting each of the bits of the digital input value in response to a determination that more than half of the bits of the digital input value have the high value. Corresponding method and computer program product, and a decoder and decoding method are also provided.

Abstract: 2n data transfer signal lines are provided between transmitting and receiving sides of data on n signal lines in order to reduce power consumption required for a data transfer even if the number of bits of data to be transferred increases. The transmitting side has an encoder for outputting a signal of a low potential to one signal line and a signal of a high potential to the other signal lines among the 2n data transfer signal lines in response to an input of transfer data from the n signal lines. The receiving side has a decoder for outputting the similar data as the transfer data to n signal lines in response to inputs from the 2n data transfer signal lines.

Abstract: A communication device includes: demodulating means for demodulating a transmission signal from another communication device that performs noncontact communication; calculating means for performing at least one of addition and subtraction of a predetermined voltage according to a logical value of a demodulated signal obtained by demodulation by the demodulating means; determining means for determining a communication system of the transmission signal transmitted by the other communication device by comparing a calculation result of the calculating means at predetermined timing after a lapse of a predetermined time from the start of communication with a threshold voltage; and transmitting means for transmitting predetermined data to the other communication device in the communication system determined by the determining means among plural communication systems that the device itself can support.

Abstract: Apparatus and methods for demodulation are provided. In one embodiment, a method includes receiving an input signal having a frequency that varies in relation to a state of the signal, calculating a sine and cosine of a phase control signal, generating a first signal proportional to the sine of a product of a first quantity and the frequency of the input signal, generating a second signal proportional to the cosine of a product of the first quantity and the frequency of the input signal, and summing a product of the first signal and the cosine of the phase control signal with a product of the second signal and the sine of the phase control signal to generate a demodulator output for resolving the state of the input signal. In certain implementations, the phase control signal is controlled so as to reduce a frequency error of the input signal.

Abstract: A binarization circuit includes a comparator that outputs a signal according to a differential voltage between the input and reference voltages. The first charging-discharging circuit generates a first voltage. The second charging-discharging circuit generates a second voltage. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage. A sum of the reference and first voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned off. A sum of the reference and the first and second voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned on.

Abstract: A carrier offset detection circuit is offered, which is provided to a demodulation circuit which demodulates a received signal subjected to FSK (Frequency Shift Keying) modulation, and which detects the offset of the carrier frequency between the transmitting side and the receiving side. A zero-crossing detection unit receives a digital base band signal indicating the level of the frequency shift (frequency deviation) of the received signal using the carrier frequency on the receiving side as a reference frequency, and detects a zero-crossing point of the base band signal and a base band signal obtained by delaying the former base band signal by one symbol, which occurs in a preamble period. A carrier offset detection circuit sets the offset value of the carrier frequency to the value of the base band signal at a timing of the zero-crossing point thus detected.

Abstract: A receiver includes a band-pass filter that limits a passband of an IF (Intermediate Frequency) signal, an FSK detector that detects the IF signal passing through the band-pass filter to generate a detection signal, and a control block that controls a modulation sensitivity of the FSK detector and a pass bandwidth of the band-pass filter, in which the control block controls the modulation sensitivity of the FSK detector according to the pass bandwidth of the band-pass filter.

Abstract: According to one embodiment, a binarization circuit includes a comparator, first and second charging-discharging circuits, and a control circuit. The comparator compares an input voltage with a reference voltage and outputs a signal in accordance with a differential voltage between the input voltage and the reference voltage. The first charging-discharging circuit generates a first voltage by multiplying the differential voltage by a first charge-discharge factor. The second charging-discharging circuit generates a second voltage by multiplying a difference between the differential voltage and a threshold voltage by a second charge-discharge factor greater than the first charge-discharge factor. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage.

Abstract: A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled into the first intermediate signal processing path; a second amplifier coupled into the second intermediate signal processing path; and a chopper circuit coupled into the first intermediate signal processing path; wherein the chopper circuit is adapted to process the first intermediate signal in dependence on first baseband data; wherein the first amplifier is adapted to amplify the first intermediate signal processed by the chopper circuit in dependence on second baseband data; and wherein the second amplifier is adapted to amplify the second intermediate signal in dependence on the second baseband data.

Abstract: A demodulation circuit, a digital microwave system including the demodulation circuit, and a signal demodulation method are provided. The demodulation circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit connected in turn. The fourth circuit includes a pulse counting unit and a data decision unit connected in turn. The signal demodulation method includes: performing bandpass filtering on input signals; increasing gains of the bandpass filtered signals; extracting pulse signals are extracted from the gain-increased signals; counting the extracted pulse signals; filtering the pulse signals having counting values falling outside of a predetermined range, and outputting the filtered pulse signals.

Abstract: An architecture for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the signal processing apparatus comprises a demodulator for generating a first signal responsive to an FSK signal, said first signal comprising a varying amplitude and a clamping means for generating a second signal, wherein said second signal has a first value when the amplitude of the first signal is above a predetermined value, and wherein said second signal has a second value when the amplitude is below a second predetermined value.

Abstract: Quadrature signal demodulator circuitry for demodulating multiple related input signals into respective pairs of quadrature signals for selective combining to provide a composite pair of quadrature signals with a maximized signal-to-noise ratio (SNR).

Abstract: An integrated transmit circuit includes a voltage controlled oscillator (702) for generating an input frequency signal (e.g., VCO) that is provided to a divide by two quadrature generator circuit (706) which generates therefrom in-phase and quadrature clocking signals (I, IB, Q, QB) that are applied to control a plurality of transmission gates (711-718) configured in a matched switching topology (710) so as to selectively pass pulses from the input frequency signal, thereby generating interleaved LO pulses (Ø1, Ø1B, . . . Ø4, Ø4B). By applying the interleaved LO pulses to control the transmission gates (26, 28, 30, 32, 34, 36, 38, and 40) in the upmixer (720), the +I, ?I, +Q, ?Q input signals are interleaved over a plurality of phases of a carrier period to produce differential outputs (42, 44).

Abstract: Low noise mixers for use in RFID readers and RFID readers configured to receive data from ISO HDX transponders in accordance with embodiments of the invention are illustrated. One embodiment of the invention receives the HDX FSK signal using a resonant antenna, upwardly mixes the FSK signal to an intermediate frequency, filters the intermediate frequency FSK signal using at least one ceramic bandpass filter, and demodulates the filtered intermediate frequency FSK signal to produce a binary output.

Abstract: A Gaussian Frequency Shift Keying/Frequency Shift Keying (GFSK/FSK) modulation circuit implemented in a digital manner comprises a frequency divider for dividing frequency of an inputted clock signal to get a sampling signal, a buffer coupled to the frequency divider for storing inputted data, an integrator coupled to the buffer for processing integration according to the data outputted from the buffer, a first read only memory coupled to the integrator for transferring the data outputted from the integrator according to a cosine function, and a second read only memory coupled to the integrator for transferring the data outputted from the integrator according to a sine function.