Abstract: A clock generation circuit has an injection-locked oscillator, a frequency doubler circuit, low pass filters and a calibration circuit. The injection-locked oscillator has an input coupled to a half-rate clock signal. The frequency doubler circuit has inputs coupled to outputs of the injection-locked oscillator. Each of the low pass filters has an input coupled to one of a plurality of outputs of the frequency doubler circuit. The calibration circuit includes comparison logic that receives outputs of the low pass filters. The calibration circuit has an output coupled to a control input of a source of a supply current in the injection-locked oscillator. In one example, the source of the supply current is a current digital to analog converter.

Abstract: Disclosed is a signal splitter that includes a coupled transmission line element coupled between two output ports of the signal splitter. The coupled transmission line element is used to lower the isolation between the two output ports for a particular frequency band. The coupled transmission line element includes a first and a second elongate electrical conductor. The first and the second elongate electrical conductor first ends are coupled to the signal transmission path that connects the two output ports. The first and the second elongate electrical conductor second ends are un-terminated. The first elongate electrical conductor and the second elongate electrical conductor are not shorted together, and the first elongate electrical conductor and the second elongate electrical conductor are electrostatically coupled, such as by twisting them together into a helix.

Abstract: A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.

Abstract: Apparatus and methods for loss of signal detection are provided. In one embodiment, a detection circuit for monitoring an input includes a small signal boost circuit, a rectifier circuit, a low-pass filter, and one or more comparators. The small signal boost circuit can generate an amplified signal by providing a first amount of gain to an input signal when the input signal is relatively small, but can saturate and provide reduced gain without external gain control adjustment when the input signal does not have a relatively small magnitude. The rectifier circuit can rectify the boosted signal to generate a rectified signal, and the low-pass filter can filter the rectified signal to generate a filtered signal. The one or more comparators can compare the filtered signal to one or more decision threshold voltages to determine the presence or absence of the input signal on the input.

Abstract: A modulation method includes sampling the first input signal by using the first local oscillation signal and the second local oscillation signal to generate the first sampled signal, sampling the second input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the second sampled signal, sampling the second input signal by using the first local oscillation signal and the second local oscillation signal to generate the third sampled signal, sampling the first input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the fourth sampled signal, adding the first sampled signal and the second sampled signal to produce the first modulation signal, adding the third sampled signal and the fourth sampled signal to generate the second modulation signal, and adding the first modulation signal and the second modulation signal to generate an output signal.

Abstract: A method and system is provided for communicating distinct data over a single frequency using on-off keying, a form of amplitude modulation, or phase changes timed to the zero crossing point of the carrier. A data signal is synchronized with the carrier by adding padding bits so that the number of bits is equal to the frequency of the carrier. The carrier is then modified by attenuating the carrier as needed once per cycle. Said carrier is then transmitted. The resulting transmitted carrier carries a number of bits equal to the transmit frequency. At the receive end, the received signal is compared to a sine wave to determine if the incoming signal is at full strength or at reduced strength, allowing for the detection of encoded digital information. In a another embodiment, the phase of the carrier is changed instead of attenuating the carrier, timed to the carrier cycles, once or twice per cycle.

Abstract: A phase-shift keying (PSK) demodulator and a smart card including the same are disclosed. The PSK demodulator includes a delay circuit and a sampling circuit. The delay circuit generates a plurality of clock signals by delaying the input signal. The sampling circuit samples the input signal in response to the clock signals, and generates output data.

Abstract: In one embodiment, a circuit provides two quadrature components, I and Q, from a received modulated signal, from three mutually phase-shifted components of the received signal. The circuit can demodulate three mutually phase-shifted components of a baseband signal, in order to provide two quadrature demodulation components. The circuit includes three circuit inputs, each designed to received said three components, respectively. The circuit further includes a first and second adder circuit. The circuit also includes a bank of weighting circuits linked, at input, to the three circuit inputs and linked, at output, to the inputs of the first and second adder circuits so as to transmit to each adder input, with a determined weighting, a particular one of said three components, the weightings being chosen so that the first and second adder circuits provide said two quadrature demodulation components.

Abstract: A low power BPSK demodulator having a simple architecture, compact design and reliable is provided. The BPSK demodulator includes a first branch (210) having a first mixer (212) and a first low pass filter (214), a second branch (220) coupled to the first branch at the output of the first low pass filter (214) and input of the first mixer (212) and having a second mixer (222), and a third branch (230) coupled to the second branch at the input and output of the second mixer (222) and having a third mixer (232) a second low pass filter (234) and a voltage control oscillator (236), wherein the third branch and the second branch form a charge pumped based phase lock loop that locks onto a carrier frequency of the BPSK demodulator.

Abstract: A pattern evaluation method includes: acquiring a plurality of examination images obtained in regard to an evaluation target pattern, at least one of the plurality of examination images being different from the other examination images; detecting all edges of the evaluation target pattern in each of the examination images; executing alignment of the evaluation target pattern in the respective examination images with a sub-pixel accuracy based on the detected edges; superimposing the aligned pattern edges to generate a single combined edge; measuring the combined edge; and evaluating the evaluation target pattern based on a result of the measurement.

Abstract: To provide an adder capable of obtaining an addition signal of a plurality of high frequency signals, and also a power combiner, a quadrature modulator, a quadrature demodulator, a power amplifier, a transmitter, and a wireless communicator, each of which uses the adder. Impedances (Zg, Zh) seen from a common output point (P3) of a plurality of first impedance circuits (110a, 110b) toward respective input terminals (102a, 102b) are set so that high frequency currents (Ig, Ih) are approximately zero. An impedance (Zs) seen from a first connection point (P1) toward the input terminals (102a, 102b) is set so that a high frequency current (Is) is approximately zero. An impedance (Zc) seen from the first connection point (P1) toward a circuit (150) is set so that a high frequency current (Ic) is approximately zero. An impedance (Zm) seen from a second connection point (P2) toward a power supply is set so that a high frequency current (Im) is approximately zero.

Abstract: Disclosed is a logarithmic detector comprising: an amplifier element; means for setting a frequency of operation of the detector; and a controller, wherein an input signal to the amplifier element is arranged to cause an oscillation in the amplifier element, and the controller is operable to sense a pre-determined threshold, indicative of oscillation and, in response to sensing said threshold, to interrupt the oscillation of the amplifier such that the frequency of said interruption is proportional to the logarithm of the power of the input signal.

Abstract: A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal, and a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

Abstract: Provided is a sub-harmonic frequency mixer having a structure in which two terminals of transistors receiving a Radio Frequency (RF) signal and a Local Oscillation (LO) signal are coupled. The frequency mixer is composed of a single-level structure of transistors and thus can be driven at a lower supply voltage compared to a common frequency mixer. A direct-conversion receiver employing such a frequency mixer needs an RF signal and an LO signal sources of single-phase. Therefore, the direct-conversion receiver has an architecture that simplifies a whole RF transceiver circuit and thus can be advantageously applied in implementing SoC (System-on-Chip) for a low power, high integration, low price and subminiature wireless transceiver circuit.

Abstract: The invention relates to a device for demodulating an input signal containing information being conveyed by phase modulation of a carrier wave. A transmitter generates a signal controlling a phase variation in the carrier wave, for each symbol having N cycles, N being an integer strictly greater than 1. The phase variation stretches on the receiver side over n cycles, n being an integer greater than 1 and less than N. The device generates a single pulse for each symbol received suited to generate the leading edge of the pulse corresponding to the symbol considered after a constant duration from the moment the symbol considered starts; and generates the trailing edge of the pulse considered at a moment the phase shift corresponding to the symbol considered has to be measured. Conversion means generate an output signal with a voltage varying as a function of the duration of the pulse produced.

Abstract: Structures and techniques for implementing multiple-antenna configurations within a radio frequency receiver are provided. In one aspect, a modularized multi-antenna receiver is provided having multiple independent microelectronic dice mounted on a common module substrate. In another aspect, a multi-antenna receiver is provided that utilizes at least one single ended low noise amplifier and at least one differential low noise amplifier within a common receiver.

Abstract: One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.

Abstract: A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the labor or man-hours and the time required for adjusting the demodulation characteristic.

Abstract: A demodulator demodulates a PSK communications signal using a synchronizer, a period window detector, and a logic device. The synchronizer provides a transition signal representing reference edges of the communication signal. The period window detector, coupled to the synchronizer, establishes a time interval based on the period of the transition signal. Finally, the logic device, having logic inputs coupled to the outputs of the period-window detector, yields a logic output signal. The demodulator preferably includes a carrier boundary detector for framing messages and minimizing noise detection in a manner that permits signal strength measurements over a wide dynamic range.

Abstract: A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the labor or man-hours and the time required for adjusting the demodulation characteristic.

Abstract: The invention relates in particular to a method of compensating differences in group propagation times between first and second analog filters of a transmitter of signals in phase quadrature, and between third and fourth analog filters of a receiver of signals in phase quadrature. The method consists in: applying the output signals from the first and second filters respectively to the third and fourth analog filters so as to measure a time difference .DELTA.1 equal to: ?Tx+Rx!-?Ty+Ry! where Tx, Rx, Ty, and Ry are respective propagation times for the signals through the first, second, third, and fourth filters; applying the output signals from the first and second filters respectively to the fourth and third analog filters so as to measure a time difference .DELTA.2 equal to: ?Ty+Rx!-?Tx+Ry! and determining weighting coefficients from the differences .DELTA.1 and .DELTA.

Abstract: An apparatus detects living bodies, in particular human living bodies, by ectromagnetic signals. The apparatus has a receiver device for electromagnetic signals that includes a device for obtaining frequency components that are characteristic in respect to living bodies, out of the magnetic signals. The receiver device includes a direct demodulator.

Abstract: The invention provides a quadrature demodulator which removes unnecessary higher harmonic signals included in a demodulation output without giving rise to increase in number of externally connected parts and increase in current consumption. The quadrature demodulator includes a first double differential circuit to which a modulated signal and a first local signal are inputted, a first emitter follower circuit for effecting impedance conversion, a second double differential circuit to which the modulated signal and a second local signal having a phase shifted by 90-degrees from the first local signal are inputted, and a second emitter follower circuit connected to a pair of outputs of the second double differential circuit for effecting impedance conversion.

Abstract: An efficient apparatus for performing frequency conversion from a final IF frequency to a baseband frequency is described. A counter (401) generates two logical signals G1 (402) and G2 (403) which are passed to an exclusive-OR gate (404) and a multiplexer (406). When a control signal (411) is deasserted, multiplexer (406) passes signal G1 to I1 and signal G2 to I2; when control signal (411) is asserted, multiplexer (406) passes binary signal G1 to I2 (410) and signal G2 to I1 (407). Similarly, multiplexer (405) swaps its input real and imaginary samples when the output of exclusive-OR gate (404) is asserted; otherwise, it performs no operation on its input samples. Signals I1 (407) and I2 (410) are used to control arithmetic inverters (408) and (409) respectively. When the controlling signal for either inverter is asserted, the inverter performs arithmetic inversion, otherwise it performs no operation.

Abstract: In a complex modulation/demodulation method and system, the data frequency f.sub.C1 of data signals I and Q inputted to a constellation mapping circuit is converted by a digital interpolation circuit into a sampling frequency f.sub.C2 equal to f.sub.S /N, where f.sub.S is an operation sampling frequency and N is selected such that the signal maximum frequency of the data signals I and Q becomes lower than f.sub.C2 /2. The interpolated data signals I and Q are respectively inputted to real and imaginary input terminals of a complex coefficient band pass filter to extract a real signal output. An output signal of the complex coefficient band pass filter is converted by a DA converter into an analog signal from which desired frequency components are extracted by an analog band pass filter, thereby performing a quadrature modulation.

Abstract: An I/Q-modulator or I/Q demodulator circuit in which the modulating signals (2, 3) are input through the output phase transfer branches of the circuit. In relation to the RF-characteristics, a series resistor (16) and a series inductance (20) in the phase transfer circuits are grounded with small capacitors (23, 25). A capacitor (17) having a high impedance at the modulating frequency is located between the branches. Tho modulating signals are not summed through the capacitor (17), and, thus, their phase difference is not weakened.

Abstract: A compact local oscillator network for use in a quadrature modulator and/or demodulator is presented. Single side band circuitry is configured to produce quadrature signals with a high degree of accuracy such that two equal amplitude signals are generated having a precise 90.degree. phase difference. The network accuracy is substantially not affected by phase or amplitude imbalances within or introduced into the network. For example, the network may include: a first quadrature circuit for dividing a first input signal into a first in-phase signal and a first quadrature signal 90.degree. out of phase; a second quadrature circuit for dividing a second input signal into a second in-phase signal and a second quadrature signal 90.degree.

Abstract: An IQ modulator/demodulator wherein the 90.degree. phase quadrature branches of an input signal are connected to different terminals of a common bridge, from which also the quivalents I and Q signals are obtained. To the bridge is also connected a local oscillator signal through a transformer. The transformer can be replaced with an active circuit, whereby the entire demodulator can be implemented in the form of an integrated circuit.

Abstract: A phase-error detecting circuit for detecting a phase error of an output signal of the VCO in a QDPSK demodulating circuit in accordance with the Costas loop method is disclosed. The phase-error detecting circuit comprises a first circuit which generates a first product (P.times.Q) of a first demodulated signal (P) and a second demodulated signal (Q) of a QPSK signal. A second circuit generates the difference of the squares (P.sup.2 -Q.sup.2) of the first and second demodulated signals. A third circuit receives both the first product (P.multidot.Q) generated by the first circuit and the difference (P.sup.2 -Q.sup.2) generated by the second circuit and generates the product of the first product (P.multidot.Q) and the difference (P.sup.2 -Q.sup.2). The first circuit includes a first quadratic multiplier for generating the first product. The second circuit includes second and third quadratic multipliers, a phase-reversing mechanism for reversing the phase of the signal (Q), and an adding mechanism.

Abstract: A microwave circuit intended for either direct modulation or direct demodulation of a microwave link communications signal is characterized in that a local oscillator (8) is incorporated in the circuit. The local oscillator supplies two signals that are in phase opposition at 180 degrees. Each signal is sent to a phase shifter. The first phase shifter (9) supplies two signals that are in quadrature, at 0 and 90 degrees. The second phase shifter supplies two signals in quadrature at 180 and 270 degrees. The 0 and 180 degree signals are sent to a first mixer (2), while the 90 and 270 degree signals are sent to a second mixer (3). In the case of a modulator, the first and second mixers receive, respectively, in-phase and quadrature signals, and the outputs of the mixers are combined to form a modulated signal. In the case of a demodulator, a modulated signal is applied through a .div.2 divider to inputs of the two mixers, and in-phase and quadrature signals are obtained at respective mixer outputs.

Abstract: An audio detector circuit forms L+R and L-R audio signals from an intermediate frequency compatible quadrature amplitude modulated signal in the form (1+L+R)cos(fct+.phi.) where .phi. contains phase modulated L+R and L-R signals. An envelope detector generates an L+R audio signal and in-phase and quadrature phase detectors produce L+R and L-R audio signals, respectively. The difference between L+R outputs of the envelope and in-phase detectors are amplified to generate a cosine correction signal. Each detector includes a differential operational amplifier having an field effect feedback transistor coupled between each amplifier output and the corresponding input and an field effect transistor coupling the compatible quadrature amplitude modulated signal to the operational amplifier inputs.

Abstract: A spread spectrum communications system is described for recovering data from a signal having a first carrier frequency modulated by one of at least four phase modulations, each phase modulation orthogonal to one another and the signal further modulated by a predetermined spreading function incorporating a frequency synthesizer for generating a plurality of frequencies, including one of the phase modulations, a plurality of mixers, a combiner, a broadband convolver, a second combiner coupled to a reference signal generator for generating respective orthogonal modulations on spaced apart carrier frequencies, a power divider coupled to the output of the convolver and filters each having a frequency passband for recovering or separating the output signals of the convolver. The invention overcomes the problem of additional hardware complexity to accomodate Walsh orthogonal functions and of requiring a plurality of broadband convolvers to decode a plurality of orthogonal modulations of lesser bandwidth.

Abstract: The present invention provides a high frequency lock detecting circuit for generating a signal indicative of a locked or a not locked phase tracking condition in a phase locked loop circuit. The lock detector comprises a plurality of high speed function generators two of which are coupled to the modulated data streams for indicating the phase data streams and a third high speed function generator is coupled to the voltage error signal of the phase locked loop for indicating the absence or presence of a voltage error signal. The analog outputs of the function generators are summed together in a summing circuit and applied to a differential amplifier which removes the complex modulated data products from the output of the function generators and provides a signal which is equal to the absolute value of the data signals applied to the first function generators minus the absolute value of the error signal applied by the third function generator.