Abstract: In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.

Abstract: The present invention relates to an imaging system, including: a coherent light source delivering an object beam and a reference beam; a device of modulation of the object beam with a modulation signal; an image sensor arranged to receive an interference pattern resulting from a combination of the object beam and of the reference beam; and a demodulation device, the system being configured to, during a measurement phase: apply to the modulation signal a first pseudo-random sequence of jumps of a parameter selected among the phase, the frequency, and the amplitude; and simultaneously apply to the modulated portion of the object beam a second pseudo-random sequence of jumps of said parameter, wherein the first and second sequences of jumps of said parameter are non-correlated.

Abstract: In electronic circuits having various gain states, small gain phase shift differences required among various gain states may pose a challenging problem. The disclosed methods and devices provide solution to such challenge. Electronic circuits are described wherein a first path including an amplifier may be bypassed by a second path including only passive elements and for gain states smaller than 0 dB. In such electronic circuits, a phase shifter included in the second path can be adjusted to address the required phase shift among various gain states.

Abstract: A near field communication device configured to receive a signal from an antenna and to generate a first in-phase signal and a first quadrature-phase signal by multiplying the signal with a first oscillation signal and a second oscillation signal; a first and second low-pass filter configured to generate a second in-phase signal and a second quadrature-phase signal; a first and second analog-to-digital converter configured to generate a third in-phase signal and a third quadrature-phase signal; a digital signal extractor configured to generate a first signal and a second signal based on the third in-phase signal, the third quadrature-phase signal, a first look-up table, and a second look-up table, select one from among the first signal and the second signal based on a signal pattern, and output the selected one as an extraction signal; and a modem configured to receive the extraction signal and to demodulate the extraction signal.

Abstract: A method configured to clip an I signal and a Q signal according to a clipping boundary, includes receiving an I value and a Q value, wherein the I value and Q value define Cartesian coordinates of a data point being transmitted on the real and imaginary axes of the complex plane, respectively; determining a clipping error between the I value and the Q value and the clipping boundary; combining the clipping error with the I value to generate a clipped I value; combining the same clipping error with the Q value to generate a clipped Q value; and providing the clipped I value and the clipped Q value to a radio frequency digital-to-analog converter (RFDAC) in a transmit chain.

Abstract: A device for estimating frequency offsets which is performed by periodically transmitting training signals from a wireless local area network system. The device includes a processor and computerized codes stored in a storage unit. The processor is configured to execute the computerized code to perform a method. The method includes receiving the plurality of training signals, selecting selected training signals by a predetermined interval from the received training signals, detecting and storing phases of the selected training signals, averaging phase differences of every pair of the detected phases of the selected training signals, calculating the frequency offsets according to an average of the phase differences for every pair of the detected phases of the selected training signals, and calculating a weighted average of the calculated frequency offsets using weighting values for each of the calculated frequency offsets.

Abstract: A sensor is provided including: an element outputting detection signals according to magnitude of physical quantity; a drive circuit outputting a driving signal to the element and receiving a monitor signal from the element; a detection circuit that includes amplifiers amplifying the detection signals and a first synchronous demodulation circuit performing synchronous demodulation on a signal from the amplifier, receives the detection signals, and outputs a physical quantity signal according to the physical quantity; a processing circuit processing a signal from the first synchronous demodulation circuit; a first diagnostic circuit that receives a signal into the processing circuit and a signal from the processing circuit, and outputs a first error signal when abnormalities occur in the processing circuit; and a second diagnostic circuit that outputs a diagnostic signal to the first diagnostic circuit, instead of the signal into the processing circuit or instead of the signal from the processing circuit.

Abstract: The proposed solution relates to a method and an apparatus in a communication system. The solution includes receiving as an input a frame including of a set of data symbols and reference symbols, each data symbol forming a rectangular symbol constellation of samples, derotating the first symbol of the set on the basis of the reference symbols, and setting phase rotating angle of the first symbol as zero. The solution further includes for each following successive symbol in the set of symbols: performing equalization; reducing the number of samples in the constellation by selecting samples in two or more corners of the constellation by utilizing two or more threshold values; estimating the phase rotating angle of the symbol from the reduced number of samples and derotating the symbol on the basis of the determined phase rotating angle.

Abstract: A system and method are described for distributed antenna wireless communications.

Abstract: Methods and a base station are provided for transmitting a serving signal to a User Equipment (UE) by the base station. The method includes generating modulation order information for determining a modulation order of an interference signal, and transmitting the serving signal with the modulation order information in a resource allocated to the UE.

Abstract: A digital radio receiver is adapted to receive radio signals modulated using continuous phase modulation. The receiver includes components for receiving analogue radio signals having various carrier frequencies and a plurality of correlators corresponding to different bit sequences. Each of the plurality of correlators share a common estimator for estimating a frequency offset between the radio signals carrier frequencies and nominal carrier frequencies. The receiver further includes components allowing the estimator to determine which of the correlators produce the most optimal output signal.

Abstract: An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

Abstract: A DARC signal demodulation circuit assemblage for recovering a DARC signal (DARC data) from an FM multiplex transmission signal includes: a pilot tone regulation circuit to obtain first and second mutually orthogonal oscillation synchronous with a stereo pilot tone encompassed by the FM multiplex transmission signal; a frequency quadruplication section for obtaining third and fourth mutually orthogonal oscillation having a frequency quadrupled as to the stereo pilot tone; a first multiplication section for obtaining a first multiplication signal from the FM multiplex transmission signal and from the third oscillation; a second multiplication section for obtaining a second multiplication signal from the FM multiplex transmission signal and from the fourth oscillation; first/second low-pass filters for obtaining first/second DARC signal components by low-pass filtration of the first and second multiplication signals; and an FM demodulation section for obtaining the DARC signal from a frequency demodulation of t

Abstract: A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analog-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.

Abstract: A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

Abstract: A phase-locked loop frequency synthesizer includes an L-state pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output at least one N/N+1 modulus signals corresponding to the at least one entry from the frequency table. The synthesizer includes a divide by N/N+1 controllable modulus divider configured to receive the at least one N/N+1 modulus signals and to divide the output frequency signal by the at least one N/N+1 modulus signals to generate a second reference frequency signal. The synthesizer includes a phase frequency detector configured to receive the reference frequency signal and the second reference frequency signal and to generate an error signal. The synthesizer also includes a filter network configured to receive the error signal and to output a voltage; and a voltage controlled oscillator configured to receive the voltage and to generate the output frequency signal.

Abstract: A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter.

Abstract: A PLL circuit, for extracting phase error information from a demodulated signal in which a variance of a phase or an amplitude changes depending on a signal-to-noise power ratio, and providing negative feedback control, to thereby suppress a phase error of the demodulated signal, includes: a phase error detector for producing a phase error signal corresponding to a value of the phase error as the phase error information; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing a control signal based on the limited phase error signal to determine frequency characteristics.

Abstract: A multi-carrier linear equalization receiver, e.g., a RAKE receiver or chip equalization receiver, is described herein. The multi-carrier receiver distributes processing delays among a plurality of received carriers based on a comparison between the signal-to-interference ratios (SIRs) determined for each carrier. The receiver initially allocates a minimum number of processing delays to each carrier. In one embodiment, any remaining additional processing delays are distributed evenly between the carriers when a comparison between the largest and smallest SIR is less than or equal to a threshold. In another embodiment, the remaining additional processing delays are distributed to favor the carrier(s) with the strongest SIR(s) when the comparison between the largest and smallest SIR exceeds the threshold.

Abstract: A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Abstract: A multilevel QAM demodulator includes a phase difference calculation unit calculating a phase difference signal based on the common phase signal and orthogonal signal after the phase rotation compensation, a phase shift amount calculation unit calculating a phase shift amount indicating a degree of a phase shift based on the common phase signal and orthogonal signal after the phase rotation compensation and phase noise compensation, and a correction unit correcting the phase difference signal based on the phase shift amount. A phase rotation is performed for the phase noise compensation based on the phase difference signal corrected by the correction unit.

Abstract: Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase.

Abstract: A low power BPSK demodulator having a simple architecture, compact design and reliable is provided. The BPSK demodulator includes a first branch (210) having a first mixer (212) and a first low pass filter (214), a second branch (220) coupled to the first branch at the output of the first low pass filter (214) and input of the first mixer (212) and having a second mixer (222), and a third branch (230) coupled to the second branch at the input and output of the second mixer (222) and having a third mixer (232) a second low pass filter (234) and a voltage control oscillator (236), wherein the third branch and the second branch form a charge pumped based phase lock loop that locks onto a carrier frequency of the BPSK demodulator.

Abstract: Disclosed herein is synchronizing circuit including: a numerically controlled oscillating section; a phase rotating section; a phase error estimating section; a loop filter; and a gain controlling section; wherein the gain controlling section controls the gain so as to suppress an effect of a phase error in an immediate main signal section in a known start section from a start of the known section to a predetermined symbol.

Abstract: A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting.

Abstract: A digital demodulator adapted in a receiver and a digital demodulation method are provided. The digital demodulator includes: a phase splitter, a complex multiplier, an AFC, a limiter, a phase detector, a re-tracker, a post-multiplier and an oscillator. The phase splitter generates a complex signal from the input signal. The complex multiplier multiplies the complex signal by both first and second phase signals to generate first and second base band signals. The AFC generates a first output signal. The limiter generates a trend signal and the re-tracker generates a tuning signal from the first output signal. The phase detector multiplies the trend and second base signal and adjusts the multiplied signal based on the tuning signal. The oscillator generates the first and second phase signals according to the output of the phase detector. The post-multiplier multiplies the trend signal by the first and second base band signals for output.

Abstract: A sampling section (100A) includes a sampling filter (102) that converts a continuous-time signal into a discrete-time signal and applies filtering of low-pass characteristics and a one-bit quantizer (107) that outputs a quantized signal representing a time-dependent change in the discrete-time signal. A synchronization section (100B) includes a phase difference detector (110) that calculates the phase difference between an inspection signal and the quantized signal and a delay control circuit (114) that feeds back the inspection signal to the phase difference detector at the timing set in consideration of a delay amount corresponding to the phase difference. When the phase difference between the inspection signal and the current quantized signal shows the same phase, the phase of the inspection signal is detected as a reference phase.

Abstract: A carrier recovery apparatus includes a pilot strength detector, a first lock loop, a second lock loop, and a controller. The pilot strength detector determines whether a pilot strength of an input signal is greater than a threshold value to generate a control signal. The first lock loop performs a first carrier recovery on the input signal. The second lock loop performs a second carrier recovery on the input signal. The controller selectively allows the first lock loop to perform the first carrier recovery on the input signal or the second lock loop to perform the second carrier recovery on the input signal according to the control signal. The first lock loop is a pilot-based FPLL and the second locked loop is a pilot-less PLL.

Abstract: A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal including an I component and a Q component; a numerically controlled oscillation section that generates a signal of predetermined phase; a phase error detection section that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section; a phase rotation section that rotates the phase of the symbol of the demodulation signal in accordance with the phase error; a loop filter that filters the phase error, and controls the numerically controlled oscillation section; and a gain control section that controls a gain of the loop filter based on a modulation technique of the modulation signal.

Abstract: The invention relates to a method and a circuit for carrier control in a quadrature demodulator, wherein a complex-value input signal (I, Q) is supplied to a mixer (1) to perform mixing with a mixing frequency (fm) to create a mixed signal (Ir, Qr), the mixed signal (Ir, Qr) is supplied to a processing section (s) to generate a processed signal (Ie, Qe), the processed signal (Ie, Qe) is supplied to phase measurement device (3) in order to measure a phase (?m) of the processed signal (Ie, Qe) and the measured phase (?m) is supplied to a phase controller (4) in order to control the mixing frequency (fm); wherein an idle time (z?d) is created at least during the processing in the processing section (2).

Abstract: A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

Abstract: A demodulation apparatus that demodulates an amplitude-phase-modulated signal having a level and a transition phase selected from among a plurality of levels and a plurality of phases according to transmission data, comprising a clock recovering section that receives the amplitude-phase-modulated signal and recovers a clock signal synchronized with the amplitude-phase-modulated signal; an amplitude and phase detecting section that detects, with the clock signal as a reference, the level and the transition phase of the amplitude-phase-modulated signal; a data output section that outputs data corresponding to the level and the transition phase detected by the amplitude and phase detecting section; and a phase difference correcting section that outputs a correction signal for correcting an oscillation frequency of the clock signal output by the clock recovering section, according to the transition phase detected by the amplitude and phase detecting section.

Abstract: A low power BPSK demodulator having a simple architecture, compact design and reliable is provided. The BPSK demodulator includes a first branch (210) having a first mixer (212) and a first low pass filter (214), a second branch (220) coupled to the first branch at the output of the first low pass filter (214) and input of the first mixer (212) and having a second mixer (222), and a third branch (230) coupled to the second branch at the input and output of the second mixer (222) and having a third mixer (232) a second low pass filter (234) and a voltage control oscillator (236), wherein the third branch and the second branch form a charge pumped based phase lock loop that locks onto a carrier frequency of the BPSK demodulator.

Abstract: A receiver has a first voltage control oscillator configured to generate a first oscillation signal, a second voltage control oscillator configured to generate a second oscillation signal having a first phase, a first phase comparator configured to detect a phase difference between the first and second oscillation signals, a demodulator configured to perform demodulation processing of the received signal and to generate timing information of a second phase included in the first oscillation signal, a second phase comparator configured to detect the phase difference between the first and second oscillation signals, and a first control voltage generator configured to generate a first control voltage for controlling a phase and a frequency of the second voltage control oscillator based on the phase difference detected by the second phase comparator.

Abstract: A phase tracking system includes a source of an input signal representing a received symbol. A phase rotator has a first input terminal which is responsive to the input signal, a second input terminal which is responsive to a phase correction signal, and an output terminal which produces a phase adjusted output signal. A decision element generates an ideal signal representing the received symbol in response to the phase adjusted output signal. A phase adjuster, which has full phase wrap-around capability, generates the phase correction signal in response to the phase difference between the phase adjusted output signal and the ideal signal.

Abstract: A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by ?/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

Abstract: A receiver for a digital communication signal has a first decision gate (DGa), which has a first decision threshold (xd) for outputting a first decision signal, a second decision gate (DGb), which has a second decision threshold (xm) for outputting a second decision signal, a counter (CNT) for counting events where the first and second decision signals of the first and second decision gates (DGa, DGb) differ from each other, and a controller (PROC) capable of controlling the decision thresholds of said first and second decision gates in accordance with count values delivered by said counter. The controller (PROC) determines an initial decision threshold value by performing a statistical analysis of the received signal and setting the decision threshold such that the distribution of logical ‘0’ and logical ‘1’ in the decided signal corresponds to the expected distribution, which is in typically 50%/50%.

Abstract: A demodulation circuit can perform a capturing operation although a frequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two pint modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: There are provided a VSB receiver and a carrier recovery apparatus thereof, in which a carrier is recovered using a VSB modulated signal. In the VSB receiver, a digital processing part selects a desired channel frequency through an antenna, converts the channel frequency into an intermediate frequency, and digitalizes the channel frequency by passing a predetermined band of the intermediate frequency. A carrier recovery part extracts pilot signals by using a first LPF having a first bandwidth and a second LPF having a second bandwidth, and recovers a baseband carrier wave signal from a passband signal by using one of the extracted pilot signals. A clock demodulation part removes the pilot signal from the baseband carrier wave signal and extracts a synchronizing signal. A noise removing part removes a linear noise and a residual phase jitter of the baseband signal by using the synchronizing signal. A decoding part decodes the baseband signal whose noise is removed.

Abstract: An integrated circuit includes an analog-to-digital (ADC) portion and a processor portion. The processor portion generates high frequency noise. The ADC portion includes chopper switches, an ADC, a first low-pass filter (LPF), an inverter, and a second LPF. An analog sensor signal is chopped by the chopper switches at a chopping frequency below the processor noise frequency. The ADC performs conversions a rate higher than the chopper frequency such that multiple first conversions are performed when the chopper switches are in a first configuration and multiple second conversions are performed when the chopper switches are in a second configuration. The first LPF attenuates the high frequency noise, converts the first conversions into first information, and converts the second conversions into second information. The inverter inverts the second information. The second LPF attenuates transposed 1/F noise and converts the first information and the inverted second information into ADC output values.

Abstract: A receiver to process a RF input signal having a plurality of channels includes a direct down conversion circuit, a demodulation circuit, and a local oscillator circuit. The direct down conversion circuit provides a downconverted signal based on the RF input signal and a local oscillator signal. The demodulation circuit receives the downconverted signal and provides a demodulated signal. The local oscillator circuit sets a frequency of the local oscillator signal based on a selected channel of the plurality of channels.

Abstract: A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal.

Abstract: A device and method for a symbol recovery in a digital television are disclosed. The device includes a symbol clock recovery device includes a remained phase error remover operating a digital baseband real/imaginary number component signals, and removing remained phase error, a timing error detector nonlinearly operating the real/imaginary number component signals having the remained phase error removed, and detecting symbol clock phase error information therefrom, and an oscillating part generating a symbol clock frequency compensated to at least two times from the detected symbol clock phase error information and outputting the compensated frequency.

Abstract: In a timing component extractor for a digital modulated signal, a frequency converting section 30 receives a complex baseband signal having a symbol rate fs and formed from an I signal and a Q signal, and converts frequency components ±fs/2, which are present in the complex baseband signal as the data changes, to frequency components ±fs/4. The I signal and Q signal of the complex baseband signal are then nonlinearly processed. In other words, multipliers 31, 32 square the I signal and the Q signal, respectively, and an adder 33 adds the respective results of the multipliers 31, 32. A BPF 34 extracts the frequency components ±fs/2 from the output of the adder 33, and outputs the extracted frequency components ±fs/2 as a timing signal. Accordingly, processing can be conducted at a sampling frequency which is twice the symbol rate fs. Moreover, timing extraction can be stably conducted without being affected by a carrier frequency offset.

Abstract: A PLL circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by ?/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal, and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal, based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

Abstract: A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal including an I component and a Q component; a numerically controlled oscillation section that generates a signal of predetermined phase; a phase error detection section that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section; a phase rotation section that rotates the phase of the symbol of the demodulation signal in accordance with the phase error; a loop filter that filters the phase error, and controls the numerically controlled oscillation section; and a gain control section that controls a gain of the loop filter based on a modulation technique of the modulation signal.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Abstract: A carrier frequency in a filtered received M-ary phase-shift keyed (MPSK) modulated signal having in-phase and quadrature components is detected by processing the filtered received signal to remove modulation components and thereby generate a test signal at the carrier frequency; processing the test signal to provide an amplitude spectrum of samples at different test frequencies; and processing the amplitude spectrum to detect the carrier frequency in accordance with the test frequency at which there is a test statistic of the highest magnitude. The magnitude of the test statistic is determined by processing a signal statistic in relation to a noise statistic. The signal statistic is the amplitude of the largest-amplitude sample. The filtered received signal is processed to provide approximate values of the modulus of the received signal and the phase of the received signal; and the approximate modulus and phase values are processed to generate the test signal.

Abstract: A carrier recovery apparatus capable of detecting a phase error of modulation signal by a simple calculation, reducing the circuit scale, and improving the frequency capture characteristic and phase jitter characteristic is presented. This carrier recovery apparatus comprises a symbol estimating unit for estimating the transmitted symbol, a phase error detector for generating a normalized phase error signal on the basis of the estimated symbol and reception signal, a loop filter for filtering the phase error, and a numerical control oscillator controlled by the loop filter.