Abstract: In a quadrature receiver for phase and/or frequency modulated signals an intermediate phase signal is quantized to produce a quantized phase signal. The receiver includes a demodulator in which pulses are generated from the quantized phase signal and it is determined whether two successive pulses have different polarities, and if so, a reconstructed baseband signal transition is produced at a predetermined reconstruction instant between the two successive pulses. The reconstruction instant is chosen in the middle between two successive pulses for FSK modulation, and it is chosen at different positions between the two pulses for other types of modulation, such as GMSK or multi-level FSK.

Abstract: A high-speed demodulating method of burst data capable of performing demodulation process at high speed in a single hardware structure. An input signal digitally modulated is taken in into an input unit to be sampled and latched therein by a sampling clock from a controller, and a modulation signal from the input unit is taken in into either a first demodulator or a second demodulator for each one burst data depending on the timing of a first control signal or a second control signal output by the controller, respectively, and demodulated, and a first demodulation signal produced from the first demodulator or a second demodulation signal produced from the second demodulator is taken in into an output unit by a third control signal output by the controller, and in the output unit, the first demodulation signal or the second demodulation signal is latched by a latch signal of the controller and supplied as an output signal.

Abstract: In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon a coherent-detected baseband analog signal in synchronization with a sampling clock signal having a time period half of a symbol time period. An phase detector receives successive first, second and third sampled data from the A/D converter, determines whether or not a signal transition formed by the first and second sampled data crosses a zero value within a predetermined time deviation, and compares a polarity of the second sampled data with a polarity of one of the first and second sampled data to generate a phase detection signal. Further, a loop filter is connected to an output of the phase detector, and a voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter.

Abstract: A reduced complexity maximum likelihood multiple symbol differential detector which utilizes a maximum likelihood sequence estimation of the transmitted phase and does so by expanding the observation window to observe the received symbol over N signal intervals and making a simultaneous decision on N-1 symbols. The phase of the received signal is calculated up front and thus the detector requires only real subtractions and real additions as opposed to complex multiplications and additions. Furthermore, the detector does not sacrifice performance over conventional prior art detectors.

Abstract: A digital modulating signal, which is a binary conversion of an RDS signal by a comparator, is sampled by a D-FF with a regeneration clock synchronized with a carrier regenerated by a carrier regeneration circuit. Next, a comparator output is input by an edge detection circuit where a data edge is detected, and the edge interval between this edge and the sampling timing edge of the regeneration clock is detected by a reliability judgment circuit where the edge interval is encoded and output as reliability data. Then, the reliability data is added as LSB data to various sampling data, and data for various symbols is regenerated at the data regeneration circuit. This minimizes the influence of the error data on the data regeneration circuit even if data is sampled erroneously.

Abstract: A demodulator is described which includes a hard limiter, reference generator and a phase determiner. The hard limiter produces a binary phase-modulated signal from an analog phase modulated input signal having a first frequency. The reference generator provides a binary reference signal having a second frequency generally equivalent to the first frequency. The phase determiner is operative during a sampling period and determines the phase between the phase-modulated and the reference binary signals during the sampling period.

Abstract: A phase modulated signal demodulation system which is not affected by noise and distortion of an input signal. The system includes a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times of a carrier frequency which is synchronized with an N-phase phase modulated input signal, and a clock generation circuit for dividing the reproduction reference clock by 1/N and for generating N clocks, each of which has a different phase offset by 360.degree./N. The system further includes a phase detector which detects a phase of the N-phase phase modulated signal by using the N clocks together with the input N-phase phase modulated signal; and an operating circuit which detects a data edge of the input signal and the reproduction reference clock.

Abstract: A demodulation apparatus of digital detection processing type of the invention offers versatility as consumer equipment in mobile communications, ATV, satellite broadcasting, CATV, and the like. A modulated wave output is obtained by multiplying an input digitally modulated wave signal by a local oscillating signal from a local oscillator. The obtained modulated wave output has a center frequency which is substantially equal to the symbol frequency. The modulated wave output is A/D converted at a rate which is four times as high as the symbol frequency, so as to be output as interleaved I and Q digital data. The I and Q data is split, and the split I and Q data are multiplied by coefficients of "+1" and "-1", respectively. The multiplied two output signals are selectively output. Thus, the data multiplied by the coefficients of "+1" and "-1" are alternately output for the I and Q signals, so as to perform the digital detection.

Abstract: A coherent phase-shift keying (PSK) detector in a receiver generates an unmodulated carrier signal, without attempting to synchronize the unmodulated carrier signal in frequency or phase to the carrier employed at the PSK transmitter. The instantaneous phase of the received PSK signal is detected with reference to the unmodulated carrier signal to create an instantaneous phase signal. Phase rotation due to frequency offset between the two carrier signals is detected and removed from the instantaneous phase signal, then a remaining phase offset is detected and removed. Data are recovered from the resulting instantaneous phase signal.

Abstract: A technique of demodulating a .pi./4-DQPSK composite carrier waveform using a non-coherent discriminator based receiver is presented. In particular, a means of recovering .pi./4-DQPSK modulated data symbols using a dual output discriminator in conjunction with a dual binary amplitude detection process in a discriminator based receiver is discussed. Means which improve the bit error rate of the receiver over the prior art are presented. Additionally, an amplitude detection means which readily provides synchronization of the detected data symbols is discussed which was not heretofore possible with the 4-level slicer of the prior art.

Abstract: This detector provides a computationally simple digital low power detector of symbol rate, also called baud rate. It uses an approximate Hilbert transform function to create approximate in-phase and quadrature signals. An approximate envelope detector (feature extractor) processes these signals to produce a signal with a strong frequency component at the symbol rate. This signal is then filtered, accumulated, and threshold detected. The approximate in-phase and quadrature signals are formed by a linear sequence of six delay elements, the output of the third delay element being the in-phase signal. A first summer receives the output of the second delay element at a minus input and the output of the fourth delay element at a plus input. A second summer receives the signal input at a minus input and the output of the sixth delay element at a plus input, and drives a right two bit shifter.

Abstract: An efficient apparatus for performing frequency conversion from a final IF frequency to a baseband frequency is described. A counter (401) generates two logical signals G1 (402) and G2 (403) which are passed to an exclusive-OR gate (404) and a multiplexer (406). When a control signal (411) is deasserted, multiplexer (406) passes signal G1 to I1 and signal G2 to I2; when control signal (411) is asserted, multiplexer (406) passes binary signal G1 to I2 (410) and signal G2 to I1 (407). Similarly, multiplexer (405) swaps its input real and imaginary samples when the output of exclusive-OR gate (404) is asserted; otherwise, it performs no operation on its input samples. Signals I1 (407) and I2 (410) are used to control arithmetic inverters (408) and (409) respectively. When the controlling signal for either inverter is asserted, the inverter performs arithmetic inversion, otherwise it performs no operation.

Abstract: In quadrature amplitude modulation, circular concentric decision regions capitalize on the observation that when the sample matrix is rotating, it is possible to identify samples more accurately by the radius of their orbit rather than their phase at any given time. The first embodiment provides that a scalar 1.sub.i is calculated for each constellation point so that the constellation point corresponding to the minimum 1.sub.i value is the symbol which the decision device decides was transmitted. The nearest constellation point having the minimum magnitude difference represents the decision. In the second embodiment, two complementary weighting factors are used to provide a weighted average of the two decision criteria in order to make the correct decision. .alpha. is the weight for representing standard rectangular decision regions, while (1-.alpha.) is the weight for representing the circular decision regions. The range for .alpha. is 0<.alpha..ltoreq.1. The variable .alpha.

Abstract: A digital quadrature demodulator for an intermediate frequency (IF) input signal with an analog-to-digital (A/D) converter having a sampling frequency f.sub.s and an input to which the IF input signal is applied where the IF input signal has a bandwith B<f.sub.s /4 centered about a frequency of f.sub.s /4. The demodulator includes an arrangement to direct even numbered output signals from the A/D converter to an inphase channel and odd numbered output signals from the A/D converter to a quadrature channel where each channel contains a highpass filter and the demodulator includes circuits to decimate by 4 signals of the channels to generate, together with the filters, a quadrature output signal Q(nT) at an output of the quadrature channel and an inphase output signal I(nT) at an output of the inphase channel. The quadrature highpass filter in the quadrature channel has an optimized transform architecture in which the filter coefficients h.sub.

Abstract: A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier and then subjected to frequency conversion by a frequency converter including: an exclusive OR element; a running average generator consisting of a shift register and an adder; and a comparator. In response to the output of the frequency converter, the phase comparator outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator includes: an exclusive OR element; an absolute phase shift measurement means consisting of an adder and D flip-flop arrays and; and a D flip-flop serving as a phase shift polarity decision means.

Abstract: For a demodulator for radio data signals, where transmission of these signals is carried out through phase shifting of a suppressed subcarrier, where a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, the amplitude-limited signal having a subcarrier frequency is transformed into digital sampling values, if necessary by additional filtering, and the sampling values are supplied to at least one phase control loop for deriving a bit clock signal.

Abstract: In a demodulator for radio data signals the transmission of which is made by phase-keying of a suppressed subcarrier the occurence of transient times is avoided in that the received signal of subcarrier frequency is transformed into a first square wave signal (A) and that a second square wave signal of subcarrier of frequency is formed which is brought into such a time relationship to the first square wave signal that by means of a comparison of both square wave signals a phase information for the first square wave signal (A) is obtained. Demodulator can be implemented by means of only digital components.

Abstract: A quadrature demodulator includes a device for generating first and second reference signals having a quadrature relation with each other. A first demodulating device serves to compare phases of the first reference signal and an input modulated signal to demodulate the input modulated signal into a first binary baseband signal. A second demodulating device serves to compare phases of the second reference signal and the input modulated signal to demodulate the input modulated signal into a second binary baseband signal having a quadrature relation with the first baseband signal. A first counting device operates to count pulses of a clock signal in response to the first baseband signal. A second counting device operates to count pulses of the clock signal in response to the second baseband signal. An address signal is generated in response to the output signals of the first and second counting devices.

Abstract: In a demodulator for use in the Radio Data System (RDS) as defined by the European Broadcasting Union, transmission of these signals is carried out through phase shift modulation of a suppressed subcarrier, a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, and the amplitude-limited signal, having a carrier frequency, is sampled at a sampling frequency that is a multiple of the frequency of the subcarrier. The sampling values are summed over a preset portion of one period of the subcarrier. The summed sampling values are supplied to a digital signal processing circuit.

Abstract: A bi-phase shift keying signal demodulation circuit for an RDS receiver receives RDS modulation signal and reproduces RDS data from the RDS modulation signal. The RDS modulation signal is produced by modulating a sub-carrier by a signal modulated by a bi-phase shift keying modulation using the RDS data.

Abstract: A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates.

Abstract: An AFC method is used in a demodulator, which employs a 2.sup.n -phase phase shift keying modulation system, where n is an integer greater than or equal to two, to correct an error between a received carrier frequency and a local frequency. The AFC method includes the steps of (a) subjecting an intermediate frequency signal of a signal received by the demodulator to a quadrature wave detection to obtain I-axis and Q-axis signals, (b) converting amplitude information of the I-axis and Q-axis signals into phase information which includes frequency information, and (c) correcting the local frequency based on the frequency information included in the phase information.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to a phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement circuit 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision circuit.

Abstract: This patent application discusses a direct phase digitizing apparatus (303) for use in a radiotelephone (101). The direct phase digitizing apparatus (303) accepts a first analog signal (309) having a phase, a voltage range and a first frequency. First, the direct phase digitizer generates an estimated phase map (611) having a second frequency and N-bits of resolution. Second, the direct phase digitizer detects a predetermined-voltage crossing (409) of the first analog signal (309). Third, using the predetermined-voltage crossings, the direct phase digitizer samples the estimated phase map. Fourth, a digital phase signal (623) is generated using the samples of the estimated phase map.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A low-bit-rate, low-cost, all-digital preambleless demodulator for maritime and mobile data communications operates under severe high noise conditions, fast Doppler frequency shifts, large frequency offsets, and multipath fading. Sophisticated algorithms, including an FFT-based burst acquisition system, a cycle-slip resistant carrier phase tracker, an innovative Doppler tracker, and a fast acquisition symbol synchronizer, provide reliable burst reception. The compact DSP-based demodulator includes an input buffer receiving a complex sampled baseband input signal and providing a baseband output to a coarse frequency estimator fast Fourier transform (FFT) or discrete Fourier transform (DFT) module which produces a first estimation of the carrier frequency. A fine frequency estimator FFT or DFT module receives the first estimation and provides a second estimation of the carrier frequency. An extra coarse frequency estimator FFT or DFT module may be provided between the buffer and the coarse frequency estimator.

Abstract: A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream.

Abstract: The present invention is directed to a differential phase-shift keying (PSK) signal demodulator in which an error rate provided when a signal modulated according to a .pi./4-shift DQPSK modulation system is demodulated can be improved. The differential PSK signal demodulator of the present invention includes means for phase-shifting a phase of a detection reference axis by a predetermined angle each in the counter-clockwise direction in synchronism with a timing at which a symbol to be detected is supplied, wherein the modulated signal is synchronizing-detected such that a rotation angle of the symbol and an angle of a detection reference axis are inhibited from becoming equal to each other, thereby a zero level being prevented from being output as a demodulated output.

Abstract: A data recovery system for deriving digital data from a bi phase encoded stream wherein signal transition occurs at mid-bit or bit boundary having an edge detector for detecting the occurrence of each fallen edge of a data stream, an edge decoder connected to the detector for determining the time between successive falling edges, a falling edge identifier connected to the edge decoder for determining whether a detected fallen edge occurs on a bit boundary or at a mid-bit, a falling edge memory connected to the falling edge identifier for remembering whether the previous falling edge occurred at a bit boundary or at mid-bit, a data decoder connected to receive input from the falling edge memory and the edge decoder, and having logic for determining the recovered data according to a table in which the data is identified in response to the occurrence at a bit boundary or at mid-bit and a selected spacing between falling edges.

Abstract: A demodulator for biphase, suppressed-carrier PSK signals, in particular useful for the demodulation of digital information transmitted as an auxiliary information in radio transmission channels, in particular of the "radiodata" kind comprising a filter for the extraction of the portion of the base band spectrum carrying said PSK signals, an amplitude limiter connected to the output of said filter for standardizing the amplitude of said PSK signals, a double-loop circuit receiving the limiter signal comprising a first loop associated with a data transition tracking loop decoder; a second loop constituted by a digital phase-locked loop. The double loop circuit cooperates with a stable oscillator for providing a frequency at a predetermined multiple of the frequency of the suppressed carrier of said PSK signal from the limiter signal.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: A differential phase demodulator for demodulating a PSK-modulated signal including a zero-cross detector for detecting zero-cross points of intermediate frequency signals of the PSK-modulated signal and generating a zero-cross detection signal; a synchronization circuit for synchronizing an externally supplied baud timing signal with the zero-cross detection signal; an oscillator for generating clock pulses; a counter for counting the clock pulses and producing a pulse count; a phase difference detector for calculating the count per period of the synchronized baud timing signal and outputting the result as the phase difference data; and a decision circuit for outputting demodulated data based on the phase difference data.

Abstract: A phase demodulator for directly demodulating carrier PSK signals, PSK-modulated with digital signals, without using any analog circuit. Where the invention is applied to a demodulator of the different detection type, the baud timing signal is converted into a synchronous band timing signal, synchronized with the first leading edge of the PSK signals converted into "1" or "0" in logical level. Meanwhile, the ring oscillator generates signals of a frequency substantially equal to the carrier frequency of the PSK signals, and generates outputs at N taps. the outputs obtained at the N taps have a 2.pi./N phase difference between every pair of mutually adjoining taps, and are latched with the synchronous baud timing signal in each baud period. The point at which the logical level of mutually adjoining latch outputs varies from "1" to "0" is the phase information of said digital signals. The corresponding phase information is encoded to constitute the demodulated output.

Abstract: A data referenced demodulator is provided for recovering differentially encoded multiphase modulated digital data such as QPSK modulated audio data. An analog carrier containing the differentially encoded QPSK data is converted to a digital waveform at an intermediate frequency that is a multiple of the QPSK bit frequency. The digital waveform is delayed in a shift register that samples the waveform at a clock rate which is a multiple of the intermediate frequency. Different stages of the shift register output the digital waveform one bit time earlier plus 45.degree. and one bit time earlier minus 45.degree.. These outputs of the shift register are multipled with the digital waveform using exclusive OR gates to provide differential QPSK detection. The shift register sampling clock is phase locked to a system master clock, which in turn is locked to the received data. In an illustrated embodiment, the sampling clock is 24 times the intermediate frequency, providing 15.degree. phase resolution.

Abstract: A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from said accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.

Abstract: In a demodulator circuit which is simple in construction, a PSK modulated signal is converted in frequency into a quasi-base band signal and is then subjected to complex separation. Partly since a phase angle sampled from a digital complex signal is supplied to a differential-detector circuit, and partly since the differential-detector circuit processes only the phase angle, the differential-detector circuit has a simple construction. As the detected phase difference between two successive symbol data, an error between a carrier wave contained in the modulated signal and a locally oscillated frequency on the receiving side is compensated and is outputted as a digital demodulated signal.

Abstract: A binary encoded phase modulated signal (biphase signal) is demodulated by determining the period of time (T) elapsing between each two successive jumps in the level of the biphase signal; providing a clock frequency (B) approximately corresponding to the bit rate of the biphase signal with the aid of a clock generator; comparing the clock duration (1/B) of the clock frequency with the period of time (T) between each two jumps in level; and, with the aid of a sample and hold circuit controlled by the clock frequency (B), always ascertaining the logical value of the biphase signal and emitting a signal corresponding to the logical value whenever, immediately prior to a bit period, twice in succession, a value between 1/4 and 3/4 of 1/B is ascertained for the period of time (T), or a value between 3/4 and 5/4 of 1/B is ascertained for the period of time (T).

Abstract: A carrier lock detector for a quadrature amplitude modulation system includes Exclusive-OR gating circuits for determining when detected signal points occur within first areas centered on signal point positions in a phase plane diagram or second areas between the signal point positions, and for producing corresponding output signals. An integrated difference between these output signals is produced by an integrator and compared with a threshold level to provide a carrier lock detection signal. The arrangement is such that the integrated difference is substantially zero when the carrier is unlocked, so that the threshold level can be set to a low value to enable reliable operation of the detector at low signal-to-noise ratios.

Abstract: A conventional demodulator for digital transmission includes means (12) for splitting the received HF signal into two identical auxiliary signals, mixers (20, 30) for transposing the auxiliary signals into in-phase and quadrature baseband components by multiplying them with in-phase and quadrature output signals from a local oscillator (14), and respective filter and amplifier means (22, 24; 32, 34) and analog-to-digital converters (26, 36) on the in-phase and quadrature channels. In addition, the demodulator includes estimation means (100) suitable for estimating faults on groups of samples (Y.sub.p,k, Y.sub.q,k) taken from the outputs of the analog-to-digital converters (26, 36), with the faults being estimated in the form of five parameters, and correction means (200) for correcting current samples (Y.sub.p, Y.sub.q) on the basis of the parameters estimated on an earlier group of samples.

Abstract: In a digital device having an input thereto comprising a digital sample stream at a frequency F, a method for employing a component therein designed to work at a frequency less than F. The method in general comprises the steps of, dividing the digital sample stream into odd and even digital sample streams each at a frequency of F/2; passing one of the digital sample streams through the component designed to work at a frequency less than F wherein said component responds only to the odd or even digital samples in the one of the digital sample streams; delaying the other of the digital sample streams for the time it takes the one of the digital sample streams to pass through the component; and, adding the one of the digital sample streams after passing through the component with the delayed other of the digital sample streams.

Abstract: A demodulation clock generator circuit employed in a modulation system such as a bi-phase mark system is improved by including a frequency detector to speed up the initial processing of a data signal to be demodulated. The frequency detector generates a frequency detection signal which corresponds to a signal from an oscillator and a signal from a synchronization signal portion of the signal to be demodulated. The frequency detector includes a memory portion clocked by the oscillator for storing the states of the signal to be demodulated and a signal generating portion for supplying the frequency detection signal when information stored in the memory portion is the same as a synchronizing portion of the signal to be demodulated and has a frequency of less than a predetermined value.