Abstract: Various embodiments relate to an amplitude shift keying (ASK) demodulator for demodulating an input signal, including: a frequency filter configured to receive the input signal, wherein the frequency filter includes adjustable components configured to adjust the frequency response of the frequency filter; a rectifier configured to rectify an output of the frequency filter, wherein the rectifier includes an adjustable current source configured to adjust the current consumption of the rectifier; a reference signal generator configured to produce a reference signal; a current to voltage converter configured to convert the current of the rectified signal to a rectified voltage and to convert the current of the reference signal to a reference voltage; and a comparator configured to compare the rectified voltage to the reference voltage and to produce a demodulated output signal.

Abstract: A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled oscillator to a second oscillator both comprised in the integrated circuit, wherein both controlled oscillators are configured to output a respective clock signal. The arrangement comprises a detector adapted to detect the crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, a crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and a cancellation signal injector adapted to introduce the cancellation signal into the second controlled oscillator.

Abstract: A communication system includes a first amplifier configured to output an amplified modulated signal, and a demodulator coupled to the first amplifier. The demodulator is configured to demodulate the amplified modulated signal responsive to a first carrier signal. The demodulator includes a filter and a bandwidth adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal and a set of control signals. The filter has a bandwidth adjusted based on the set of control signals. The bandwidth adjusting circuit is coupled to the filter, and is configured to generate the set of control signals based on a frequency of the filtered first signal and a frequency of the first signal. The bandwidth adjusting circuit includes a frequency detector configured to generate a second signal based on the frequency of the filtered first signal and the frequency of the first signal.

Abstract: An efficient baseband predistortion linearization method for reducing the spectral regrowth and compensating memory effects in wideband communication systems using effective multiplexing modulation technique such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. The present invention is based on the method of piecewise pre-equalized lookup table based predistortion, which is a cascade of a lookup table predistortion and piecewise pre-equalizers.

Abstract: In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in a receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver.

Abstract: In conventional radio frequency (RF) systems, transmitters will usually convert baseband signals to RF so as to be transmitted. As part of the conversion process, the transmitters will perform digital predistortion (DPD), which uses feedback from a power amplifier. However, there are usually mismatches between the in-phase (I) and quadrature (Q) paths within with feedback loop. Traditional IQ correction filters were ineffective at providing adequate compensation for these mismatches, but here a filter is provided that provides adequate out-of-band compensation by use of frequency selectivity.

Abstract: A communications device includes a modulator and a filter downstream therefrom and operable to generate an output wideband complex signal with a frequency notch therein. The filter includes a finite impulse response (FIR) filter with L taps to generate N output values, with L>N. A Fast Fourier Transform (FFT) block is downstream from the FIR filter and has a length N so that filter transition regions occur between frequency bins of the FFT block. A notching block is downstream from the FFT block to generate the frequency notch. An Inverse Fast Fourier Transform (IFFT) block is downstream from the notching block and has the length N.

Abstract: In some embodiments, a method of reducing adjacent channel power ratio and compensating memory effects of multi-channel wideband communication systems using multiplexing modulation techniques is provided. The method includes generating an address from samples of a baseband input signal of a communication system. The method also includes retrieving from a memoryless lookup table an entry in accordance with the address. The method further includes pre-equalizing the baseband input signal, the pre-equalization depending on one or more magnitudes of the input signal. The method still further includes multiplying the pre-equalized baseband input signal and the lookup table entry.

Abstract: RFID readers, reader systems, and methods are provided that utilize double conversion for received tag response signals. A digitized signal is derived from the tag response signal by first shifting the response signal to about DC. The components of the digitized signal are then up converted and down converted and filtered such that only components around DC remain. The up converted and down converted signals may then be compared and one selected or the two combined after weighting to enhance demodulation and reduce circuit complexity.

Abstract: RFID tags are commanded to generate a pilot tone in their backscatter. When the backscattered pilot tone is received in the reader, the pilot tone is used to estimate the tag period/frequency. Then, the estimate is used to seed and lock a symbol timing recovery loop, which provides a detected signal to one or more correlators for detecting the tag preamble. A delayed version of the received tag signal is compared against a baseline signal threshold established from the received signal to detect the pilot tone.

Abstract: Techniques for detecting and mitigating interference are described. A device (e.g., a cellular phone) senses interference levels and digitally reconstructs the expected interference in the received signal. The device may correlate the reconstructed interference with the received signal and determine interference in the received signal based on correlation results. The device may adjust the operation of one or more circuit blocks (e.g., a mixer, an LNA, etc.) in a receiver based on the detected interference in the received signal. Alternatively or additionally, the device may condition the digital interference to obtain conditioned reconstructed interference matching the interference in the received signal and may then subtract the conditioned interference from the received signal.

Abstract: A radio receiver which performs iterative decoding of a received signal is provided. The radio receiver comprises: a receiving unit receiving a signal on a symbol-by-symbol basis; a demodulation unit (303) demodulating the received signal; a last symbol timing generation unit (308) generating a last symbol timing signal on the basis of the signal demodulated by the demodulation unit (303); a modulation unit (304) modulating the signal demodulated by the demodulation unit (303); and a cancellation unit (306) cancelling an interference component of the received signal using a replica signal generated on the basis of the signal modulated by the modulation unit (304). The modulation unit (304) controls the timing of rearrangement of a data sequence on the basis of the timing of the last symbol. Thus, a radio receiver in which the receiving processing time is reduced can be provided.

Abstract: A receiver estimates I/Q imbalance in I and Q input signals using circuitry to separate different frequency components of the I and Q input signals, and estimation circuitry arranged to estimate I/Q imbalance at the different frequency bands. The separating of the bands may be carried out in the frequency domain, and may involve combining corresponding values representing corresponding negative and positive frequency bands, and converting the separated frequency domain representations to a time domain representation before the estimation. The estimated imbalance may be used to correct the I and Q signals at the different frequency bands.

Abstract: A receiver includes a band-pass filter that limits a passband of an IF (Intermediate Frequency) signal, an FSK detector that detects the IF signal passing through the band-pass filter to generate a detection signal, and a control block that controls a modulation sensitivity of the FSK detector and a pass bandwidth of the band-pass filter, in which the control block controls the modulation sensitivity of the FSK detector according to the pass bandwidth of the band-pass filter.

Abstract: Embodiments of the invention are concerned with correction of quadrature errors associated with digital communications systems, and in particular in a wireless transmit chain in which an up-converter and a down-converter both have a direct conversion architecture. One embodiment comprises a correction network for correcting a difference between a transmission characteristic of an in-phase signal path and a transmission characteristic of a quadrature signal path, said quadrature signal path being for the transmission of in-phase and quadrature parts of a signal and the signal comprising frequency components within a base band, wherein the correction network comprises an in-phase input port, a quadrature input port, an in-phase output port and a quadrature output port, wherein each input port is connected to each output port by a digital filter network, the digital filter network comprising a set of filter tap coefficients and configuration means for configuring values of said set of filter tap coefficients.

Abstract: A phase noise correction device having a function for accurately detecting a phase noise component and capable of reducing a load on a reception device is provided. A phase noise correction device for correcting a phase noise generated in a local oscillator includes: a division section that divides a signal generated in the local oscillator; a reference signal generation section that generates a signal of the same frequency as that of the divided signal; a phase difference detection section that detects a phase difference between the divided signal and the generated reference signal; and a phase noise correction section that gives a phase rotation to a baseband signal in the direction that cancels the phase noise according to the detected phase difference as a phase noise component.

Abstract: Disclosed is an improved noise reducing apparatus using an anti-circuit, including a digital logic circuit and a digital anti-circuit corresponding to the digital logic circuit. The digital anti-circuit functions to cancel noise generated by the digital logic circuit. The anti-circuit includes logic to generate a similar number of switching edges as the logic circuit, where the anti-circuit edges are in the opposite direction as the logic circuit. The anti-circuit may have a circuit structure close to that of the noisy circuit, or can be formed of components different in structure but generating an output pattern similar to (and opposite from) the noisy circuit. In some embodiments, the differently structured components can include a state machine coupled to a memory or look-up-table.

Abstract: Disclosed is an improved noise reducing apparatus using an anti-circuit, including a digital logic circuit and a digital anti-circuit corresponding to the digital logic circuit. The digital anti-circuit functions to cancel noise generated by the digital logic circuit. The anti-circuit includes logic to generate a similar number of switching edges as the logic circuit, where the anti-circuit edges are in the opposite direction as the logic circuit. The anti-circuit may have a circuit structure close to that of the noisy circuit, or can be formed of components different in structure but generating an output pattern similar to (and opposite from) the noisy circuit. In some embodiments, the differently structured components can include a state machine coupled to a memory or look-up-table.

Abstract: A combined PLL and ALL module for switching FM signals includes a PLL unit and an ALL unit electrically connected therewith. The PLL unit is used to initially process FM signals received from a co-channel. Outputs of the PLL unit are sent to the ALL unit and processed therein. The PLL unit and the ALL unit are controlled to process the FM signals by adjusting the ratio of second amplitude to first amplitude to closely approach a predetermined value such that the two FM signals are switched.

Abstract: A combined PLL and ALL module for switching FM signals includes a PLL unit and an ALL unit electrically connected therewith. The PLL unit is used to initially process FM signals received from a co-channel. Outputs of the PLL unit are sent to the ALL unit and processed therein. The PLL unit and the ALL unit are controlled to process the FM signals by adjusting the ratio of second amplitude to first amplitude to closely approach a predetermined value such that the two FM signals are switched.

Abstract: This method reduces the variance of the estimation of the signal-to-noise rate in a multiuser digital communications system. These communications require a sending of a phase reference symbol prior to sending a information, where the estimation is made of the signal-to-noise rate in order to use a modulation with a maximum number of bits per symbol, maintaining a bit error probability in reception within certain given margins. The method minimizes and equalizes the variance of the samples obtained for the different values, even and odd of bits per carrier, which the system uses. The estimation is necessary for selecting the number of bits per carrier in order to be adapted to the channel and as back-up information in the event of using a receiver with diversity.

Abstract: A tuner and a demodulating unit thereof are provided. A trap filter for a specific frequency is installed in the IF demodulating unit so as to eliminate a frequency signal acting as a beat component.

Abstract: The present invention has a N pieces of receiving antennas, a propagation path characterization estimator, a weight generator for interference canceller, an array processing interference canceller, a weight generator for signal estimator, a signal estimator, a transmission signal classification apparatus, and a decoding order decision apparatus. The antenna inference elimination circuit eliminates only signal component relating to transmission signal component which does not belong to groups. The signal estimator performs separation and decoding of the transmission signal belonging to the group. The transmission signal classification apparatus classifies the transmission signals from sets of the transmission antennas in which a cross-correlation value of the vector is larger than a threshold value, into one group, and classifies the transmission signal in which the cross-correlation value is smaller than the threshold value, into another group.

Abstract: A noise blanker (40, 106) monitors and removes noise from a sampled signal by adaptive filtering (98, 150) the sampled signal to generate trained adaptive filter prediction coefficients. The sampled signal is provided as an output signal when the noise blanker is in a training mode. A noise monitor (34, 154) detects whether noise contained within the sampled signal exceeds a predetermined threshold and provides a control signal in response to the detecting. The noise blanker is placed in a prediction mode for a predetermined amount of time in response to asserting the control signal. A prediction output signal is generated using a plurality of prediction coefficients as an all-pole filter. The prediction output signal has minimal noise content.

Abstract: A method for providing maximum likelihood detection with decision feedback interference cancellation is provided. The method includes estimating a current symbol with previous symbol interference (PSI) removed based on estimated previous symbols. A next symbol is estimated with PSI removed based on the estimated current symbol and/or the estimated previous symbols. The current symbol is re-estimated with PSI removed based on the estimated previous symbols and next symbol interference (NSI) removed based on the estimated next symbol. This method of providing maximum likelihood detection with decision feedback interference cancellation may be used in direct sequence spread spectrum systems with relatively short block spreading, such as IEEE802.11b Wireless LAN standard, or in any other suitable systems.

Abstract: A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a reference frequency, which corresponds to the nominal mid-frequency of the demodulator, which is a function of the resistor and the capacitor. Any discrepancy between the actual mid-frequency of the demodulator and its nominal mid-frequency leads to the production of a voltage that differs from a nominal voltage at the output. A detector detects this error and adjusts the values of the resistor or capacitor until the error between the nominal voltage and the voltage is zero or is a minimum. The described principle can be used, for example, in integrated mobile radio receivers.

Abstract: An FM signal receiver for use in receiving a burst signals as in a Bluetooth system includes a BPF and a frequency-demodulation circuit, each having, for example, a phase shifter, which is constructed from similar or related circuitry so as to enable adjustment of the frequency characteristics of the BPF and frequency-demodulation circuit through an identical control signal. A short-circuit switch is disposed linking the input and output terminals of an amplifier. A control circuit opens the switch in a receiving operation and closes the switch in an adjusting operation. Thus, adjustment is carried out without using the amplifier. Therefore, an amplifier offset does not affect the frequency-to-voltage conversion by the frequency-demodulation circuit in the adjusting of the frequency-demodulation circuit and similar adjusting of the BPF. Thus, the BPF is prevented from being incorrectly adjusted due to the offset. The BPF characteristics are suitably adjusted.

Abstract: A demodulator includes a reference signal generator for generating a reference signal, an FM demodulation circuit for demodulating a modulated signal, and a control circuit for controlling demodulation sensitivity of the FM demodulation circuit. The control circuit controls the demodulation sensitivity of the FM demodulation circuit so that an output signal, obtained when the reference signal from the reference signal generator is inputted to the FM demodulation circuit, becomes a specified value. This structure can stabilize the demodulation sensitivity of the demodulation circuit while restraining increases in circuit scale and current consumption, and can adjust dispersions in the demodulation sensitivities of the respective ICs due to relative errors of a resistance value of a resistor and a capacity value of a condenser in an IC, the resistor and the condenser constituting the demodulator.

Abstract: A high-performance demodulator for use in UWB (Ultra WideBand) multiple-access communication is disclosed. In a communication device, the correlation between a received signal corresponding to signals transmitted from a plurality of communication terminals by means of UWB (Ultra WideBand) communication and pulses at possible positions in a signal transmitted from each communication terminal is calculated. On the basis of the resultant calculated correlation, and taking into account interference among the signals transmitted from the communication terminals, the received signal is demodulated into original data issued by the respective communication terminals.

Abstract: A method and modem for communicating serial input data over a transmission link are disclosed. Serial input data is partitioned into parallel data elements prior to rotation by an invertible linear mapping. Computationally efficient multi-rate wavelet filter banks are employed in a receiver for analyzing a received signal. Self-interference components are calculated in the receiver per sub-band and tap-weights for the filter banks are derived as a function over the range of self-interference values. A weighted sum is formed and subtracted from the delayed, received signal to eliminate the interference, and is removed from the recovered signal.

Abstract: In a circuit arrangement for demodulating signals, particularly frequency-modulated signals, in which a limiter, to whose input the signals to be modulated can be applied, is followed by a demodulator from whose output the demodulated signals can be derived, the outputs of the demodulator and the limiter are connected to a respective input of a mixer whose output is connected to the input of the limiter via a low-pass filter.

Abstract: A digital FM demodulator converts a digital FM input signal to a demodulated signal, detects the amplitude of the digital FM input signal, generates a corresponding amplitude signal, and adjusts the amplitude of the demodulated signal according to the amplitude signal, thereby compensating for variations in the amplitude of the digital FM input signal and removing amplitude distortion from the demodulated signal. This reduces the performance requirements of, for example, a low-pass analog filter preceding the digital FM demodulator in an FM radio broadcast receiver, permitting the analog filter to be implemented in a semiconductor integrated circuit.

Abstract: The demodulator according to the invention comprises a negative feedback loop which slowly compensates for a DC potential of a demodulated signal through an integrator formed of a resistor and a capacitor, and a negative feedback loop which senses a amplitude of a demodulated signal and rapidly charges or discharge the capacitor in response to the result of the sensing, wherein the two negative feedback loop operate independently of each other.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: A demodulator circuit for demodulating a frequency modulated input signal includes a filter (12) for receiving an incoming input signal and for providing a filtered output signal, a detector (16) for receiving the filtered output signal, and for producing a demodulated output signal therefrom, a tuning circuit (18, 20) which is operable to introduce a test signal into the demodulator circuit in the absence of an incoming input signal, and to vary the frequency response characteristics of at least one of the filter and detector in response to the test signal.

Abstract: A reference signal source produces a substantially distortion free reference signal which is supplied to a demodulator that is arranged to demodulate the substantially distortion free reference signal. A calibration filter and an equalizer are included downstream of the demodulator. A controller sets the calibration filter to initially pass the reference signal to the equalizer without substantial change to the reference signal. The controller subsequently calibrates the calibration filter in accordance with the demodulator caused distortion reduced by the equalizer.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select desired loop gain.

Abstract: An FM demodulator circuit includes a filter (10) and a detector (14) for receiving a frequency modulated input signal and for providing a demodulated output signal. A tuning circuit (19) is provided for tuning the frequency characteristics of the filter and of the detector. A DC offset estimator (18) is connected to the output of the detector to produce an offset signal representing the estimated DC offset of the demodulated output signal, and to provide the offset signal to the tuning circuit. The tuning circuit is operable to tune the frequency characteristics of the filter and detector in dependence upon the offset signal.

Abstract: Known is a zero intermediate frequency receiver or zero-IF receiver in which DC-offset correction is done in the I- and Q-paths, after mixing down of the received RF-signal or of an IF-signal. Such a DC-offset correction is not sufficient for high gain I- and Q-paths, particularly not in pagers for receiving long messages. Furthermore, no optimal power saving is achieved if such a receiver alternately operates in receive mode and sleep mode. A zero intermediate frequency receiver is proposed in which DC-offset correction is distributed over the high gain I- and Q-path. Preferably, blocking means are provided between DC-offset correction circuits and low pass filters in the I- and Q-path to prevent that an output signal of an upstream DC-offset correction circuit in the path excites a downstream low pass filter in the path during DC-offset correction. Herewith, considerable power savings are achieved.

Abstract: Receiver having an RF input for applying an RF input carrier-modulated modulation signal thereto, which receiver is coupled to a multiplier circuit and to a phase-locked loop (PLL) with a signal path incorporating a phase detector, a loop filter, a first dc decoupling circuit and a controlled oscillator having an in-phase and a quadrature output via which local in-phase and quadrature carriers are applied to the multiplier circuit and the phase detector, respectively, and a signal generator for generating a local auxiliary pilot and a pilot detector for detecting the local auxiliary pilot, an output of which is coupled to the controlled oscillator via a low-pass filter.

Abstract: This invention relates to telecommunications systems. The present invention provides a system and method operable to the cancel interference from digital subscriber line systems. A data signal demodulator having first and second inputs arranged to receive differential data signals and local field RFI signals respectively, wherein a digital adaptive notch filter is formed by DSP means which locates an interferer in the differential signal by adapting its bandwidth and center frequency by adaptation means and wherein the center frequency and bandwidth of the notch filter are used to generate a bandpass filter centered on the interferer and of approximate bandwidth to the interferer; whose output, after processing forms a feedback signal which is sampled, processed, weighted and then combined with the local field RFI input signal of the demodulator, which combined signal is summed with the differential input signal to thereby cancel interference coupled onto the first input.

Abstract: A FM (Frequency Modulated) DCFB (Deviation Compression Feedback) signal demodulator can be achieved by utilizing FM deviation compression feedback techniques. An FM signal is coupled to a mixer (10) wherein a signal from a local oscillator is mixed with the input signal. The output of the mixer is then coupled to a variable selective IF amplifier. The IF amplifier couples the signal to a limiter amplifier, the output of the limiter amplifier is FM demodulated and fed to an output. The output signal is simultaneously fed back through a variable Frequency Compensation Network (FCN) (Loop Filter). The output signal of the FCN is then fed back to a local oscillator (17). The output of the local oscillator (17) is in turn fed back into the original mixer (10). The improved demodulated signal is sampled at an output (26).

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. An FM input signal including the carrier wave is supplied to a phase detector in the phase locked loop. The output of the phase detector is filtered and used to generate a signal for use in controlling a voltage controlled oscillator having an output also connected to the phase detector. The phase locked loop is tuned to a selected carrier wave frequency and a variable gain setting of a variable gain circuit in the phase locked loop is selected to select a desired loop gain. The signal for use in controlling the voltage controlled oscillator is varied by the variable gain circuit to alter the amount by which the frequency of the output of the voltage controlled oscillator changes in relation to a given output of the phase detector. The variable gain setting is selected to select a required bandwidth for demodulation.

Abstract: A portion of a FSK signal is encoded with a central frequency (f.sub.0) and the FSK signal is transmitted. A receiver captures the transmitted FSK signal, and demodulates the FSK signal to provide and analog data signal. The analog data signal is DC coupled to a first input of a comparator. The comparator generates a logic level binary output corresponding to the FSK signal. A second input of the comparator is coupled to a bias circuit. Preferably the bias circuit is provided by a digital to analog convertor (DAC). A control circuit detects the predetermined portion of the FSK signal in which the center of frequency is being transmitted. During the predetermined portion the control circuit samples the binary logic level output of the comparator, converts the binary logic level output to a digital error word, and uses the digital error word to control the DAC.

Abstract: An FM demodulator having two input terminals (11, 12), to which FM input signals having 90.degree. phase relation are applied, the said FM demodulator including a phase comparator (1) and a tunable, phase shifting circuit (2), the phase shifting circuit (2) being tuned by the FM demodulator output signal via a feedback path comprising a loop, filter. By adding a compensation filter (5) to the tuning control loop the phase shifting circuit is effectively cancelled from the tuning control loop, thereby making the tuning control loop independent of the bandwidth of the phase shifting circuit (2). Thus the bandwidth of the phase shifting circuit (2) can be reduced for threshold extension.

Abstract: An automatic offset control circuit comprises a differential output preamplifier having an offset adjustment function, further comprising an average detector, a peak detector, and a differential input amplifier. The average detector generates a reference voltage representing an average value of a positive output and a negative output of the preamplifier. The peak detector outputs a peak voltage representing a peak of the negative output of the preamplifier. The differential input amplifier compares the peak voltage with the reference voltage to output an offset adjustment signal to the preamplifier. The offset adjustment signal is obtained based on a difference between the reference voltage and the peak voltage. A bottom detector may be used instead of the peak detector, provided a bottom value is detected using the positive output of the preamplifier.

Abstract: An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

Abstract: A demodulator circuit and a demodulating method are disclosed. A demodulator including a phase-locked loop for a receive carrier recovery or a phase lock recovery demodulates an input received signal and a band of a loop filter of the phase-locked loop is controlled by a control signal. A bit error rate monitor detects a bit error rate of a demodulated outputs the control signal on the basis of the bit error rate result of the demodulator, and a loop filter band controller output from the bit error rate monitor. Hence, the bit error rate of the demodulated signal is detected and the loop filter band of the phase-locked loop of the demodulator is controlled based on the detected bit error rate. As a result, an exact control of the loop filter band of the demodulator can be performed on the basis of the received signal state without using any received signal power detector, any C/N detector or the like.

Abstract: A frequency demodulation circuit having an improved detection sensitivity is provided by forming an all-pass equalizer in a Quadrature-type demodulator capable of allowing a band covering at least a carrier frequency deviation to pass therethrough. The equalizer comprises a band-pass filter for detecting the frequency deviation of an inputted FM carrier signal, a gain-doubling amplifier and a substractor for performing subtraction between the signal inputted to the band-pass filter and the output of the amplifier. The operation of the circuit is such that a FM carrier signal is supplied to the band-pass filter through a phase shifter and to a phase comparator and the output of the substractor and the FM carrier signal are compared to each other by the phase comparator to thereby obtain a FM demodulated signal.

Abstract: In an FM television signal angle modulated with luminance and chrominance information, there exists a high degree of correlation between picture elements occurring one line period apart. In an effort to steer the pass band of a tunable bandpass filter to the instantaneous frequency of the incoming television signal, a steering signal is developed which utilizes this high degree of correlation. For NTSC systems, luminance information is delayed by one-line period (63.5 us in the U.S.A.) and combined with suitable delayed chrominance information to form the filter's steering signal. For MAC systems, one-line delayed luminance and two-line delayed chrominance information are alternately applied to the filter as its steering signal. By steering the pass band of the filter to the incoming signal, maximum signal will be captured with minimum noise, enhancing the signal-to-noise ratio of a color television system.