Abstract: An apparatus is provided for on-chip reconstruction of transient settling behavior. The apparatus comprises a first sampling circuit configured to sample a tracked analog signal output from a circuit under test over an operating period at a first sampling time, thereby generating a first sample output. In addition, the apparatus comprises a second sampling circuit configured to sample the tracked analog signal output at a second sampling time, thereby generating a second sample output. The apparatus further comprises a signal subtraction circuit configured to perform subtraction of the first sample output and the second sample output, thereby generating a difference signal. Moreover, the apparatus comprises a signal conversion circuit configured to output the difference signal in the digital domain.

Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).

Abstract: Frequency domain (FDTF) and time domain (TDTF) trans-filters compress in-band AWGN, demodulate input signals and have no threshold due to applied noise. Two parallel frequency selective networks with opposite amplitude vs frequency slopes are designed to remain 180 degrees out of phase over the signal band in the FDTF whereas two parallel delay networks are used in the TDTF. Output amplitudes are equal at band center and are summed producing a monotonic amplitude vs frequency characteristic going thru zero at center frequency with abrupt phase reversal. This produces the parabolic output noise density and differentiates applied signals. Absence of nonlinear circuit components and product devices prevents generation of noise×noise products, avoiding the threshold phenomenon. Exponentially modulated digital signals produce output impulses due to the slope and abrupt phase reversal. The impulses have strong fundamental frequency components and may be recovered at baseband without frequency conversion.

Abstract: The trans-filter compresses in band AWGN, demodulates input signals and has no threshold due to applied noise. Two frequency selective networks with opposite amplitude vs frequency slopes are designed to remain 180 degrees out of phase over the signal band. Output amplitudes are equal at band center and are summed producing a monotonic amplitude vs frequency characteristic going thru zero at center frequency with abrupt phase reversal. This produces the parabolic output noise density and differentiates applied signals. Absence of nonlinear circuit components and product devices prevents generation of noise×noise products, avoiding the threshold phenomenon. Exponentially modulated digital signals produce output impulses due to the slope and abrupt phase reversal. The impulses have strong fundamental frequency components and may be recovered at baseband without frequency conversion. Cascading trans-filters increases noise reduction and impulse amplitude.

Abstract: A suppression method for strong interference noise of power line carrier channel is based on the processing process to carrier signals transmitted in standardized frequency interval among power line transmission regional area. According to the situation of frequency lead or lagging carrier of strong interference noise, the pending signals are respectively transmitted to a first suppression circuit (3) of which the frequency of strong interference noise signal is lower than the frequency of carrier signal, and a second suppression circuit (5) of which the frequency of strong interference noise signal is higher than the frequency of carrier signal through split-flow processing channel module to process the amplitude limiting signal, and then output signals of the first suppression circuit (3) and second suppression circuit (5) are conducted with differential mixing and output to complete the noise reduction process.

Abstract: A method for estimating and compensating for noise on antennas of a multi-antenna wireless system. The method includes receiving multiple signals via multiple receive antennas of a receiver, where each of the signals is received via a respective antenna. The method further includes estimating noise power imbalance corresponding to the receive antennas based on the multiple signals.

Abstract: A method separates a multi-component signal by first estimating parameters of the signal. Then, using periodicity-based algebraic separation and energy-based demodulation, the signal is separated into components according to the parameters and constraints. Last, a Teager-Kaiser energy detector is applied to each component to provide a direct current signal for each component, and the constraint for each component used by the separating.

Abstract: The present technique relates to a demodulation device, a demodulation method and a program capable of realizing a demodulation process at a rate equivalent to a case where I and Q channel signals are not inverted, even when the I and Q channel signals are inverted. A frequency correction unit establishes synchronization of a frequency and clock based on a signal from a frequency synchronization unit. A channel inversion detection unit of a frame synchronization unit detects presence or absence of inversion of I and Q channel signals, and supplies, as a detection result, a channel inversion detection result to the channel inversion control unit. The channel inversion control unit switches the I and Q channel signals if the inversion has occurred, based on the channel inversion detection result. This technique can be applied to a demodulation device.

Abstract: An apparatus for demodulating an input signal that includes a frequency detector for tracking a frequency of the input signal, an oscillator and a mixer is disclosed. The input signal and an output signal of the oscillator can constitute the incoming signals for the mixer and the output signal of the mixer can constitute the demodulated input signal, wherein an arithmetic unit is arranged downstream of the frequency detector and upstream of the oscillator, wherein the tracked frequency of the input signal and a predefined second frequency constitute the incoming signals of the arithmetic unit and the arithmetic unit is designed such that it computes a control signal for the oscillator from the tracked frequency of the input signal and the predefined second frequency with the output signal of the oscillator depending on the control signal.

Abstract: Provided are a receiver and a receiving method for a scalable bandwidth in a mobile station of an Orthogonal Frequency Division Multiplexing (OFDM) system. The receiving method includes the steps of: (a) filtering a received RF signal; (b) oscillating a frequency according to a center frequency control signal to output a local oscillation frequency; (c) down-converting the filtered RF signal by using the local oscillation frequency; (d) scalable-filtering the down-converted signal while adjusting a bandwidth according to a bandwidth control signal; (e) controlling gain of the scalable-filtered signal; (f) converting the gain-controlled analog signal into a digital signal by using a sampling frequency matching with a corresponding bandwidth according to an ADC control signal; and (g) demodulating the converted digital signal, outputting the center frequency control signal, the bandwidth control signal, and the ADC control signal according to control information received from an upper layer.

Abstract: A method and apparatus are disclosed for detecting a pilot signal in a wireless receiver using coherent combining/noncoherent detection techniques. Coherent combining/noncoherent detection techniques are used to detect the pilot signal whenever the receiver is already frequency locked, or otherwise known to have a small frequency offset Conventional noncoherent combining/noncoherent detection techniques are utilized to initially acquire the timing of the forward channel. Once the receiver is frequency locked, coherent combining/noncoherent detection techniques may be used to continuously detect the pilot signals. After the receiver is frequency locked, the residue frequency error is small over several consecutive correlator outputs The correlator outputs can thus be combined coherently (since the frequency error is known to be small), and the phase dependency is then eliminated by noncoherent detection.

Abstract: A receiver is provided. The receiver includes a differential amplifier amplifying differential input signals input to input terminals and outputting differential output signals through output terminals and an oscillator connected to the output terminals of the differential amplifier. The differential amplifier and the oscillator operate alternatively in response to an enable signal.

Abstract: Provided are a receiver and a receiving method for a scalable bandwidth in a mobile station of an Orthogonal Frequency Division Multiplexing (OFDM) system. The receiving method includes the steps of: (a) filtering a received RF signal; (b) oscillating a frequency according to a center frequency control signal to output a local oscillation frequency; (c) down-converting the filtered RF signal by using the local oscillation frequency; (d) scalable-filtering the down-converted signal while adjusting a bandwidth according to a bandwidth control signal; (e) controlling gain of the scalable-filtered signal; (f) converting the gain-controlled analog signal into a digital signal by using a sampling frequency matching with a corresponding bandwidth according to an ADC control signal; and (g) demodulating the converted digital signal, outputting the center frequency control signal, the bandwidth control signal, and the ADC control signal according to control information received from an upper layer.

Abstract: A receiver estimates I/Q imbalance in I and Q input signals using circuitry to separate different frequency components of the I and Q input signals, and estimation circuitry arranged to estimate I/Q imbalance at the different frequency bands. The separating of the bands may be carried out in the frequency domain, and may involve combining corresponding values representing corresponding negative and positive frequency bands, and converting the separated frequency domain representations to a time domain representation before the estimation. The estimated imbalance may be used to correct the I and Q signals at the different frequency bands.

Abstract: A system for identifying at least one phase transition in a phase-shift keying signal comprising a plurality of data samples corresponding to phase values. The system comprises a memory operable to store computing device executable instructions; and a computing device. The computing device is operable to generate a first falling edge region function for each data sample; generate a first rising edge function for each data sample; generate a first level function for each data sample; and generate a second falling edge function for each data sample. The second falling edge function equals the first falling edge function if the first falling edge function is greater than the first rising edge function and the first level function, and the second falling edge function equals zero.

Abstract: A diversity receiver includes: a plurality of demodulating means for demodulating inputted OFDM signals, to output their demodulated signals; noise component calculating means provided for each demodulating means, for calculating noise components included in the demodulated signals outputted from corresponding demodulating means; channel profile calculating means provided for each demodulating means, for calculating channel profiles based upon the demodulated signals outputted from corresponding demodulating means; transmission channel decision means for determining transmission channel based upon the channel profiles; reliability information generating means for generating reliability information indicating reliability of the demodulated signals outputted from each demodulating means, based upon the noise components and the results of the determinations by the transmission channel decision means; a weighting factor calculating means for calculating, depending on the reliability information, weighting factors

Abstract: A software defined radio detects an amplitude modulated (AM) signal contained within a received signal. This detection involves first receiving a radio frequency (RF) signal that contains the AM signal modulated about a carrier frequency (fc). The RF signal is downconverted using a first local oscillator having a frequency flo. An in-phase (I) channel signal and a quadrature (Q) channel signal are produced. From the I-channel signal, a relationship between the carrier frequency and the frequency of the local oscillator is determined with a frequency detector. The downconverted carrier signal of the I-channel signal is used to create a second set of signals with proper phases and frequencies that can be used to rotate the I-channel and Q-channel signals to account for differences between the downconverted fc and DC.

Abstract: A testing apparatus tests the performance of an electronic device having an operation circuit for providing a useful output signal. A demodulator configured to provide a phase or frequency demodulated signal related to the output of the operation circuit is packaged with the operation circuit. The gain of the demodulator is controllable from outside the package. The testing apparatus analyses the demodulated signal and controls the gain of the demodulator.

Abstract: Provided are a method and system for demodulating a signal. The method includes receiving the signal along first and second signal paths within a demodulator having a common starting point. Impedance values along each of the paths are changed alternately in synchronism.

Abstract: A method of splitting a signal (10) into two parts (10?, 10?) is disclosed together with signal processing circuitry (22) for the same. The method comprises the steps of derotating the signal (10) whereby the frequency band of the derotated signal overlaps zero frequency; and splitting the derotated signal into two parts, a first signal part (10?) consisting substantially of positive frequency signal components and a second signal part (10?) consisting substantially of negative frequency signal components. Also disclosed is methods, incorporating such a method of splitting a signal, for identifying the presence of in-band interference (11) in a signal and for despreading a spread spectrum signal.

Abstract: A demodulator for demodulating a modulated input signal transmitted at a carrier frequency includes a current mirror for receiving the modulated input signal and generating a first and a second current-mirror output signals of same amplitude and frequency as the modulated input signal. The demodulator further includes a first and a second switch-controlled sampling circuits connected to the current mirror for receiving the first and second current mirror output signals respectively. The demodulator further includes a switching signal generator provided for generating a first and a second switch control signals having a frequency substantially equals to the carrier frequency with a flexibly adjustable phase difference between the first and the second switch control signals.

Abstract: A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory.

Abstract: A FM demodulator using a single input signal has two I-Q splitters with constant group delay apparatuses. During operation, t two I-Q splitters with constant group delay apparatuses may receive the input modulated signal to generate not only one pair of modulated and respectively delay &tgr;1 and &tgr;2 in phase signals but also another pair of modulated and respective delay &tgr;1 and &tgr;2 quadrature signals. These signals are used to demodulate the final demodulated signal.

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A narrow-band digital frequency-modulation (FM) limiter-discriminator (LD) receiver with two independent detectors that combine to remove most of the bit errors caused by FM-clicks in an encoded channel. The output of the LD circuit is presented to a sample-and-hold (S&H) detector and to an integrate and dump (I&D) detector. Because the S&H and I&D detector outputs are offset in time by one-half bit and they are not entirely correlated, an error in one does not necessarily imply an error in the other. Using convolutional coding and Viterbi decoding, with threshold-compensation of the I&D detector output and threshold- or envelope-compensation of the S&H detector output, averaging the two compensated detector signals improves the receiver bit error rate (BER) performance by more than 3 dB over the soft-decision thresholded I&D detector alone, which until now was believed to be optimum in the art.

Abstract: This invention discloses a demodulation method. The method includes steps of: A) Receiving a modulated input signal having an input signal frequency. B) Generating a first switch control signal at a first switching frequency substantially equal to the input signal frequency. C) Generating a second switch control signal having the same frequency as the first switch control signal and having a phase that is approximately 90 degrees different from a phase of the first switch control signal. And D) Controlling at least two switching circuits with the first and second switch control signals for obtaining at least two sets of sampled amplitudes of the input signals for generating switching output signals for each of the switching circuits defined by subtracting the sampled amplitudes when the first switch control signal is high by the sampled amplitudes when the first switch control signal is low for each of the switching circuits to generate demodulated output signals for the modulated input signal.

Abstract: A variable delay line detector (34, 48, 66)includes a power splitter (36, 50, 68), a mixer (44, 62, 72) and a variable delay line (42,52, 70). Various devices are suitable for the variable delay line (42, 52, 70), such as a non-linear transmission line (NLTL). By providing a variable delay line, the variable delay line detector (34, 48, 66) is adapted to be programmed in real time thus making it suitable in applications where the phase and or frequency of the input signal varies. As such, the variable delay line detector (34, 48, 66) may be used in applications heretofore unknown, such &a an inexpensive demodulator in a frequency hopped spread spectrum system.

Abstract: A frequency selective noise reduction circuit and finds application in receiver demodulator arrangements in mobile telecommunication base stations. A receive signal is divided into two paths. One path includes a Phase Lock Loop circuit (PLL) which is employed to identify noise. The noise signal is inverted and then combined with the other signal.

Abstract: Demodulating FM signals using digital signal processing extracts a carrier signal from digitized channel signals, multiplies the digital channel signal with this extracted carrier signal, and further filters out the carrier signal to produce the demodulated signal. The DSP technique first down converts a group of channels to baseband which are then processed through an A/D converter to produce a digitized composite signal. A bank of bandpass filters, typically based on FFT processors, applied to the composite signal produce (a group of) digitized channel signal(s). The digitized channel signal is then demodulated by recovering a carrier signal by digitally filtering, for example, using a Hilbert bandpass filter, the channel signal and digitally filtering the product of the carrier signal and the channel signal to recover the modulating voice signals.

Abstract: In a preferred embodiment, an FM demodulator includes an I and Q sampler for generating data samples of I and Q signals of an FM signal. A signal processor derives samples of a modulating waveform of the FM signal from the I and Q data samples, using a Lagrangian interpolation function of the I and Q data samples. Variables include derivatives of the I and Q signals obtained by differentiation of the Lagrangian function. Preferably, the processor further utilizes a correction factor to correct the modulating waveform samples obtained from the Lagrangian-based interpolation, to thereby derive a modulating waveform exhibiting low signal distortion.

Abstract: A circuit configuration for intermediate frequency demodulation for a video signal processing device includes an intermediate frequency filter to which an input signal converted to an intermediate frequency is delivered, and a mixer for demodulation with a simulated video carrier. In a further branch, the video carrier is eliminated from the input signal by a bandpass and converted in an oscillator into reference signals being mutually phase offset by 90.degree.. A phase tracker ensures that the phase and frequency of the simulated video carrier are correct relative to the signal to be demodulated. The phase tracker contains in each of two branches a mixer and a low pass, through which a component separation of the video signal to be demodulated is carried out. The reference signals are weighted in further mixers with determined equisignal components and combined into the simulated video carrier.

Abstract: Method and apparatus for improving an estimate of a message being carried by a frequency modulated dominant carrier in the presence of co-channel interference from a subdominant carrier. An envelope detector provides an envelope signal E(t). A frequency demodulator provides a demodulated frequency signal F(t). In one embodiment, a comparator compares the envelope signal to a threshold voltage V.sub.T. A switch is operated when the envelope signal is less than V.sub.T. The signal F applied to the switch is held by a holding circuit while the switch is open. Interpolation and lowpass filtering improve the quality of the output signal. In another embodiment of the invention, the frequency demodulated signal F is summed with an unfiltered signal to provide a first summed signal. The first summed signal is summed with an unfiltered signal to provide a second summed signal which is an estimate of the message on a co-channel subdominant carrier.

Abstract: A demodulator receives a radio signal and causes a carrier signal reproducing circuit to reproduce the carrier signal of the received signal. One amplifier amplifies the amplitude of the reproduced carrier signal by K, and another amplifies the amplitude of the reproduced carrier signal by (K+2). An adder adds the reproduced carrier signal, amplified by K, and the received signal. A subtracter subtracts the received signal from the reproduced carrier signal amplified by (K+2). The output signal of the adder is demodulated by a first FM demodulator and the output signal of the subtracter is demodulated by a second FM demodulator. Another subtracter outputs the difference between the demodulated signals from the first and second FM demodulators as a demodulated signal of the received signal.

Abstract: A data transmission system includes a source of a data signal and a modulator, responsive to the data signal, producing a first modulated signal representing the data signal and a second modulated signal representing a signal 180 out-of-phase with the data signal. The first and second modulated signals are transported via a transmission channel. A first demodulator demodulates the transported first modulated signal and a second demodulator demodulates the transported second modulated signal. A subtractor, responsive to the first and second demodulators, produces a signal representative of the data signal.

Abstract: An apparatus and method is provided of recovering a frequency modulated signal having a first component of the frequency modulated signal at a zero-RF spectral location and a second component of the frequency modulated signal at a zero-RF spectral location in quadrature relationship to the first component. The method includes the steps of: upconverting and summing the first and second components to produce a reference signal (100), time delaying the first and second components, upconverting and summing the delayed, upconverted first and second components to produce a delayed reference signal (101) in quadrature relationship to the reference signal; limiting the reference and delayed signal (102); and exclusive or-ing (103) the limited reference and limited delayed signal.

Abstract: A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69).

Abstract: A device in which the frequency band (W) of a multiple carrier signal (MCS) is divided into a number K of sub-bands. The data contained in each sub-band are sampled at a predetermined rate (Sr) to generate a spaced sequence of samples. The data samples from all the sub-bands are time multiplexed to produce a composite signal comprising the K successive spaced sequences of samples. In this way, the composite signal transmits the data at a high apparent rate suitable for demodulation by a conventional multiple carrier demodulator designed for this high data transfer rate. This device is used in satellite communication systems.

Abstract: A demodulation apparatus incorporating an adaptive equalizer, capable of realizing a highly reliable communication, lower power consumption, and a compact size. In the demodulation apparatus, an output of one of two demodulators, at least one of which including an equalizer, is selected according to a presence or absence of multipath which is determined from a non-coincidence of bit codes, eye apertures, bit error ratea, or a matched filter output, while the operation of the other demodulator is stopped for reduction of power consumption, by stopping a supply of power or clock signals to the other demodulator. In a case using a frequency offset detection unit and a frequency offset memory, one of these is selected according to a convergence or divergence of an error signal from an equalizer, while the operation of the other one is stopped for reduction of power consumption.

Abstract: A demodulation apparatus incorporating an adaptive equalizer, capable of realizing a highly reliable communication, lower power consumption, and a compact size. In the demodulation apparatus, an output of one of two demodulators, at least one of which including an equalizer, is selected according to a presence or absence of multipath which is determined from a non-coincidence of bit codes, eye apertures, bit error rates, or a matched filter output, while the operation of the other demodulator is stopped for reduction of power consumption, by stopping a supply of power or clock signals to the other demodulator. In a case using a frequency offset detection unit and a frequency offset memory, one of these is selected according to a convergence or divergence of an error signal from an equalizer, while the operation of the other one is stopped for reduction of power consumption.

Abstract: The order statistic signal processor obtains continuing estimates of amplitude, phase, or frequency of an input signal based on order statistics. By way of definition, the P'th order statistic for a set of samples from a continuously distributed process is the P'th largest of the samples. Where a signal parameter fluctuates with time as a result of contamination by noise and interference and where the noise fluctuation rate is much greater than the rate at which changes in a signal parameter occur, an order statistic associated with a set of signal parameter samples can serve as an estimate of the signal parameter. The order statistic signal processor is based on an iterative process whereby the prior estimate of a signal parameter, i.e. amplitude or phase, is subtracted from each of a plurality of signal parameter samples obtained over a period of time. The differences are converted to quantities of fixed magnitude with signs corresponding to the differences.

Abstract: A receiver for FSK signals produces quadrature related first and second frequency down-converted difference signals (I and Q), which are amplitude limited to form respectively first and second square wave signals. The first and second square wave signals are sampled at changes in polarity of the second and first square wave signals, combined and fed to a memory, for example a hysteresis circuit, responsive to a change in polarity in the combined signal for producing a first substantially constant dc output until the next following change in polarity is detected whereupon a second substantially constant dc output is produced. By using a memory rather than a filter, reactive components are avoided making it less expensive to integrate. Also, a fixed level bit slicer can be used.

Abstract: A frequency detection system is based on a digital phase locked loop, the detection system being especially suitable for use in noisy environments like supervisory audio tone (SAT) detection in AMPS and TACS mobile telephone systems. In addition to the digital phase locked loop (4), the frequency detection system according to the invention incorporates a detector circuit (5), which comprises a detection timer (6) and two phase detectors VI1 (7) and VI2 (8). The timer (6) forms a detection sequence of desired length, at the end of which the output signal (SATVAL) of the detector circuit is updated. The first phase detector VII (7) has a phase window in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with the window. The second phase detector VI2 (8) also has a phase window of its own in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with its window.

Abstract: A digital demodulating apparatus which is high in accuracy in operation and simple in construction. The digital demodulating apparatus comprises an analog to digital converter for converting an input modulated signal having a carrier frequency of fc and a band width of 2B into a digital signal with a sampling clock signal of a sampling frequency of fs, a sampling clock generating circuit for generating a clock signal of the sampling frequency fs which is defined asfc.perspectiveto.(2m+1)/4.multidot.fsandfs>4Bm being an arbitrary integer, an orthogonal component extracting circuit for extracting, from an output digital signal of the analog to digital converter, two components which are different by (an odd number/2).multidot..pi. in phase from each other, and a demodulator of the digital signal processing type for receiving such two extracted components from the orthogonal component extracting circuit and producing a demodulated signal from the two received components.

Abstract: A demodulation apparatus incorporating an adaptive equalizer, capable of realizing a highly reliable communication, lower power consumption, and a compact size. In the demodulation apparatus, an output of one of two demodulators, at least one of which including an equalizer, is selected according to a presence or absence of multipath which is determined from a non-coincidence of bit codes, eye apertures, bit error rates, or a matched filter output, while the operation of the other demodulator is stopped for reduction of power consumption, by stopping a supply of power or clock signals to the other demodulator. In a case using a frequency offset detection unit and a frequency offset memory, one of these is selected according to a convergence or divergence of an error signal from an equalizer, while the operation of the other one is stopped for reduction of power consumption.

Abstract: Electronic receive arrangement for receiving a modulated carrier signal, which arrangement comprises a mixer/demodulator driven with the carrier frequency fc, at least one adder included in a closed signal loop, a low-pass filter, and a pulse shaper constituted by a sigma-delta (one-bit) signal converter and driven with the sampling frequency fs and also comprises a digital decimation filter. The signal loop includes the mixer/demodulator so that the modulated carrier signal is applied to the adder and the output signal of the adder is applied to the mixer/demodulator. The signal loop also comprises a second mixer driven with frequency fc, and the frequencies fs and fc present a common multiple.

Abstract: In an FM demodulator which is used in a video tape recorder and in which the linearity of input/output signals is not easily assured to increase a demodulation enable frequency, an FM signal is supplied to the base of a first transistor constituting a first differential amplifier, and a constant voltage is input to the base of a second transistor. A constant voltage is applied to the base of a third transistor constituting a second differential amplifier, and an FM signal having a phase opposite to the FM signal supplied to the first transistor is supplied to the base of a fourth transistor. A capacitor is connected between the emitters of the first and second transistors and the emitters of the third and fourth transistors. A first constant current circuit is arranged between the emitters of the first and second transistors, and a second constant current circuit having a current value twice that of the first constant current circuit is arranged between the emitters of the third and fourth transistors.

Abstract: A system for detecting the phase of a frequency of phase modulated signal that includes digital quadrature sampling of the frequency or phase modulated signal at two times that are one quarter of a cycle of a reference signal apart, determination of the arctangent of the ratio of a first sampling of the frequency or phase modulated signal to the second sampling of the frequency or phase modulated signal, and a determination of quadrant in which the phase determination is increased by 2.pi. when the quadrant changes from the first quadrant to the fourth quadrant and decreased by 2.pi. when the quadrant changes from the fourth quadrant to the first quadrant whereby the absolute phase of the frequency or phase modulated signal can be determined using an arbitrary reference convention.

Abstract: A direct conversion receiver having a tri-phase architecture including three separate baseband signal channels. RF communications signals which are being tuned by the receiver are split into three equal and in-phase components which are mixed with three equal but substantially out-of-phase injection signals on frequency with the communications signal. The resulting baseband component signals are independently filtered and amplified on the three signal channels. The baseband components are then directed to a signal processing unit which corrects the baseband components for gain or phase mismatch errors between the signal channels based on the information carried by the three components and thereafter demodulates the signals in order to acquire the information carried by the RF communications signal. An automatic gain control system and a signal filtering system adapted for use with direct conversion receivers are also disclosed.

Abstract: The outputs of two filter channels for accepting two keying frequencies are compared to produce the output. Each channel uses finite impulse response transversal filters; preferably with an impulse response of duration comparable with the symbol period of the incoming signal. Each channel has a pair of filters for accepting phase quadrature components (or, alternatively, quadrature synchronous demodulators followed by filters); the filter coefficients differ from sinusoidal by (or, in the alternative case, are formed by) a modification function which is the same for both filters of the pair.

Abstract: A direct conversion receiver for demodulating an FM signal converted frequency down converts the signal to quadrature related baseband signals (I,Q). These signals are applied by way of respective d.c. blocking capacitors (16, 18) and differentiating circuits (26, 28) to a differential arctan demodulator (20). The action of the differentiating circuits (26, 28) is to remove any d.c. component in the I and Q signals and to perform a frequency shaping which enables the demodulator (20) to recover correctly the modulating information. Measures are disclosed to overcome the effects of 180 degree phase jumps which will occur when the direction of rotation of the phasor reverses and of frequency dependent amplitude scaling introduced into the differentiated signals (I', Q').