Abstract: Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (i) a phase of one or more phases of a local oscillator signal and (ii) a corresponding data signal associated with one of the two or more data lanes, generating a composite phase-error signal representing a combination of the two or more obtained data-derived phase-error signals, receiving the composite phase-error signal at a loop filter responsively generating an oscillator control signal, and receiving the oscillator control signal at a local oscillator and responsively adjusting a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: The data processing unit (15) for a receiver of signals carrying information (1) includes a clock and data recovery circuit (16) on the basis of a data signal (DOUT), and a processor circuit (17) connected to the clock and data recovery circuit. The clock and data recovery circuit is clocked by a local clock signal (CLK) and includes a numerical phase lock loop, in which a numerically controlled oscillator (25) is arranged. This numerically controlled oscillator generates an in-phase pulse signal (IP) and a quadrature pulse signal (QP) at output. The frequency and phase of the pulse signals IP and QP are adapted on the basis of the received data signal (DOUT). The processor circuit is arranged to calculate over time the mean and variance of the numerical input signal (NCOIN) of the numerically controlled oscillator (25), so as to determine the coherence of the data signal if the calculated mean and variance are below a predefined coherence threshold.

Abstract: A method for receiving a signal having a succession of symbols, transmitted by a digital modulation, each symbol transmitted having a phase and an amplitude belonging to a set of values in finite number, the method includes evaluating a phase error (PHE) on a received symbol (S), resulting from a signal transmission noise, correcting the phase of the received symbol according to the phase error evaluated, demodulating the symbol corrected in phase, and modeling the transmission noise by a Gaussian component not correlated with the signal received and defined by a power and an interference component defined by an amplitude and which phase is substantially uniformly distributed, the phase error of the received symbol evaluated on the basis of the power of Gaussian component and the amplitude of the interference component.

Abstract: A microcontroller-based method and apparatus are described for generating one or more amplitude and frequency selectable low frequency pilot tone signals (PT) that are injected into an embedded MEMS sensor (110) and mixed signal ASIC (120) and then recovered at the microcontroller (140) to compute or measure various gyro parameters during operational use of the device with no down time or interference with normal operations.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Abstract: A method and apparatus are disclosed for detecting a pilot signal in a wireless receiver using coherent combining/noncoherent detection techniques. Coherent combining/noncoherent detection techniques are used to detect the pilot signal whenever the receiver is already frequency locked, or otherwise known to have a small frequency offset Conventional noncoherent combining/noncoherent detection techniques are utilized to initially acquire the timing of the forward channel. Once the receiver is frequency locked, coherent combining/noncoherent detection techniques may be used to continuously detect the pilot signals. After the receiver is frequency locked, the residue frequency error is small over several consecutive correlator outputs The correlator outputs can thus be combined coherently (since the frequency error is known to be small), and the phase dependency is then eliminated by noncoherent detection.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: An inertial sensor has a transducer with a sense resonator. The sense resonator is oscillated. A signal responsive to the oscillation is provided. A first baseband signal and a second baseband signal are provided responsive to the signal responsive to the oscillation of the sense resonator. A signal for controlling a resonance frequency of the sense resonator is provided responsive to performing a Goertzel algorithm on the first baseband signal and the second baseband signal. One use of controlling the resonance frequency is to control an offset between the resonance frequency of the sense resonator and the frequency of the oscillation of drive masses in the sense resonator. Using the Goertzel algorithm is particularly efficient in controlling the resonance frequency.

Abstract: Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase.

Abstract: A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal including an I component and a Q component; a numerically controlled oscillation section that generates a signal of predetermined phase; a phase error detection section that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section; a phase rotation section that rotates the phase of the symbol of the demodulation signal in accordance with the phase error; a loop filter that filters the phase error, and controls the numerically controlled oscillation section; and a gain control section that controls a gain of the loop filter based on a modulation technique of the modulation signal.

Abstract: A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

Abstract: A demodulation apparatus that demodulates an amplitude-phase-modulated signal having a level and a transition phase selected from among a plurality of levels and a plurality of phases according to transmission data, comprising a clock recovering section that receives the amplitude-phase-modulated signal and recovers a clock signal synchronized with the amplitude-phase-modulated signal; an amplitude and phase detecting section that detects, with the clock signal as a reference, the level and the transition phase of the amplitude-phase-modulated signal; a data output section that outputs data corresponding to the level and the transition phase detected by the amplitude and phase detecting section; and a phase difference correcting section that outputs a correction signal for correcting an oscillation frequency of the clock signal output by the clock recovering section, according to the transition phase detected by the amplitude and phase detecting section.

Abstract: A phase tracking system includes a source of an input signal representing a received symbol. A phase rotator has a first input terminal which is responsive to the input signal, a second input terminal which is responsive to a phase correction signal, and an output terminal which produces a phase adjusted output signal. A decision element generates an ideal signal representing the received symbol in response to the phase adjusted output signal. A phase adjuster, which has full phase wrap-around capability, generates the phase correction signal in response to the phase difference between the phase adjusted output signal and the ideal signal.

Abstract: An arrangement is described for demodulating a vestigial sideband signal component contained in an amplitude-modulated frequency signal, and preferably in a vision intermediate-frequency signal derived from a television signal.

Abstract: A demodulation apparatus that can support various oscillation frequencies. The portable phone device includes a frequency synthesizer for generating a local-oscillation signal having a local oscillation frequency for converting the frequency of an input receiving signal into an intermediate frequency based on an oscillation signal generated by an TCXO and a synchronization hold portion provided with an NCO for generating a signal having a predetermined frequency based on the oscillation signal generated by TCXO. The frequency synthesizer makes the local oscillation frequency variable by setting the dividing ratio variable in accordance with an arbitrary oscillation frequency so that the intermediate frequency remains within a predetermined range regardless of the oscillation frequency, and an NCO makes the frequency of the signal variable by setting the dividing ration variable in accordance with the oscillation frequency.

Abstract: In a timing component extractor for a digital modulated signal, a frequency converting section 30 receives a complex baseband signal having a symbol rate fs and formed from an I signal and a Q signal, and converts frequency components ±fs/2, which are present in the complex baseband signal as the data changes, to frequency components ±fs/4. The I signal and Q signal of the complex baseband signal are then nonlinearly processed. In other words, multipliers 31, 32 square the I signal and the Q signal, respectively, and an adder 33 adds the respective results of the multipliers 31, 32. A BPF 34 extracts the frequency components ±fs/2 from the output of the adder 33, and outputs the extracted frequency components ±fs/2 as a timing signal. Accordingly, processing can be conducted at a sampling frequency which is twice the symbol rate fs. Moreover, timing extraction can be stably conducted without being affected by a carrier frequency offset.

Abstract: In one aspect, the present invention includes a method for receiving an amplitude modulation (AM) signal in a receiver and performing a coordinate rotation digital computer (CORDIC) operation in obtaining a demodulated AM signal. The demodulated AM signal may be obtained from a magnitude output of the CORDIC operation or as a real output of a multiplication between a complex baseband signal and a demodulating carrier signal generated in a feedback loop.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Abstract: To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics.

Abstract: An AM detecting apparatus includes a voltage comparator And an AND circuit. The voltage comparator compares a detection signal a low-pass filter outputs with a no-signal potential. The AND circuit outputs, when the amplitude of an AM signal is higher than the reference value, one of a first control signal and second control signal in response to a comparison result of the voltage comparator 5, and outputs, when the amplitude of the AM signal is lower than the reference value, the first control signal. The phase of the VCO signal is controlled such that the phase difference between the AM signal and VCO signal agrees with the control signal the AND circuit outputs. The AM detecting apparatus can carry out the coherent detection of the desired signal in the AM signal even during overmodulation.

Abstract: A first automatic phase control (APC) detection circuit generates an APC detection signal having normal polarity from an amplitude modulation signal and APC detection reference signal. A second APC detection circuit generates an APC detection signal having reverse polarity from the amplitude modulation signal and the APC detection reference signal. A switch selects the APC detection signal having normal polarity in case of normal modulation and selects the APC detection signal having reverse polarity in case of overmodulation.

Abstract: An AM detecting apparatus includes a voltage comparator And an AND circuit. The voltage comparator compares a detection signal a low-pass filter outputs with a no-signal potential. The AND circuit outputs, when the amplitude of an AM signal is higher than the reference value, one of a first control signal and second control signal in response to a comparison result of the voltage comparator 5, and outputs, when the amplitude of the AM signal is lower than the reference value, the first control signal. The phase of the VCO signal is controlled such that the phase difference between the AM signal and VCO signal agrees with the control signal the AND circuit outputs. The AM detecting apparatus can carry out the coherent detection of the desired signal in the AM signal even during overmodulation.

Abstract: A method of receiving a signal and performing a carrier recovery, the method comprising the steps of: (a) receiving a signal Xk. (b) rotating Xk by a previous correction angle &thgr;k−1 to generate a rotated signal Qk, wherein the rotation is based upon a sine and cosine of the previous correction angle. (c) mapping the rotated signal Qk to a valid decision Ak out of a constellation. (d) generating a normalized error signal &Dgr;&thgr;k,k−1 that reflects an angular difference between a correction angle &thgr;k and the previous correction angle &thgr;k−1. (e) calculating and storing a sine and a cosine of the correction angle &thgr;k, wherein the calculation is based upon &Dgr;&thgr;k,k−1, the sine of the previous correction angle &thgr;k−1 and the cosine of the previous correction angle.

Abstract: A reproduced signal is adaptively equalized in an adaptive equalizer after going through an AD converter. The AD converter, the adaptive equalizer, a phase error detector, a phase shifter, a DA converter, a loop filter, and a variable frequency oscillation circuit, all of which structure a PLL circuit, and a clock signal phase-locked to reproduced data is fed back to the AD converter. The phase shifter slightly shifts, as appropriate, a phase error detected in the phase detector according to the change in a barycenter of tap coefficients detected in a tap barycenter detection circuit. With such structure, signals can be processed in an accurate manner without causing competition in operation between the PLL and adaptive equalization.

Abstract: An AFC (Automatic Frequency Control) device and a method of controlling reception frequency in a dual-mode terminal. When a dual-mode terminal uses one or two AFC devices, the time required for acquiring tracking synchronization in a PLL circuit for a first frequency can be reduced using a test augmentation frequency which is an integer multiple of a tracking synchronization acquiring residual frequency of a PLL circuit for a second frequency to which the first frequency transitions for reliable synchronization acquisition. Errors with respect to an output dynamic range caused by use of two AFCs are reduced and thus the demodulation performance of a receiver is ensured by varying quantization bits of an A/D clock based on the dynamic range of residual errors in a frequency area. The demodulation performance can also be ensured by operating an ACPE circuit for an AFC device having many residual frequency errors.

Abstract: In a circuit arrangement for demodulating an intermediate-frequency video signal generated while using a Nyquist edge, having a phase-locked loop (1) including a phase detector (3), a loop filter (4) and a voltage-controlled oscillator (5), and a video demodulator (2), the intermediate-frequency video signal being applied to the phase detector (3) and the output signal of the phase-locked loop (1) being applied to the video demodulator (2), which converts the intermediate-frequency video signal into a baseband video signal, phase fluctuations contained in the carrier of the intermediate-frequency video signal due to its generation while using a Nyquist edge are compensated in that the phase comparator (3) operates, by approximation, independently of modulation in the control range of the intermediate-frequency video signal, in that the baseband video signal is present in an inverted form with respect to the intermediate-frequency video signal, and in that a correction signal is derived from the baseband video

Abstract: An adaptable, variable rate symbol timing recovery system for a digital sal receiver comprises an analog to digital (A-D) signal converter having analog signal input and digital data signal output terminals. A source of selectable, substantially fixed rate, data sampling clock signals is coupled to the A-D signal converter for sampling a signal received at the input at a predetermined, substantially fixed clock rate, depending on data rate and modulation of the received signal. A digital signal processing loop is coupled to the digital data signal output terminal for adjustably producing interdependent signals in synchronism with the data signals at the output terminal which are asynchronous with respect to the fixed rate clock signals. A Controller is provided for selectively configuring the data sampling clock signal source and the digital signal processing loop according to the data rate and modulation characteristics of the received signal.

Abstract: Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal and a second beat note signal are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop is configured to receive the first and second beat note signals for generating a first state signal. The first flip-flop generates the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal. The second flip-flop is configured to receive the first and second beat note signals for generating a second state signal. The second flip-flop generates the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal.

Abstract: A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCP)(20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency (.omega.'.sub.r).

Abstract: Receiver having an RF input for applying an RF input carrier-modulated modulation signal thereto, which receiver is coupled to a multiplier circuit and to a phase-locked loop (PLL) with a signal path incorporating a phase detector, a loop filter, a first dc decoupling circuit and a controlled oscillator having an in-phase and a quadrature output via which local in-phase and quadrature carriers are applied to the multiplier circuit and the phase detector, respectively, and a signal generator for generating a local auxiliary pilot and a pilot detector for detecting the local auxiliary pilot, an output of which is coupled to the controlled oscillator via a low-pass filter.

Abstract: A highly efficient linear amplifier and/or modulator and demodulator comprising first and second feedback loops is provided. Each loop processes a component of the input signal and the component signals are recombined at, for example, a summing junction 18. The feedback signals for each loop are dependent upon the output signal and are in phase quadrature. The input signal is separated into I and Q signals, which are also in phase quadrature, by a component separator 10.

Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock indicator circuit determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming signal (or alternatively, of the outgoing signal) as determined in order to supply an output signal of predetermined polarity. The frequency lock indicator consists of a zero crossings detector and a latch that is sampled for a time period. The zero crossings detector is a delay and an exclusive OR gate. An optional confidence counter may be used with the latch to determine when frequency lock has occurred to provide the lock indicator signal.

Abstract: A polarity detection circuit for an FPLL demodulated signal including a small DC pilot recovers the DC pilot by determining the DC levels of the demodulated output signals both with and without the DC pilot. A zero carrier condition is created for determining the DC level of the output signal without the DC pilot. The two DC levels are subtracted and limited and the polarity of the recovered DC pilot is used to control the operation of a polarity inverter to assure that the output signal has a desired polarity.

Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock circuit also determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming, or alternatively, of the outgoing signal, as determined in order to supply an output signal of predetermined polarity.

Abstract: A bi-phase stable FPLL is locked by a DC pilot component in a recovered data signal. The signal is formatted in repetitive data segments including sync characters and a DC pilot. A sign bit, indicative of the polarity of the recovered data, is developed from the sync characters and is used to augment the DC pilot to stabilize the lock up of the FPLL to produce the desired polarity of recovered data.

Abstract: A high frequency television signal receiving apparatus providing excellent linear detection of output characteristics by improving the phase characteristic of the picture synchronous detector. A variable capacitive element is equivalently connected in parallel to a reference solid-state oscillation element. The reference solid-state oscillation element controls the frequency of a local oscillation device including a PLL circuit for feeding a local oscillation signal to a mixer for converting a high frequency signal into an intermediate frequency signal. A first low pass filter is connected between a phase comparator for detecting a phase difference of the intermediate frequency signal and the output of a detection oscillator for generating a detection oscillation signal with a specific phase difference. A second low pass filter having a larger time constant than the first low pass filter is connected to the variable capacitive element.

Abstract: A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.

Abstract: A printed circuit board includes an oscillator and a modulator. The oscillator includes a first printed inductor and a capacitive diode which are printed on one side of the printed circuit board. The modulator includes a second printed inductor coupled to the first printed inductor and printed on the same side of the printed circuit board as the oscillator. A conductive surface at a reference potential is arranged the other side of the printed circuit board and in the vicinity of the oscillator and the modulator and electrically coupled to the oscillator and the modulator using conductive through holes.

Abstract: A demodulator receives a radio signal and causes a carrier signal reproducing circuit to reproduce the carrier signal of the received signal. One amplifier amplifies the amplitude of the reproduced carrier signal by K, and another amplifies the amplitude of the reproduced carrier signal by (K+2). An adder adds the reproduced carrier signal, amplified by K, and the received signal. A subtracter subtracts the received signal from the reproduced carrier signal amplified by (K+2). The output signal of the adder is demodulated by a first FM demodulator and the output signal of the subtracter is demodulated by a second FM demodulator. Another subtracter outputs the difference between the demodulated signals from the first and second FM demodulators as a demodulated signal of the received signal.

Abstract: A phase adjusting circuit for a demodulator is provided. The circuit comprises an A/D converter for sampling an input analog signal at an interval shorter than the Nyquist interval and converting the sampled analog signal to a digital signal, a digital filter for narrowing the frequency band of the digital signal to output a filtered digital signal, a digital sampling/holding circuit for decimating sampling components of the filtered digital signal to output a decimated digital signal, and a phase locked loop circuit for detecting a phase error of the decimated digital signal and controlling the number of sampling intervals to be skipped by the digital sampling/holding circuit.

Abstract: An oscillator capable of setting a desired frequency by using only two resonators without setting up any additional adjustment processes, and a synthesizer tuner circuit with an AM synchronous detect circuit.

Abstract: A digital phase shifter for phase-shifting a cyclic input signal includes first--third dividers 1, 4 and 8, first and second phase detectors 2 and 6, first and second voltage controlled oscillators (VCOs) 3 and 7, and a digital comparator 5. The input signal F(IN) and a clock signal F(VCO3) output from the first VCO3 are divided by N and M at the first and second dividers, respectively and phases of the divided signals are compared at the first phase detector 2, whereby the leading edges of the input and clock signals are synchronized. The second divider 4 also generates a count value (m) representing a cycle order number to the comparator, where it is compared with a preset value (.phi.) for determining the amount of phase shift, and an equate pulse EQ5 is generated when the compared values are the same.

Abstract: To demodulate an analog signal having information modulated by a carrier, the analog signal is chopped by a chopper, the chopped signal is digitized by a sigma-delta analog-to-digital converter to produce a series of digital samples at a sampling frequency, the digital samples are filtered in a digital decimating filter to produce data words, and the data words are modulated by an intermediate frequency signal to produce a detected information signal. The various frequency signals are generated by a phase-lock loop so that the intermediate frequency is the difference between the carrier frequency and the chopping frequency, and both the chopping frequency and the intermediate frequency are sub-multiples of the sampling frequency.

Abstract: A demodulator circuit and a demodulating method are disclosed. A demodulator including a phase-locked loop for a receive carrier recovery or a phase lock recovery demodulates an input received signal and a band of a loop filter of the phase-locked loop is controlled by a control signal. A bit error rate monitor detects a bit error rate of a demodulated outputs the control signal on the basis of the bit error rate result of the demodulator, and a loop filter band controller output from the bit error rate monitor. Hence, the bit error rate of the demodulated signal is detected and the loop filter band of the phase-locked loop of the demodulator is controlled based on the detected bit error rate. As a result, an exact control of the loop filter band of the demodulator can be performed on the basis of the received signal state without using any received signal power detector, any C/N detector or the like.

Abstract: A synchronous AM detector and processor requiring a reduced number of external components and fewer integrated circuit pins comprises an audio processor having a first filter operation controlled by a control voltage and an AM stereo decoder including a lock detector and a phase locked loop having a second filter operation controlled by the control voltage. A single control node is coupled to the audio processor and the phase locked loop, the control node providing the control voltage for the audio processor and the phase locked loop. The voltage at the control node is biased normally high, capable of being pulled low by the audio processing circuit and capable of being pulled low by the lock detector. An RC circuit decays the rise time of the control voltage at the control node after the control voltage has been pulled low. Circuitry is added to control the first filter operation of the audio processing circuitry responsive to the control voltage at the control node.