Abstract: Examples described herein may include medical devices and electrosurgical generators with resonant isolated transformers to perform filtering and gain functions. An example electrosurgical generator includes a radio frequency (RF) inverter stage configured to receive an input signal and, in response to control feedback signals, to provide an output signal that provides power to a load. The RF inverter stage includes a resonant isolated transformer configured to receive the input signal and to provide gain and filtering adjustments to the input signal to provide the output signal.

Abstract: A radiation pattern of a phased array antenna, comprising a plurality of antenna elements, may be dynamically modified using phase shifters to apply variable phase shifts between antenna elements. In a phased array antenna designed for airborne applications, the phase shifters may be required to enable a fine phase-shifting resolution and to operate over a wide temperature range. The phase shifters may also be required to perform while exhibiting small process variations, small form factor, low power consumption, and low loss. One possible solution to this is a passive vector-interpolating phase shifter configured to exhibit such characteristics.

Abstract: A transmitting apparatus, a receiving apparatus corresponding to the transmitting apparatus, and a transmitting-receiving system including: a first A/D converting part that converts an analog audio signal into a digital signal; a compressing part that compresses the converted digital signal; a modulating part that generates a modulated signal by modulating the compressed digital signal; an all-pass filter that reduces a phase distortion included in the modulated signal; and a transmitting part that transmits a phase-distortion-cancelled signal resulting from reducing the phase distortion of the modulated signal with the all-pass filter are provided.

Abstract: A power amplifier and power amplification circuit are described herein. An illustrative power amplifier is disclosed to include an input terminal, a drive amplifier connected to the input terminal, and an impedance modulator having a capacitance that is adjusted inversely and proportionately relative to a signal output by the drive amplifier, wherein the impedance modulator provides a feedback loop between an output of the drive amplifier and the input terminal.

Abstract: A power amplifier system which operates at a narrow band with high power and high efficiency or at a wide band is provided. Said power amplifier system comprises at least one high power amplifier; at least one connection line; at least one input block which receives at least one signal from an input, which is connected to said high power amplifier and connection line, which sends received signal to either high power amplifier or connection line and which amplifies the power of the signal sent to the connection line; and at least one high power asymmetric output switch, which is connected to said high power amplifier and connection line and which sends signals coming from said high power amplifier and connection line to an output.

Abstract: Envelope tracking schemes for Doherty power amplifiers are provided herein. In certain embodiments, a mobile device includes a Doherty power amplifier that amplifies an RF signal for transmission on an antenna, and an envelope tracker that controls a supply voltage of the Doherty power amplifier based on an envelope of the RF signal amplified by the Doherty power amplifier. Thus, supply modulation is used to control the supply voltage of the Doherty power amplifier to achieve gains in linearity, efficiency, and/or other performance metrics. Furthermore, the Doherty power amplifiers herein can provide higher overall transmission efficiency and/or lower DC power consumption, which in turn leads to lower operating temperatures and/or improved reliability.

Abstract: Provided are a vector quantization device, a voice coding device, a vector quantization method, and a voice coding method which enable a reduction in the calculation amount of voice codec without deterioration of voice quality. In the vector quantization device, a first reference vector calculation unit (201) calculates a first reference vector by multiplying a target vector (x) by an auditory weighting LPC synthesis filter (H), and a second reference vector calculation unit (202) calculates a second reference vector by multiplying an element of the first reference vector by a filter having a high pass characteristic. A polarity preliminary selection unit (205) generates a polar vector by disposing a unit pulse having a positive or negative polarity, which is selected on the basis of the polarity of an element of the second reference vector, in the position of said element.

Abstract: Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.

Abstract: A Doherty amplifier system is disclosed. The Doherty amplifier system includes a carrier amplifier having a main input for receiving a first portion of a radio frequency (RF) signal and a main output in communication with a RF signal output. A peaking amplifier has a peak input for receiving a second portion of the RF signal and a peak output in communication with the RF signal output. Further included is a first impedance inverter coupled between the main output and the peak output. A second impedance inverter is coupled between the peak output and the RF signal output. A first impedance inverter coefficient of the first impedance inverter is numerically within ±10% of a second impedance inverter coefficient of the second impedance inverter.

Abstract: The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

Abstract: A Doherty amplifier system is disclosed. A main amplifier is configured to receive a first portion of a radio frequency (RF) signal at a main input and provide an amplified copy of the first portion of the RF signal at a main output. A peaking amplifier is configured to be controllably activated to receive a second portion of the RF signal at a peak input and provide an amplified copy of the second portion of the RF signal at a peak output. A saturation detector has a detector input coupled to the main output of the main amplifier and a first detector control output, wherein the saturation detector is configured to detect saturation of the main amplifier and activate the peaking amplifier as saturation of the main amplifier is detected and deactivate the peaking amplifier when saturation of the main amplifier is not detected by the saturation detector.

Abstract: A power amplifier module includes a first phase shifter, a second phase shifter, and an electromagnetic shield. The first phase shifter includes a first transmission line assembly to shift a first amplified signal by a first phase angle. The second phase shifter includes a second transmission line assembly to shift a second amplified signal by a second phase angle. The electromagnetic shield is arranged to shield the first transmission line assembly from the second transmission line assembly. The power amplifier module may have, for example, Doherty amplifier configuration.

Abstract: The present disclosure relates to a current detecting apparatus using an operational amplifier and a method thereof. In accordance with an aspect of the present disclosure, there is provided a current detecting apparatus of a conductor including: a shunt resistor connected to the conductor; an operational amplifier connected to the shunt resistor; a first resistor connected between the shunt resistor and a first input terminal of the operational amplifier; a second resistor connected between the shunt resistor and a second input terminal of the operational amplifier; a third resistor connected between a ground and the first input terminal of the operational amplifier; and a fourth resistor connected between the ground and the second input terminal of the operational amplifier.

Abstract: A system may comprise a scanner assembly and a radiometer. The radiometer may comprise a W-Band and F-Band receiver and an intermediate frequency processor. The system may be rotatably mounted to a bus via the scanner assembly.

Abstract: A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor.

Abstract: A system for thermally protecting an amplifier driving a capacitive load may include a low-pass filter configured to filter, with a variable cutoff frequency, an input signal to generate a filtered input signal, wherein the amplifier is configured to receive the filtered input signal and amplify the filtered input signal to generate a driving signal to the capacitive load and a controller configured to receive a real-time estimate of a temperature associated with the amplifier and vary the variable cutoff frequency as a function of the temperature.

Abstract: Systems, methods, circuits and computer-readable mediums for regulators, e.g., low-dropout (LDO) regulators, with load-insensitive compensations are provided. An example regulator includes an amplifier operable to receive an input voltage and a feedback voltage, a follower responsive to an output voltage of the amplifier and operable to supply a regulated voltage to a load coupled to the follower, and a feedback circuit coupled to the load and the amplifier and operable to provide the feedback voltage. The amplifier is operable to have a substantially unity gain beyond a resonant frequency of the amplifier.

Abstract: Various embodiments disclosed herein provide for a low complexity transmitter structure for active antenna arrays by reducing the number of digital predistortion extraction loops that need to be performed. Digital predistortion (DPD) corrects any non-linearities in a power amplifier. By determining which power amplifiers have similar characteristics in an array, and thus may use similar predistortion coefficients, once the DPD coefficients are determine for one of the grouped power amplifiers, DPD can be performed on each of the grouped power amplifiers based on the DPD coefficients.

Abstract: A signal processing system may include a modulation stage configured to generate a modulated input signal, an open-loop switched mode driver coupled to the modulation stage and configured to generate an output signal from the modulated input signal, a voltage regulator configured to generate a supply voltage that supplies electrical energy to the open-loop switched mode driver, and a control subsystem configured to, when a magnitude of the modulated input signal falls below a threshold magnitude, control the voltage regulator to control the supply voltage such that the output signal varies non-linearly with the modulated input signal for magnitudes of the modulated input signal below the threshold magnitude.

Abstract: Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.

Abstract: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.

Abstract: A circuit system including an operational amplification circuit is disclosed. The operational amplification circuit includes N stages of operational amplification units that are cascaded, an input terminal of the 1st stage of operational amplification unit is an input terminal of the operational amplification circuit, and an output terminal of the Nth stage of operational amplification unit is an output terminal of the operational amplification circuit; an output terminal of the ith stage of operational amplification unit is connected to an input terminal of the (i+1)th stage of operational amplification unit, so as to provide an input signal for the (i+1)th stage of operational amplification unit; and there is a feedback channel from the output terminal of the Nth stage of operational amplification unit to an input terminal of each of the 1st stage of operational amplification unit to the Nth stage of operational amplification unit.

Abstract: A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

Abstract: An operational amplifier includes: a first gain stage for generating a second signal based on a first signal transmitted from a prior stage circuit; a second gain stage for generating an output signal based on the second signal; multiple candidate capacitors; and a capacitor selection circuit for switching the coupling relationship of the multiple candidate capacitors based on the magnitude of an input signal of the prior stage circuit, so that only a portion of the multiple candidate capacitors could be coupled to the second gain stage at a time.

Abstract: A traveling wave amplifier includes two input-side lines, two output-side lines, and amplification cells. The amplification cells each include a first input terminal, a second input terminal, a first transistor including a base connected to the first input terminal and a collector connected to one output-side line, a second transistor including a base connected to the second input terminal and a collector connected to the other output-side line, a current source connected to an emitter of each of the two transistors, a first series circuit connected between the collector of the second transistor and the base of the first transistor and including a capacitor and a resistor, and a second series of circuit connected between the collector of the first transistor and the base of the second transistor and including a capacitor and a resistor.

Abstract: A method for temperature mitigation includes receiving a signal from a temperature sensor that is disposed within a computing device. A processor chip within the computing device produces heat. The signal from the temperature sensor is converted to temperature data. The method further includes processing the temperature data to generate an estimate of a temperature of an external surface of the device. The processing includes applying a low pass filter to the temperature data, applying an amplitude attenuation to the temperature data, and applying a delay to the temperature data. The method further includes reducing an operating parameter of the processor chip, such as operating frequency, in response to the estimated temperature of the external surface of the device.

Abstract: An apparatus includes a demapper to compute a reliability metric associated with a number of bit streams received by multiple radio-frequency (RF) antennas. The apparatus further includes a channel decoder in a feedback loop with the demapper to process the reliability metric and to provide a feedback signal to the demapper. The demapper is an iterative demapper and can use a symbol subset of at least a first stream of the plurality of bit streams and the feedback signal to compute the reliability metric for a second stream of the plurality of bit streams.

Abstract: A system for performing an ocular surgical procedure is provided. The system includes a multiple frequency signal source, a configurable tuned output filter connected to the multiple frequency signal source, and a multiple frequency ultrasonic handpiece. The multiple frequency signal source operates at a first frequency and is configured to drive the configurable filter and the multiple frequency ultrasonic handpiece at the first frequency. The multiple frequency signal source operates at a second frequency and is configured to drive the configurable filter and the multiple frequency ultrasonic handpiece at the second frequency, and the design addresses third harmonic frequency issues for the multiple frequency ultrasonic handpiece. Switchable passive components, such as inductors, resistors, and/or capacitors may be employed in the configurable tuned output circuit, or alternately multiple similar circuits may be employed. Alternately, a multi-tap transformer may be provided.

Abstract: Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

Abstract: This invention discloses an active load generation circuit and a filter. The active load generation circuit includes a transistor, a voltage control circuit, a voltage offset and tracking circuit, and a temperature sensing circuit. The transistor provides an impedance and includes a control terminal and an input terminal. The control terminal receives a control voltage, the input terminal receives an input signal, and the impedance is associated with the control voltage. The voltage control circuit generates an intermediate voltage according to a power supply voltage and a first reference voltage. The voltage offset and tracking circuit generates the control voltage according to the input signal and the intermediate voltage such that the control voltage varies with the input signal. The temperature sensing circuit senses an ambient temperature of the active load generation circuit and adjusts the first reference voltage according to the ambient temperature.

Abstract: An amplifier circuit that includes a first amplifier that has a first input that receives an input signal, a second input and an output. The amplifier circuit also includes a second amplifier that has a first input that is coupled to the output of said the amplifier and a second input. The circuit further includes a first impedance network Z1, a second impedance network Z2, a third impedance network Z3 and a fourth impedance network Z4. The first impedance network Z1 is coupled to a load and the second input of the second amplifier, the second impedance Z2 is connected the output of the first amplifier and the second input of the first amplifier, the third impedance Z3 is connected to the output of the first amplifier and the load, the fourth impedance Z4 is connected the output of the second amplifier and the second input of said first amplifier.

Abstract: This disclosure provides systems, methods and apparatus for increasing the efficiency of an amplifier when driven by a variable load. In one aspect a transmitter device is provided. The transmitter device includes a driver circuit characterized by an efficiency. The driver circuit is electrically connected to a transmit circuit characterized by an impedance. The transmitter device further includes a filter circuit electrically connected to the driver circuit and configured to modify the impedance to maintain the efficiency of the driver circuit at a level that is within 20% of a maximum efficiency of the driver circuit. The impedance is characterized by a complex impedance value that is within a range defined by a real first impedance value and a second real impedance value. A ratio of the first real impedance value to the second real impedance value is at least two to one.

Abstract: A differential elliptic filter circuit includes: a differential amplifier, feedback and feedforward paths. An upper pair and a lower pair of inverting feedback paths couple a corresponding one the differential signal outputs of the amplifier to an inverting one of a pair of inputs of the amplifier, to provide two complex conjugate poles, and establish upper and lower virtual grounds at the amplifier inputs. Upper and lower inverting feedforward paths couple corresponding passive nodes of the upper and lower pairs of inverting feedback paths to respectively the lower and upper virtual grounds to provide two zeros of the circuit. The upper and lower non-inverting feedforward paths couple an upper and lower one of a pair of differential signal inputs of the circuit to respectively the upper and lower virtual grounds to enable positioning of the two zeros of the circuit on an imaginary axis of a pole-zero plot.

Abstract: An analog predistortion linearizer system with dynamic frequency compensation for automatically adjusting predistortion characteristics based on a detected frequency includes a frequency detector configured to generate at least one frequency detection signal in response to receiving an amplifier drive signal, the frequency detection signal including a frequency indicator that indicates the frequency of the amplifier drive signal. Moreover, the system also includes a controller communicatively coupled to the frequency detector and configured to generate a predistorter control signal in response to receiving the frequency detection signal from the frequency detector, and a predistorter communicatively coupled to i) the frequency detector and ii) the controller, the predistorter configured to generate a predistorted amplifier drive signal based on at least the predistorter control signal.

Abstract: A vertical combiner for an overlapping linear phased array is provided. The vertical vector combiner enables two strip-line signals from different layers to be combined, or divided, by vertical transitions between substrate layers and produce a desired output signal phase. The combiner can terminate in a short to act as an antenna. In an antenna application, the antenna provides multiple substrate layers for each strip-line signal, each having a metal ground plane. The ground planes are be coupled by vertical transitions access enabling a stepped ground within the structure which increases bandwidth. The multi-layer combiner architecture enables integration with phased array feed networks for millimeter wave phased array antennas.

Abstract: The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.

Abstract: A sensor arrangement (10) comprises an amplifier (11) having a signal input (12) to receive an input signal (SIN) and a signal output (13) to provide an amplified sensor signal (SOUT) that is an inverted signal with respect to the input signal (SIN). Furthermore, the sensor arrangement (10) comprises a feedback path connecting the signal output (13) to the signal input (12), wherein the feedback path comprises a series connection of a capacitive sensor (14) and a feedback capacitor (15). A voltage source arrangement (19) of the sensor arrangement (10) is connected to a feedback node (18) between the capacitive sensor (14) and the feedback capacitor (15).

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high bandwidth path is substantially reduced by combining the output of the high bandwidth path with the output of the low bandwidth path to generate a high bandwidth, low offset output. The offset can be further reduced by including transimpedance amplifiers in the high bandwidth sensors to optimize the frequency response of high bandwidth Hall sensor.

Abstract: An I-V converting module includes: a current output sensor, an I-V transforming circuit, a sampling and holding circuit, a source follower, a loop switch, and a bypass circuit. A drain of the source follower is connected to an input/output end of the sampling and holding circuit. A source of the source follower is connected to an input end of the I-V transforming circuit and an output end of the current output sensor, and a gate of the source follower is connected to an output end of the I-V transforming circuit via the loop switch, and to the bypass circuit. When the loop switch is closed and the bypass circuit is disabled, a feedback loop formed by the source follower, the I-V transforming circuit and the loop switch is conducted, and the I-V converting module enters into a sampling setup stage.

Abstract: A front-end amplifier circuit for receiving a biological signal includes a signal channel. The signal channel amplifies the biological signal to generate a detection current and includes a capacitive-coupled transconductance amplifier. The capacitive-coupled transconductance amplifier amplifies the biological signal with a transconductance gain to generate a first current.

Abstract: Embodiments of an apparatus are disclosed. In an embodiment, a power receiver unit is disclosed. The power receiver unit includes a power pick-up unit, a communication modulator, and a filter. The power pick-up unit receives a wireless power signal. The communication modulator applies a modulation to the received wireless power signal. The filter suppresses a load signal from a load of the wireless charge receiver to prevent interference with the modulation.

Abstract: A direct conversion wireless transmitter includes IQ mismatch pre-compensation using direct learning adaptation to adjust IQ pre-compensation filtering. Widely-linear IQ_mismatch pre-compensation filtering compensates for IQ mismatch in the TX analog chain, filtering of input data x(n) to provide pre-compensated data y(n) with a compensation image designed to interfere destructively with the IQ_mismatch image. A feedback receiver FBRX captures feedback data z(n) used for direct learning adaptation. DL adaptation adjusts IQ_mismatch filters, modeled as an x(n)_direct and complex conjugate x(n)_image transfer functions w1 and w2, including generating an adaptation error signal based on a difference between TX/FBRX-path delayed versions of x(n) and z(n), and can include estimation and compensation for TX/FBRX phase errors. DL adaptation adjusts the IQ pre-comp filters w1/w2 to minimize the adaptation error signal. Similar modeling can be used for IQ mismatch.

Abstract: Embodiments of a Doherty amplifier device are provided, including a first amplifier stage having a first gain; a second amplifier stage having a second gain that is less than the first gain; and an input power splitter coupled to inputs of the first and second amplifier stages, wherein the input power splitter includes either an inductive element, a capacitive element, or both coupled between the inputs of the first and second amplifier stages, and a resistive element coupled to the input of the second amplifier stage, the input power splitter respectively delivers first and second power levels to inputs of the first and second amplifier stages, and the resistive element is configured to tune gain linearity of the Doherty amplifier device by increasing the second power level to be greater than the first power level, based on a ratio of the second gain to the first gain.

Abstract: A high bandwidth Hall sensor includes, for example, a Hall element for generating a first polarity Hall-signal output current. An amplifier receives, at a first input, the first polarity Hall-signal output current and outputs a feedback current of a second polarity opposite the first polarity in response. The feedback current is coupled to the first input, and the feedback current suppresses an instantaneous voltage generated by the first polarity first Hall element output current at the first input. In an embodiment, the feedback current suppresses the instantaneous voltage generated by first polarity Hall element output current such that the effects of the Hall element source impedance are reduced.

Abstract: The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a differential amplifier in cascode configuration. An input transistor is coupled to an output transistor via a peaking inductor. The output transistor is also directly coupled to a degeneration resistor. There are other embodiments as well.

Abstract: Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.

Abstract: Circuits for low noise amplifiers with interferer reflecting loops are provided. In some embodiments, circuits for a low noise amplifier with an interferer reflecting loop are provided, the circuits comprising: a low noise amplifier (LNA) having an input and an output; a buffer having an input coupled to the output of the LNA and an output; and notch filter having an input coupled to the output of the buffer and an output coupled to the input of the LNA.