Having D.c. Feedback Bias Control For Stabilization Patents (Class 330/270)
  • Patent number: 9035699
    Abstract: Exemplary embodiments are directed to operating a multi-stage amplifier with low-voltage supply voltages. A multi-stage amplifier may include a first path of an amplifier output stage configured to convey an output signal if a first supply voltage is greater than a threshold voltage. The multi-stage amplifier may also include a second path of the amplifier output stage configured to convey the output signal if the first supply voltage is less than or equal to the threshold voltage.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 19, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Vijayakumar Dhanasekaran
  • Patent number: 9028479
    Abstract: A radio-frequency (RF) amplifier having a direct response to an arbitrary signal source to output one or more electrosurgical waveforms within an energy activation request, is disclosed. The RF amplifier includes a phase compensator coupled to an RF arbitrary source, the phase compensator configured to generate a reference signal as a function of an arbitrary RF signal from the RF arbitrary source and a phase control signal; at least one error correction amplifier coupled to the phase compensator, the at least one error correction amplifier configured to output a control signal at least as a function of the reference signal; and at least one power component coupled to the at least one error correction amplifier and to a high voltage power source configured to supply high voltage direct current thereto, the at least one power component configured to operate in response to the control signal to generate at least one component of the at least one electrosurgical waveform.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Covidien LP
    Inventor: James H. Orszulak
  • Patent number: 8903687
    Abstract: A method for compensating for a dielectric absorption effect in a measurement configuration during measurements by an instrument having measurement terminals includes providing a feedback loop in the instrument, the loop having a gain adjustment and a simulation impedance and being adapted to provide a signal counter to the dielectric absorption at the measurement terminals; applying a transient calibration signal to the test terminals for at least two values of the gain adjustment; measuring a response to the calibration signal for each of the at least two values; and determining an operating value of the gain adjustment based on the measured responses. The operating value is used for subsequent measurements by the instrument, the simulation impedance modeling the dielectric absorption characteristics of the measurement configuration.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: December 2, 2014
    Assignee: Keithley Instruments, Inc.
    Inventors: John G. Banaska, Gregory Roberts
  • Patent number: 8390742
    Abstract: In a semiconductor integrated circuit arranged to perform sag compensation for a video signal, an operational amplifier includes a non-inverted input terminal, an inverted input terminal, and an output terminal, in which a video signal is input to the non-inverted input terminal. A first resistor includes a first end connected to the inverted input terminal and a second end being grounded. The output terminal is connected to a first external terminal and the inverted input terminal is connected to a second external terminal. A second resistor includes a first end connected to the output terminal and a second end connected to the inverted input terminal. A first capacitor is disposed between the first external terminal and the second external terminal and connected in parallel to the second resistor, and the second resistor has a resistance value determined based on a capacitance value of the first capacitor.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: March 5, 2013
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Shuhei Abe, Nagayoshi Dobashi, Yoshiaki Hirano
  • Patent number: 8195096
    Abstract: The instant invention relates to an apparatus and method for enhancing DC offset correction speed of a radio device. On the exemplary, the apparatus includes one or two-stage signal-processing units and a controller. Each signal-processing unit has a baseband filter, a gain stage and a DC offset correction (DCOC) loop applied on the gain stage. A connection direction of an electrode terminal of a capacitor of the baseband filter is capable of being switched by the controller to process a pre-charge or a discharge phases thereby adjusting a bandwidth of the baseband filter to be either a normal operational bandwidth or wider than the normal operational bandwidth for rapidly setting time of the baseband filter.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: June 5, 2012
    Assignee: Mediatek Inc.
    Inventors: Chinq-shiun Chiu, Shou-tsung Wang
  • Patent number: 7663442
    Abstract: According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Feng Chen
  • Patent number: 7603084
    Abstract: A variable amplifier with adjustable current to correct for DC offset. The variable amplifier includes a zero function, allowing for zeroing of some amplifiers in an amplifier chain during correction for DC offset of another amplifier in an amplifier chain. In some embodiments selectable current injection is provided to an amplifier chain in conjunction with signals from selectable mixers.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: October 13, 2009
    Assignee: Wionics Technologies, Inc.
    Inventor: Turgut Aytur
  • Patent number: 7599670
    Abstract: DC power savings in a mobile communication device can be achieved by dynamically adjusting the biasing for a receiver based on the communication link quality. The output signal levels of at least one low noise amplifier (LNA) are monitored to identify the DC operating conditions for the LNA. Closed loop control of the DC biasing is adjusted based on a comparison between the monitored DC operating conditions and a reference signal. The output of the LNA is also coupled to a radio receiver section that is configured (e.g., SW or HW) to evaluate the link quality based on various criteria such as inter-modulation distortion, noise, interference, fading, etc. The reference signal that is used to control the DC biasing of the LNA is adjusted (periodically, continuously, or on demand) in response to the evaluated link quality. The dynamic biasing yields acceptable signal reception with low DC power consumption.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: October 6, 2009
    Assignee: Microsoft Corporation
    Inventor: James B. Turner
  • Patent number: 7058360
    Abstract: A method for stabilizing the performance variation of a primary radio frequency (RF) device is provided that includes providing a secondary RF device. An output signal is generated with the secondary RF device. The output signal is provided to a feedback circuit. A feedback signal is generated based on the output signal with the feedback circuit. The feedback signal is provided to the secondary RF device. The output signal is generated based on the feedback signal. The feedback signal is provided to the primary RF device.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: June 6, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Daniel R. Meacham
  • Patent number: 6975848
    Abstract: A filter module for reducing a DC offset voltage in a radio frequency communication channel is described. A first capacitor is coupled between a first differential input node and a first differential output node. A second capacitor is coupled between a second differential input node and a second differential output node. An active variable resistor is coupled between the first differential output node and the second differential output node. The active variable resistor receives a control signal. The control signal adjusts the value of the active variable resistor, which adjusts the frequency response of the filter module. The rate at which the filter module reduces DC offset voltages is thereby adjusted. The filter module is also adaptable to single-ended applications.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: December 13, 2005
    Assignee: ParkerVision, Inc.
    Inventors: Gregory S. Rawlins, Kevin Brown, Michael W. Rawlins, David F. Sorrells
  • Patent number: 6630866
    Abstract: The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to &bgr;2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form: &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, speed performance is increased and bandwidth is extended.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: October 7, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Neil Gibson, Marco Corsi, Tobin Hagan
  • Patent number: 6600371
    Abstract: It is shown a low noise amplifier comprising a first circuit block suitable for converting a first amplifier input voltage signal into current, a second circuit block adapted to divide the current coming from said first block, said second block being controlled by a second voltage signal, said first and second blocks conferring a variable voltage gain to the amplifier. The amplifier comprises at least one first and at least one second resistors and a feedback network, said at least one first resistor connected with one first output terminal of said second block and with a supply voltage, and said at least one second resistor being connected between said at least one first and at least one second output terminals of said second block, and said feedback network being coupled with said at least one first terminal and with said first circuit block, and said at least one second terminal being coupled with at least one output terminal of said low noise amplifier.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: July 29, 2003
    Assignee: STMicroelectronics s.r.l.
    Inventor: Giovanni Cali
  • Patent number: 6525602
    Abstract: An amplifier stage for a buffer with negative feedback includes an input stage having an input terminal, an output terminal, a first and a second supply terminal, a biasing branch, a first and a second balancing branch each comprising an active transistor for supplying, at the output terminal, a current depending on the current difference in the first and second balancing branches. The biasing branch and the first and second balancing branches are connected in parallel between the first and second supply terminals. The input terminal divides the biasing branch into two input branches having a constant-current generator. Each active transistor is connected to a corresponding current generator for receiving a control voltage correlated with a voltage at the terminals of the current generator.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: February 25, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luciano Tomasini, Jesus Guinea
  • Patent number: 6127888
    Abstract: There is disclosed a power amplification device for BTL-driving a load with a half-wave signal whose output direct current level is set close to an earth level, in which output signals of first and second output amplifiers (2) and (3) are added in an adder circuit (10). A higher output signal is selected from the two output signals and generated as an output signal c. Output currents of variable current sources (8) and (9) of the first and second output amplifiers (2) and (3) are controlled in response to the output signal c to change operating currents of the first and second output amplifiers (2) and (3). The operating currents are enlarged only when the output signals of the first and second output amplifiers (2) and (3) are enlarged. Thereby, the efficiency of the operating current of BTL drive type output amplifier is enhanced.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: October 3, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Kenichi Kokubo
  • Patent number: 6111464
    Abstract: An LDMOS RF amplifier having a bias voltage generated through feedback around an LDMOS sense transistor has a sense transistor, a current sensing circuit that monitors current in the sense transistor, and a bias voltage generation circuit controlled by an output of the current sensing circuit. The bias voltage from the bias voltage generation circuit is applied to the gates of both the sense transistor and an LDMOS RF power amplifier transistor. An AC-coupled RF input signal is applied through typical impedance-matching circuitry to the gate of the RF power amplifier transistor, and an AC-coupled output signal is tapped from, and power applied to, the drain of the RF power amplifier transistor through impedance matching circuitry of the type known in the art.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: August 29, 2000
    Assignee: Nokia Networks Oy
    Inventor: Steven J. Laureanti
  • Patent number: 5977829
    Abstract: A low distortion amplifier and method of reducing distortion in an amplifier at high output power in which energy dissipated while the amplifier is operating at low output power, is reduced. A bias circuit provides a quiescent bias current to the input stage of the amplifier for operating the amplifier without substantial distortion at low input signal levels and low output power. A sense transistor senses a current less than and proportional to an output current from the amplifier, and feeds back the sensed current to the input stage to augment the quiescent bias current when output power increases. When the output power decreases, the sensed current is removed in order to maintain the low power output bias currents.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: November 2, 1999
    Assignee: Harris Corporation
    Inventor: Glenn E. Wells
  • Patent number: 5825247
    Abstract: An improved power amplifier having complimentary power transistors connected in push-pull arrangement, and having a bias voltage source coupled to the transistors for generating a transverse idling current flowing through the complimentary pair of transistors. A regulating, feedback control circuit has a set point input and inputs connected to precision resistors connected to detect the current through the power transistors and the output current. Analog arithmetic computing circuits continuously compute the instantaneous difference between the detected transverse idling current through the power transistors and the set point input for the idling current. The output of the controller circuit is connected to the bias voltage sources to vary the bias voltage in proportion to the instantaneous difference between the detected transverse idling current and the set value of idling current to maintain a constant, transverse idling current.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: October 20, 1998
    Assignee: Mircea Naiu
    Inventor: Jochen Herrlinger
  • Patent number: 5825246
    Abstract: The amplifier (200) includes an input stage (220) coupled to two output transistors (281, 282) having a common terminal at the output terminal (206) of the amplifier. Class AB operation of the output transistors (281, 282) is possible at a comparatively low supply voltage. In order to obtain such operation, measurement transistors (271, 272) are coupled to the same control input (283, 284) as the output transistors (281, 282). These measurement transistors (271, 272) are serially coupled to a current mirror (260). The quiescent current of the output transistors (281, 282) is measured and used to produce a feedback signal which is superimposed to the control signals.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: October 20, 1998
    Assignee: Motorola, Inc.
    Inventors: Vladimir Koifman, Yachin Afek, Israel Kashat
  • Patent number: 5537081
    Abstract: An audio amplifier with no turn-on pop noise is achieved by the following features: (i) an input stage which operates under zero common-mode input voltage, (ii) an output stage which provides the low voltage end of its voltage swing very close to ground voltage, and (iii) a system of shunt circuits for discharging external capacitors, so as to prevent, upon subsequent power-up, pop noises due to residue charges in the external capacitors. In one embodiment, two peripheral collector transistors are provided to implement a window comparator for discharging the input terminals, the bias voltage and the output terminal of the audio amplifier.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: July 16, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Toyojiro Naokawa, Hiroshi Hirayama
  • Patent number: 5495214
    Abstract: At high frequencies, a video amplifier draws a higher current and normally is biased to provide such current. However, since high frequencies are rarely encountered, the present circuit controls the operating point as a function of the frequency. More specifically, a controlled variable which controls the operating point of the amplifier stage is obtained in dependence on the frequency to which the amplifier stage is driven.
    Type: Grant
    Filed: June 16, 1994
    Date of Patent: February 27, 1996
    Assignee: Deutsche Thomson-Brandt GmbH
    Inventor: Bernhard Malota
  • Patent number: 5361041
    Abstract: An improved push-pull amplifier having a driver circuit for driving a source follower output transistor. The driver circuit includes a replicating transistor having electrical characteristics substantially similar to those of the source follower transistor, a buffer amplifier, and a circuit, coupled to the replicating transistor and the buffer amplifier, for summing the voltage across the replicating transistor and the buffer output signal to provide a gate signal to the source follower output transistor. A cross current feedback circuit regulates the quiescent current flow through the output transistors by adjusting the gate signal provided to the upper, source follower output transistor in response to a sensed current flow through the lower output transistor.
    Type: Grant
    Filed: June 17, 1993
    Date of Patent: November 1, 1994
    Assignee: Unitrode Corporation
    Inventor: Charles A. Lish
  • Patent number: 5237261
    Abstract: A voltage step-up regulator produces a frequency control voltage for a frequency synthesizer in a radio transmitter using a low operating voltage. To minimize the disturbances conveyed elsewhere in the radio device, the step-up regulator comprises an amplifying transistor controlled by an oscillator signal which operates as a class A amplifier, the output of amplifying transistor (Q1) including a diode and two selectively coupled capacitors for rectifying and filtering the amplified signal. The step-up regulator further comprising a feedback circuit for stabilizing the output voltage by adjusting the amplitude of the amplified signal.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: August 17, 1993
    Assignee: Telenokia Oy
    Inventor: Arto Haapakoski
  • Patent number: 5229721
    Abstract: An amplifier which combines the low quiescent current requirements of a Class B transistor amplifier with the minimal distortion qualities of a Class AB amplifier. In one disclosed embodiment the amplifier is utilized as a receiver amplifier and as a transmitter in a modular telephone adapter for coupling a telephone headset to a conventional modular telephone comprising a handset and a base unit. Signal expansion circuitry takes advantage of the dynamic emitter resistance of transistors in the amplifier's output stage through modulation of collector current in the output transistors and inverted phase summation of the resulting error signal with the input signal. DC bias circuitry supplies a current supply which is relatively insensitive to changes in power supply or device parameters.
    Type: Grant
    Filed: April 6, 1992
    Date of Patent: July 20, 1993
    Assignee: Plantronics, Inc.
    Inventor: Wayne R. Stade
  • Patent number: 5202646
    Abstract: An output stage for an amplifier includes first and second load current-carrying n-p-n output transistors disposed in different respective amplifier branches having different amplification properties. Negative feedback and limiting circuitry provides a negative feedback current to the first one of the output transistors and limits the negative feedback current to a preselected maximum value over a predetermined output current range whereby the amplification properties of the first one of the output transistors are affected in a range of output voltages of the amplifier stage.
    Type: Grant
    Filed: October 23, 1991
    Date of Patent: April 13, 1993
    Assignee: Telefunken Electronic GmbH
    Inventors: Gutsch Henrik, Rebmann Volkmara, Schnabel Jurgen
  • Patent number: 5175749
    Abstract: An apparatus automatically corrects for DC offset in a multi-level packet-switched receiver. A reference carrier frequency is used during the receiver's idle mode to establish a DC offset exiting a discriminator (302). The DC offset is amplified by a video amplifier (315) and fed into an error amplifier (320) which generates the negative of the DC offset. The DC offset and the negative of the DC offset are input into a summing network (330) resulting in a zero DC offset exiting the video amplifier (315).
    Type: Grant
    Filed: January 25, 1991
    Date of Patent: December 29, 1992
    Assignee: Motorola, Inc.
    Inventors: David A. Ficht, Gary D. Schulz
  • Patent number: 5162752
    Abstract: An improved working point adjusting circuit for a single power amplifier having multiple output circuits. When this simple circuit is connected to a Class B transistor power amplifier to support two or more output channels or speakers, it adjusts the working point of the transistors in the output circuit of the power amplifier to the linear portion of the current-voltage characteristics of the transistor so the amplifier works in the level of a Class A amplifier. It provides many significant advantages including (1) much higher energy efficiency on output transistors; (2) much less signal distortion on loaded speakers; (3) simple circuitry for increased reliability; (4) low component count for reduced costs; and (5) individualized adjustment for each output channels which eliminates the different effect caused by the very fine differences between the multiple loaded output devices such as loudspeakers.
    Type: Grant
    Filed: November 21, 1991
    Date of Patent: November 10, 1992
    Assignee: Josef Lakatos
    Inventor: Gyula Padi
  • Patent number: 5087890
    Abstract: An amplifier circuit includes a negative feedback connected amplifier and a series circuit comprising a capacitor, one end of which is connected to an output terminal of the amplifier, and a resistor, one end of which is connectable to a reference potential. A comparator is provided which has first and second inputs and one output. The first input is connected to a junction between the capacitor and the resistor, the second input is connected to an output of the amplifier, and the output of the comparator is connected to one input of the amplifier. The comparator does not react to an AC signal of a specific frequency band, but operates to set the output offset voltage only to one fractional part of the transition gain, and therefore operates to accomplish offset compensation without using a large capacitor.
    Type: Grant
    Filed: September 19, 1990
    Date of Patent: February 11, 1992
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuhisa Ishiguro, Masanori Fujisawa
  • Patent number: 5070308
    Abstract: A working point adjusting circuit for a power amplifier. When this simple circuit is connected into a Class B transistor power amplifier it adjusts the working point of the transistors in the output circuit of the power amplifier to the linear portion of the current-voltage characteristics of the transistor so the amplifier works in the level of a Class A amplifier. It provides many significant advantages including (1) much higher energy efficiency on output transistors; (2) much less signal distortion on loaded speakers; (3) simple circuitry for increased reliability; and (4) low component count for reduced costs.
    Type: Grant
    Filed: September 25, 1990
    Date of Patent: December 3, 1991
    Inventor: Gyula Padi
  • Patent number: 4922208
    Abstract: In an output stage of an operational amplifier comprising first and second NPN output transistors a circuit is coupled between the positive supply conductor and the collector of the first NPN transistor for providing a boosted base current drive thereto as a function of the load current sourced from the emitter of the first transistor to the output of the operational amplifier. The circuit senses the collector current flowing through the first transistor for increasing the base current drive thereto as the collector current increases.
    Type: Grant
    Filed: April 7, 1989
    Date of Patent: May 1, 1990
    Assignee: Motorola, Inc.
    Inventors: David M. Susak, Robert L. Vyne
  • Patent number: 4918400
    Abstract: An amplifier circuit comprising an input amplifier stage, a push-pull output stage, a bias stage having the same construction as the input amplifier stage, a first resistor to be given a current flowing through the bias stage, second and third resistors connected along with the first resistor between a power supply and the ground in series therewith, and fourth and fifth resistors connected between the output point of the push-pull output stage and the ground in series therewith. The point of connection between the fourth resistor and the fifth resistor is connected to the input amplifier stage to provide a negative feedback loop having no capacitor.
    Type: Grant
    Filed: April 18, 1989
    Date of Patent: April 17, 1990
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Takashi Otsuki
  • Patent number: 4888502
    Abstract: A variable bandwidth filter comprises a transistor long-tailed pair. One of the transistors of the pair has a field effect transistor which is connected in the collector circuit of the transistor and which is used as a variable collector load resistor. The field effect transistor is shunted by a capacitor and the gate of the field effect transistor is fed with a control voltage via a feed-back control loop arrangement which serves to maintain constant the d.c. voltage across the field effect transistor whereby the effective bandwidth of a filter circuit defined between the base of the said one transistor is arranged to be controllable in dependence upon the current in the common tail of the pair as determined by a variable current source connected in the tail.
    Type: Grant
    Filed: February 1, 1988
    Date of Patent: December 19, 1989
    Assignee: Plessey Overseas Limited
    Inventor: Adrian E. Jarrett
  • Patent number: 4833423
    Abstract: In a wide-band direct-coupled transistor amplifier, the current through the power output stage must be stabilized to prevent fluctuations in the amplifier output signal. To stabilize the output stage current, a negative feedback loop is established providing a bias control for the amplifier input stage. In the past, voltage feedback apparatus, typically including operational amplifiers, has been utilized. In the present invention, a current feedback path, which avoids the voltage level translation inherent in the prior art, is used to provide the feedback bias control for the input stage of the amplifier. A technique for the compensation of temperature drift and for voltage offset is described.
    Type: Grant
    Filed: July 20, 1987
    Date of Patent: May 23, 1989
    Assignee: Apex Microtechnology Corporation
    Inventor: John J. Molloy
  • Patent number: 4647866
    Abstract: Apparatus and method for driving a non-centertapped load such as a loudspeaker from a low voltage supply such as a single dry cell, with increased efficiency. A push-pull signal having similar polarity voltage excursions is applied to opposite terminals of the load. Alternate individual terminals of the load which are opposite to the terminals to which the non-idle phases of the push-pull signal are alternately applied are connected to a common terminal via a pair of transistors. The pair of transistors are driven by an amplified representation of the push-pull input signal. Since pulse signals are not used to drive the pair of transistors, capacitors need not be used to eliminate switching transients which would otherwise appear, and increased efficiency results.
    Type: Grant
    Filed: January 17, 1985
    Date of Patent: March 3, 1987
    Assignee: Siltronics, Ltd.
    Inventor: Russell W. Brown
  • Patent number: 4531100
    Abstract: An amplifier which is particularly suitable for low supply voltage operation and which is relatively insensitive to power supply voltage variations includes a signal amplifying stage (11) and a control stage (10). The signal amplifying stage (11) includes the output load (13), such as a loudspeaker, in series with a transistor (12) which is controlled by a current mirror circuit (14, 15, 16) in the control stage. The circuit acts by continuously comparing part of the voltage across the output load (13) with a very low reference voltage arising from the difference in the base-emitter voltages of two transistors (14, 15) operating at unequal collector current values. This causes voltage excursion peaks appearing at the junction of the output load (13) and the amplifying transistor (12) to be clamped to a voltage equal to or otherwise related to that at the opposite side of the output load (13).
    Type: Grant
    Filed: July 11, 1983
    Date of Patent: July 23, 1985
    Inventor: Francis W. Adkin
  • Patent number: 4521740
    Abstract: An amplifier output circuit in which crossover distortion is largely eliminated, temperature compensation of idle current is obviated, and the idle current is maintained stable, independent of the magnitude of the input signal. In one embodiment in which two output amplifying elements are connected in a Class B SEPP circuit configuration, first and second error signal amplifiers are provided. While the first error amplifier functions as an error amplifier for an error voltage level shifted between the voltage at the output electrode of its current amplifying element and the voltage at the circuit input terminal, the second error amplifier functions as an error amplifier for an error voltage level shifted between the voltage at the output terminal of its amplifying element and the voltage at the circuit output terminal.
    Type: Grant
    Filed: February 18, 1983
    Date of Patent: June 4, 1985
    Assignee: Pioneer Electronic Corporation
    Inventor: Kazuaki Nakayama
  • Patent number: 4499431
    Abstract: An apparatus for improving the salient properties of the output stages of electronic power amplifiers v.s. varying load conditions. A novel circuit, based on current feedback sensing the instantaneous drive current of the output devices, is used to linearize the output characteristics of the output devices. The important features, compared with the presently known and employed drive circuits, relate to a more linear transfer characteristic, much larger output current capability, and more output amplifier design.
    Type: Grant
    Filed: May 3, 1982
    Date of Patent: February 12, 1985
    Assignee: Shin-Shirasuna Electric Corp.
    Inventor: Matti N. Otala
  • Patent number: 4491804
    Abstract: A Class AB amplifier circuit includes bias circuitry for biasing the output transistor into partial conduction independent of the base-to-emitter voltage of the transistor. The bias circuitry is a simple circuit loop including the output transistor and forms the remainder of the amplifier circuit which can be fabricated in monolithic integrated circuit form. The loop comprises a differential amplifier for providing a substantially constant offset voltage across a pair of terminals between which is connected a current biasing component. The current biasing component is connected in series with the output transistor to produce a small quiescent current to flow therethrough, the value of which is independent of the transistor's characteristics.
    Type: Grant
    Filed: November 18, 1982
    Date of Patent: January 1, 1985
    Assignee: Motorola, Inc.
    Inventors: W. Eric Main, Dennis L. Welty, Don W. Zobel
  • Patent number: 4442409
    Abstract: A push-pull amplifier having like conductivity output transistors is driven by a phase-splitter transistor amplifier. The collector load of the phase-splitter includes a diode bridge for establishing the amplifier idling current. One arm of the bridge incorporates the pull-up output transistor base-emitter junction-the current conducted therein being accurately determined by bridge parameters.
    Type: Grant
    Filed: February 25, 1982
    Date of Patent: April 10, 1984
    Assignee: RCA Corporation
    Inventor: Donald R. Preslar
  • Patent number: 4370623
    Abstract: An amplifier arrangement is provided which comprises first and second biasing power supply circuits, a push-pull amplifier comprising a pair of transistors, a DC amplifier having a non-inverting input terminal connected to a junction point at which one half of a predetermined potential fed from the first biasing power supply circuit is applied and an inverting input terminal connecting a feedback loop through which the output the amplifier is fedback, a second biasing power supply circuit having a junction point at which the output of the DC amplifier is applied, and means responsive to an output of the DC amplifier for applying either of the first and second predetermined potentials fed from the first and second biasing circuits in accordance with the amount of feedback from the output of the push-pull amplifier to produce an output signal showing a biasing current, whereby the output signal is applied to each base of the push-pull transistors so as to balance the half potential of the first biasing power su
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: January 25, 1983
    Assignee: Kabushiki Kaisha Nagasawa
    Inventor: Hideki Nagasawa
  • Patent number: 4356452
    Abstract: A class A complementary push-pull amplifier comprising first amplification means and second amplification means complementary in type to the first amplification means; first and second current detection means for detecting each output current of the first and second amplification means, each current detection means being coupled in serial relation with each other between output points of the first and second amplification means and a load of the push-pull amplifier being connected to a junction point of the first and second current detection means; comparator means for comparing a potential difference developed across the first current detection means and/or the second current detection means with a constant voltage to produce a control signal; and bias setting means for feeding bias current to the first and second amplification means in proportion to the control signal thereby to maintain the sum of output currents of the first and second amplification means constant.
    Type: Grant
    Filed: August 26, 1980
    Date of Patent: October 26, 1982
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Masayuki Iwamatsu
  • Patent number: 4336504
    Abstract: A push-pull output circuit which is capable of producing a relatively-high maximum output voltage without the use of a bootstrap capacitor provides positive and negative half cycle output circuits which are constructed as inverted Darlington output circuits to which current mirror circuits and level shifting elements are coupled. As a result, the distortion factor of an open loop characteristic in the push-pull output circuit is improved.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: June 22, 1982
    Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.
    Inventors: Kunio Seki, Norihisa Katoh
  • Patent number: 4283683
    Abstract: A circuit responsive to applied audio signals for amplifying the same and providing the amplified signals across differential output terminals. The circuit comprising an audio amplifying section which is responsive to the audio input signals for amplifying the same and a feedback circuit connected across the output terminals for providing a feedback signal to the amplifier section to reduce any direct current offset voltage errors appearing across the output terminals to a minimum value. Additionally, the amplifier section includes circuitry for setting the quiescent voltage bias levels of the output terminals to a predetermined level and for providing common-mode rejection of voltage supply line ripple.
    Type: Grant
    Filed: May 29, 1979
    Date of Patent: August 11, 1981
    Assignee: Motorola Inc.
    Inventor: William E. Main
  • Patent number: 4237425
    Abstract: A bias adjusting circuit for a push-pull amplifier is disclosed, which automatically increases or decreases the bias in the amplifier circuit so that the desired bias level is maintained. The bias adjusting circuit measures the current consumption of both halves of the push-pull amplifier, determines the point at which output current zero crossings have occurred, and at these times makes any necessary changes to the bias current to conform to a desired level. The circuit has an insignificant effect on the amplifier's power efficiency, and offers a degree of bias stability unattainable with conventional techniques.
    Type: Grant
    Filed: May 3, 1979
    Date of Patent: December 2, 1980
    Inventor: David A. Spiegel
  • Patent number: 4220930
    Abstract: A quasi-linear amplifier, wherein each of first and second current dividers maintains a constant ratio between drive currents to respective output transistor means and dummy output transistor means, uses regulation of the quiescent drive currents to the dummy output transistors to establish the quiescent drive currents to the output transistors. The quiescent drive currents to the output transistors are maintained at levels conditioning these transistors for Class AB amplification of signal currents.
    Type: Grant
    Filed: December 26, 1978
    Date of Patent: September 2, 1980
    Assignee: RCA Corporation
    Inventor: Adel A. A. Ahmed
  • Patent number: 4095128
    Abstract: A push-pull switching circuit including two grounded emitter transistors 5, 6 controlled by a pair of AND gates 3, 4. The collector output of each transistor is fed back to an input of the AND gate controlling the other transistor, the remaining AND gate inputs being supplied by the Q and Q outputs of a flip-flop circuit 2. During the prolonged conduction of each transistor due to minority carrier storage, its lowered collector potential prevents the enabled AND gate for the other transistor from raising its output and initiating conduction, thereby avoiding overlapping or simultaneous transistor conduction.
    Type: Grant
    Filed: February 1, 1977
    Date of Patent: June 13, 1978
    Assignee: Furuno Electric Co., Ltd.
    Inventor: Hidetoshi Tanigaki
  • Patent number: 4090139
    Abstract: Series-connected, field-effect transistors (FET's) of complementary conductivity types are employed to mix two or more input signals. The transistors are quiescently biased in their linear operating range. Each input signal is applied to the gate electrode of one FET and the gate electrode of the corresponding FET of opposite conductivity type in the series string. The output signal containing sum and difference frequencies is available at a common drain connection between two adjacent transistors of opposite conductivity types at the center of the string.
    Type: Grant
    Filed: March 4, 1977
    Date of Patent: May 16, 1978
    Assignee: RCA Corporation
    Inventor: Merle Vincent Hoover