Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

Abstract: A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Abstract: A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Abstract: A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.

Abstract: A power switch circuit is disclosed. The power switch circuit includes an input terminal, an output terminal, a first switch, a second switch, a sensing switch and an adjusting circuit. The first switch is coupled to the input terminal. The second switch is coupled to the first switch and the output terminal. A first node between the first switch and the second switch has a first node voltage. A breakdown voltage of the second switch is higher than that of the first switch. The sensing switch is coupled to the input terminal and the first switch. The adjusting circuit is coupled to the first node and the sensing switch. A second node between the adjusting circuit and the sensing switch has a second node voltage. The adjusting circuit adjusts the second node voltage according to the first node voltage to make it equal to the first node voltage.

Abstract: A signal amplifier includes one or more driver stage amplifiers and a power stage amplifier. The one or more driver stage amplifiers are connected in series. The one or more driver stage amplifiers and the power stage amplifier are connected to the same power supply, such that each of the at least one driver stage amplifier forms a loop with the power stage amplifier. The signal amplifier can further include a wave trap unit configured to block an oscillation frequency in the loop. One terminal of the wave trap unit is connected to the loop. The other terminal of the wave trap unit is grounded.

Abstract: An apparatus includes a digital-to-analog converter (DAC) and an independently controlled biasing circuit coupled to the DAC. The DAC includes at least a first transistor and a second transistor, where the first and second transistors are configured to provide output signals for the DAC. The biasing circuit includes a third transistor having a body coupled to the third transistor source and this source is coupled to a first transistor body and to a second transistor body of the first and second transistors of the DAC. A current loop is coupled to the source and the drain of the transistor of the biasing circuit that maintains a substantially same value of current in the biasing circuit as in the DAC.

Abstract: An amplifier includes two input terminals to receive a differential, two-tone transmission signal; two output terminals; a coil having terminals connected with the input terminals respectively, and a center tap; a first transistor having the gate connected with one terminal of the coil, and the output terminal connected with one output terminal; a second transistor having the gate connected with the other terminal of the coil, and the output terminal connected with the other output terminal; a diode having a terminal connected with the center tap; and a bias circuit connected with the other terminal of the diode to output a gate voltage to turn on the first and second transistors. The diode adjusts the terminal voltage depending on a signal level of a double harmonic wave of the transmission signal supplied to the terminal of the diode from the center tap.

Abstract: Apparatus having structures implementing compact and symmetric multi-way transformer combiners are described herein. In an embodiment, each unit device cell of a plurality unit device cells may include two metal layers on top of the unit device cell coupled to a multi-way transformer combiner by one of the two metal layers such that the configuration of the unit device cells with the multi-way transformer combiner is symmetric. Additional apparatus, systems, and methods are disclosed.

Abstract: An apparatus for amplifying power is provided. The apparatus includes a supply modulator for generating a supply voltage based on an amplitude component of a transmission signal, and a power amplify module for amplifying power of the transmission signal using the supply voltage, wherein the power amplify module includes a first power amplifier and a second power amplifier, and when an output power of the transmission signal is greater than a reference power, the first power amplifier amplifies the power of the transmission signal using the supply voltage, and when the output power of the transmission signal is equal to or less than the reference power, the second power amplifier amplifies the power of the transmission signal using the supply voltage.

Abstract: A push-pull amplifier has an input node and a series connection of two resistors. The series connection comprises a first terminal, a second terminal, and a third terminal. A first resistor of the two resistors is connected between the first terminal and the second terminal. A second resistor is connected between the second and third terminals. The input node is connected to the second terminal. A first controllable current source is connected to the first terminal of the series connection for sourcing a first current to the series connection. A second controllable current source is connected to the third terminal of the series connection for sinking a second current from the series connection. A first transistor and a second transistor are connected in push-pull configuration, wherein a control input of the first transistor is connected to the first terminal of the series connection and a control input of the second transistor is connected to the third terminal of the series connection.

Abstract: An amplification system is provided that comprises a push-pull amplifier system having a first power transistor series coupled with a second power transistor that alternately switch between a push-pull amplifier mode of operation and a single-ended amplifier mode of operation. In the push-pull amplifier mode, both the first power transistor and the second power transistor alternately conduct to provide an amplified output signal to an output load in response to an input signal having an amplitude that is greater than or equal to a threshold level. In the single-ended amplifier mode of operation, the first power transistor conducts and the second power transistor is disabled for amplification purposes in response to the input signal having an amplitude that is less than the threshold level.

Abstract: An amplifier including: an output stage having two first power supply terminals capable of receiving a first voltage defined by first positive and negative variable potentials with respect to a reference potential; and a circuit for controlling the current in transistors of the output stage with a reference value, wherein the output stage includes a first and a second MOS transistors in series between the first two terminals, the junction point of this series association defining an output terminal of the amplifier; the control circuit includes two measurement MOS transistors having their respective sources and gates coupled to the respective sources and gates of the first and second transistors of the output stage; at least one control branch, comprising transistors in series between two terminals of application of a second voltage, defines nodes connected to the gates of the output transistors, said second voltage being greater than the first one.

Abstract: An amplification system is provided that comprises a push-pull amplifier system having a first power transistor series coupled with a second power transistor that alternately switch between a push-pull amplifier mode of operation and a single-ended amplifier mode of operation. In the push-pull amplifier mode, both the first power transistor and the second power transistor alternately conduct to provide an amplified output signal to an output load in response to an input signal having an amplitude that is greater than or equal to a threshold level. In the single-ended amplifier mode of operation, the first power transistor conducts and the second power transistor is disabled for amplification purposes in response to the input signal having an amplitude that is less than the threshold level.

Abstract: A Doherty amplifier (100) is described which comprises an input terminal (102) for receiving an input signal (101) and an output terminal (103) for providing an amplified signal (104) of the input signal (101). The Doherty amplifier is supplied by a first supply voltage and a second supply voltage which have opposite polarities in respect to a reference level.

Abstract: A power amplifier according to the present invention includes: an input-side transformer which has an annular primary coil which is a first metal line and a plurality of linear secondary coils which are second metal lines, and matches input impedance and divides the input signal into a plurality of split signals; push-pull amplifiers each including a pair of transistors for amplifying one of the split signals; and an output-side transformer which has an annular secondary coil which is a third metal line and a plurality of linear primary coils which are fourth metal lines, and combines the amplified split signals and matches output impedance, two input terminals of the pair of transistors being connected to each other via each of the second metal lines and two output terminal of the pair of transistors being connected to each other via each of the fourth metal lines.

Abstract: Disclosed are circuits, techniques and methods for buffering a high frequency signal for transmission over an integrated circuit. In one particular implementation, a plurality of amplification circuits are individually biased for amplifying a signal from a voltage controlled oscillator and/or digitally controlled oscillator to provide a local oscillator signal on a device.

Abstract: In one example, an amplifier for providing stable output quiescent current comprising includes a number of supply rails, an output device configured for providing an output voltage, the output device coupled to the plurality of supply rails, and an output quiescent current controller coupled to the plurality of supply rails and the output device, the output quiescent current controller to regulate the voltage in the output device to provide a consistent quiescent current in the output device.

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.

Abstract: A Bi-Directional and Adjustable Current Source (“BACS”) for providing an amplifier input with a voltage signal that is linear, where an output of the BACS and the amplifier input are shunted with a capacitor, is described. The BACS may include a first switch in signal communication with a high voltage reference and a first current source in signal communication with the first switch. The BACS may also include a second switch in signal communication with a low voltage reference and a second current source in signal communication with the second switch. The BACS may further include a directional current element in signal communication with both the first current source, the second current source, the output of the BACS, the amplifier input, and the capacitor, where the directional current element is configured to prevent current flow from the output BACS to the first current source.

Abstract: A class-AB driver design with improved frequency response is disclosed. In one embodiment, the class-AB driver includes a push-pull output stage, a trans-linear loop, an input stage, a current biasing and enabling circuit. Further, the trans-linear loop is coupled to a signal input terminal ABIN via node A, and the push-pull output stage is coupled to the trans-linear loop via node B and node C. Further, the trans-linear loop includes a speed balancing resistor RB in a faster signal traveling path (i.e., ABIN to ABOUT via node A and B) to match up the speed with a slower signal traveling path (i.e., ABIN to ABOUT via node A and C). In another embodiment, the MOS transistors are also used instead of the speed balancing resistor RB to balance the signal traveling time of the two signal traveling paths.

Abstract: An amplifying apparatus including an amplifier having a first FET, a second FET having a source connected to a drain of the first FET, a load resistance connected to a drain of the second FET, a first bias circuit configured to supply a first bias voltage to a gate of the first FET, and a second bias circuit configured to supply a second bias voltage to a gate of the second FET. The second bias circuit includes a second comparison circuit configured to send a control signal to the gate of the second FET so that a bias voltage of a connection node between the first and second FETs changes in conjunction with an output voltage of the first bias circuit.

Abstract: A power amplifying apparatus based on envelope elimination and restoration (EER) includes a voltage amplifier to amplify a high frequency component of an envelope signal, a switching amplifier to generate a low frequency component signal of a drain bias based on a first pulse width modulation (PWM) signal that corresponds to a low frequency component of the envelope signal, and a push-pull switch, connected to the switching amplifier in parallel, to add a high frequency component signal to an output of the switching amplifier by pushing or pulling current to or from the output of the switching amplifier.

Abstract: A class-AB driver design with improved frequency response is disclosed. In one embodiment, the class-AB driver includes a push-pull output stage, a trans-linear loop, an input stage, a current biasing and enabling circuit. Further, the trans-linear loop is coupled to a signal input terminal ABIN via node A, and the push-pull output stage is coupled to the trans-linear loop via node B and node C. Further, the trans-linear loop includes a speed balancing resistor RB in a faster signal traveling path (i.e., ABIN to ABOUT via node A and B) to match up the speed with a slower signal traveling path (i.e., ABIN to ABOUT via node A and C). In another embodiment, the MOS transistors are also used instead of the speed balancing resistor RB to balance the signal traveling time of the two signal traveling paths.

Abstract: A signal processing circuit is proposed, which is intended to receive a pair of input signals Sp and Sn in phase opposition on two input terminals and to provide two pairs of output currents SIp and SIn in phase opposition on four output terminals. Each input signal Sp and Sn is amplified in an amplification unit LNAUp and LNAUn and subsequently split in a splitting unit SPLUp and SPLUn. The invention is such that each of the two splitting units SPLUp and SPLUn includes at least two branches, respectively BIp, BQp and BIn, BQn connected between said amplification unit, respectively LNAUp and LNAUn, and one of said output terminals, the four branches BIp, BQp and BIn and BQn each including at least an impedance, respectively RIp, RQp, RIn, RQn, having identical characteristics. Mixer circuits can be easily stacked with this signal processing circuit.

Abstract: An amplifier circuit uses low threshold voltage devices for mid rail response in low voltage applications, but uses a high threshold voltage device at an output stage of the amplifier to generate an output from the amplifier.

Abstract: An analogue amplifier with multiplexing capability, without the need to incorporate a multiplexor, comprising an input port, a test input port, an output port, a control input to switch the amplifier between a normal amplifying mode and a test mode, wherein a analogue signal introduced to the input port is amplified to the output port in normal mode, and a test signal on the test port is routed to the output port when the amplifier is in test mode.

Abstract: An apparatus for compensating operating current in an amplifier device when supply voltage to the amplifier device decreases below a predetermined value at an input voltage supply locus includes: (a) A first control circuit coupled with the input voltage supply locus. The first control circuit generates an output signal at an output locus when the supply voltage decreases below the predetermined value. (b) A second control circuit coupled with the output locus and coupled with the amplifier device. The second control circuit effects the compensating in response to the output signal.

Abstract: An amplifier comprises a Low Noise Amplifier (LNA) that amplifies a Radio Frequency (RF) signal that includes a transconductance, a gain and an input stage that receives the RF signal. A bias assembly includes a bias circuit with a bias resistance and generates a bias current for the input stage of the LNA, which is related to the bias resistance. A shunt feedback stage amplifies an output of the input stage, generates an RF output and includes a shunt resistance. Changes in the bias resistance due to changes in conditions are substantially offset by changes in the shunt resistance due to the changes in conditions, which reduces variation of the gain of the LNA based on the changes in conditions.

Abstract: An amplification circuit is provided for the signal output from a microphone in which the signal is amplified by a differential structure amplifier. The circuit includes the pull-up voltage, which initializes the operating state of the microphone, being coupled to a first input of the differential structure amplifier and to a second input of the differential structure amplifier through a pull-up resistor.

Abstract: An amplifier comprising a Low Noise Amplifier (LNA) to amplify a Radio Frequency (RF) signal. The LNA having a transconductance and including an input stage to receive the RF signal. The LNA again varying as a function of changes in conditions. A bias assembly to generate a bias current to bias the LNA input stage. The bias assembly configured to reduce variation of the LNA gain to changes in conditions.

Abstract: A push pull amplifier is disclosed having upper and lower output devices operating in a mode in which the devices drive a load alternately. The amplifier includes bias means for providing a bias current to the output devices at all times. The bias means is incorporated in a feedback loop and is arranged such that transitions from load current to minimum bias current in the upper and lower output devices are sufficiently gradual so that harmonic frequencies generated by the transitions are within the capability of the amplifier under all signal conditions. The feedback loop includes a non-linear transform circuit for each upper and lower output device to prevent the bias current reducing to zero. The feedback loop also includes a linearity control circuit for controlling the harmonic frequencies in the upper and lower output devices.

Abstract: It is shown a low noise amplifier comprising a first circuit block suitable for converting a first amplifier input voltage signal into current, a second circuit block adapted to divide the current coming from said first block, said second block being controlled by a second voltage signal, said first and second blocks conferring a variable voltage gain to the amplifier. The amplifier comprises at least one first and at least one second resistors and a feedback network, said at least one first resistor connected with one first output terminal of said second block and with a supply voltage, and said at least one second resistor being connected between said at least one first and at least one second output terminals of said second block, and said feedback network being coupled with said at least one first terminal and with said first circuit block, and said at least one second terminal being coupled with at least one output terminal of said low noise amplifier.

Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifying transistor to obtain a conduction angle of less than about 180°. The dc bias circuit includes a dynamic biasing circuit for decreasing the dc bias signal provided to the amplifying transistor as the input signal to the power amplifier circuit increases. This configuration permits the amplifier circuit to operate as a linearized Class C amplifier, having a substantially linear input-output relationship similar to that of a Class B amplifier, but with increased operating efficiency.

Abstract: A sensor for measuring a current passing through a load. The sensor has a power transistor having a first terminal connected to substantially constant voltage and a second terminal connected to the load. The sensor can sample a voltage difference with a variable capacitor, and a controller can be configured to cause a variable capacitor in the current sensor to have a capacitance inversely proportional to a resistance of the power transistor, whereby a charge stored on the variable capacitor is proportional to the current passing through the power transistor when the sampling switches are opened. A comparator can compare the current through the power transistor to a known reference current to generate a digital output signal. The sensor can include a power transistor, reference transistor and amplifier connected and configured so as to generate a signal on a reference line having a current of known proportion to the current passing through the load.

Abstract: An output stage (10) is provided having transistors of the same polarity type, which function to amplify the input signal at a wide range of frequencies, with low power consumption and low crossover distortion. By biasing the output transistors to remain on during both the positive and negative voltage swing of the input signal, low power consumption as well as low output crossover distortion is achieved. A high efficiency, low crossover distortion, current amplifier circuit for amplifying an input signal (VIN) in accordance with this present invention includes an output driver (12), a current source (IS1) and a translinear loop circuit (14). The output driver (12) includes a sourcing circuit (Q6). The current source (IS1), connected to the output driver (12), provides bias current to the sourcing circuit. The translinear loop circuit (14), connected to the output driver (12), receives the input signal (VIN).

Abstract: A class AB amplifier biasing circuit is provided for controlling the quiescent state of a pull-up output device and a complimentary pull-down output device. The biasing circuit includes first and second current sources, each having a floating resistor configured to supply current to the pull-up and pull-down devices, respectively. The biasing circuit also includes gate control circuits for controlling the gate voltages of the first and second floating resistors. A device replica transistor is connected to a voltage node associated with the gate of the either the pull-up device or the pull-down device.

Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180°. The dc bias circuit includes a dynamic bias boosting circuit for increasing the dc bias current provided to the amplifying transistor by the dc bias circuit in direct proportion to an increase in the input signal provided to the power amplifier. The bias boosting circuit permits the power amplifier circuits to operate in Class B or Class AB with improved power output characteristics and reduced power dissipation at low power levels.

Abstract: A system and method, wherein the dielectric absorption of a capacitor is cancelled by a compensating circuit. One embodiment uses a compensation circuit comprising a compensating capacitor with substantially identical characteristics as the capacitor to be compensated in an integrator circuit. The effects of the dielectric absorption of the capacitor in the integrator circuit are reduced or eliminated because the dielectric absorption of the compensating capacitor cancels the dielectric absorption of the capacitor in the integrator circuit. Another embodiment uses compensation circuitry to reduce or eliminate the effects of dielectric absorption in any particular capacitor. The compensation capacitor in the compensation circuitry has a higher rate of dielectric absorption and a lower capacitance value than the capacitor whose dielectric absorption effects are to be reduced or eliminated.

Abstract: Responsive to an external load, an output stage (201) of an amplifier (200) in accordance with the present invention provides a current boosting scheme capable of generating a large output current while maintaining a low quiescent current. The output stage (201) includes a sink control circuit (204) coupled to the input terminal (202) for receiving the output of the input amplifier stage. A translinear loop circuit (210) is coupled to the sink control circuit (204), for receiving the sink pass-through current and for producing a source pass-through current. A current mirror circuit (222) is coupled to the translinear loop circuit (210) for receiving the source pass-through and for producing a bias current output therefrom. An output driver (230) is coupled to the current mirror circuit (222) and the sink control circuit (204), wherein the output driver (230) receives the bias output current and the sink pass-though current to provide an output current.

Abstract: A method and apparatus for controlling amplifier operating angle provides a corresponding increase in amplifier efficiency through a continual adjustment of operating angle from Class A, through Class AB, to Class B, an improved bandwidth in the output stage by preventing the output stage from reaching cutoff and the ability to adjust the high frequency content of the drive waveform to match that of the output stage thereby attaining the highest efficiency consistent with required distortion levels. A push-pull amplifier is coupled to a differential pushpull current drive source with out of phase drive signals and a preprocessing circuit with a first set of current sources which mirror one drive signal and a second set of current sources which mirror the other drive signal.

Abstract: A MOSFET (1) performing a current source operation and a MOSFET (2) performing a current sink operation are both of n-channel type. An input voltage (Vin) to be inputted to a gate electrode of the MOSFET (2) is divided by two resistance elements (6 and 7) and then inputted to the gate electrode of the MOSFET (2). A transistor (4) is disposed between a drain electrode of a MOSFET (3) and a gate electrode of the MOSFET (1). A constant current (Ib1) supplied by a constant current source (8) separately flows into the transistor (4) and a resistance element (5). A constant reference voltage(Va) is inputted to a base electrode of the transistor (4), which is low enough to operate the MOSFET (3) within a triode region. This configuration achieves both larger dynamic range and easier control of idling current.

Abstract: An output stage for an amplifier AMP includes a first transistor T1 and a second transistor T2 having their main current paths arranged between two power supply terminals VCC and GND, the bias terminal of the first transistor T1 being connected to the output of the amplifier AMP and the bias terminal of the second transistor T2 being connected to the input of the amplifier AMP via a bias circuit BC. The bias circuit includes a detection module intended to signal the instant when the second transistor T2 enters the state of saturation, and an impedance matching module intended, when activated, to attribute a high impedance to the bias terminal of the second transistor T2 when the transistor becomes saturated. The circuit limits the value of a parasitic current injected into the substrate via a parasitic transistor PT2 which appears when the second transistor T2 is saturated.

Abstract: An amplifier arrangement includes a class-G amplifier, biased by a first and a second pair of bias voltages, a drive control circuit and a second amplifier (C) biased by the second pair of supply voltages, the drive control circuit (DCD) thereby being adapted to turn on said second amplifier (C) at a higher input signal amplitude than the input signal amplitude at which the current in the class-G amplifier is internally switched over from the first pair to the second pair of bias voltages.

Abstract: A sensor for measuring a current passing through a load. The sensor has a power transistor having a first terminal connected to substantially constant voltage and a second terminal connected to the load. The sensor can sample a voltage difference with a variable capacitor, and a controller can be configured to cause a variable capacitor in the current sensor to have a capacitance inversely proportional to a resistance of the power transistor, whereby a charge stored on the variable capacitor is proportional to the current passing through the power transistor when the sampling switches are opened. A comparator can compare the current through the power transistor to a known reference current to generate a digital output signal. The sensor can include a power transistor, reference transistor and amplifier connected and configured so as to generate a signal on a reference line having a current of known proportion to the current passing through the load.

Abstract: An output stage of an amplifier circuit includes: a sinking bipolar circuit 23 for sinking current from an external load; a sourcing transistor 14 for sourcing current to the external load, the sourcing transistor 14 coupled in series with the sinking bipolar circuit 23, a common output node 34 is formed between the sourcing transistor 14 and the sinking bipolar circuit 23; a mirroring transistor 16 coupled to the sourcing transistor 14 such that current in the sourcing transistor 14 approximately mirrors current in the mirroring transistor 16; a current mirror circuit 39 responsive to the mirroring transistor 16 and coupled to control current flow through the sinking bipolar circuit 23; and a translinear bias circuit 48 coupled to the sinking bipolar circuit 23 for maintaining a minimum current in the bipolar circuit 23.

Abstract: A power stage for an operational amplifier includes an output stage, a current source stage, and a gain stage. The output stage is formed by first and second NPN output transistors arranged in a Totem-Pole configuration, each having respective resistors connected between their respective base and emitter terminals. The output transistors are biased in class AB by a quiescent current supplied by the current source stage and are controlled dynamically by the gain stage. The gain stage includes an NPN gain transistor having a collector terminal connected to the base terminal of the first output transistor and an emitter terminal connected to the base terminal of the second output transistor.

Abstract: A comparator which for example can be used for a digital potentiometer is shown. Specifically, a dual differential input circuit with a push/pull amplifier at the output stage is disclosed wherein a crossing is detected in an inputted signal as the crossing occurs and wherein the push/pull amplifier pair at the output stage provides very fast detection of a crossing. This is particularly useful in acting as a trigger mechanism for changes in a digital potentiometer for example to elements noise caused as "wiper changes" occur.

Abstract: While no signals are being supplied to first and second drive circuits, the drive circuits keep supplying idling currents to the bases of first and second transistors which constitute a push-pull amplifier. A first control circuit is provided in the base-emitter path of the first transistor, to control the first transistor in accordance with an input signal. A second control circuit is provided in the base-emitter path of the second transistor, to control the second transistor in accordance with an input signal. The first control circuit comprises a third transistor, a first resistor connected between the collector and base of the third transistor, a third resistor connected between the collector of the third transistor and the base of the first transistor, a constant current source connected to the base of the third transistor.

Abstract: An amplifier system includes a constant current unit which produces a constant current in response to a source voltage from a source voltage terminal. An emitter follower unit has a base, an emitter and a collector, an input signal being supplied to the base, the emitter being connected to the constant current unit, the source voltage being supplied to the collector, the emitter follower unit producing an output signal at the emitter in response to the input signal. A current regulating unit regulates the constant current in response to a collector current fed into the collector of the emitter follower unit, so that the constant current is fed from the emitter of the emitter follower unit into the constant current unit.