Abstract: A compensation circuit includes a tail current source, an error amplifier; a compensation resistor, and a voltage-to-current converter circuit. The tail current source is configured to generate a tail current. The error amplifier is coupled to the tail current source and biased by the tail current. The compensation resistor is coupled to the error amplifier. The voltage-to-current converter circuit is coupled to the error amplifier. The compensation resistor is configured to vary in resistance responsive to a change in the tail current, or the voltage-to-current converter circuit is configured to vary in transconductance responsive to the change in the tail current.

Abstract: The present application provides a distributed LDO regulator structure without an external capacitor. The structure includes one CORE module; and one or more POWER modules driven by one of the CORE modules. The CORE module comprises a mirror source voltage generating circuit and a built-in LDO regulator circuit. An output end of an operational amplifier and a gate of the sixth PMOS together serve as a control voltage end of the POWER module. A negative input end of the operational amplifier is connected to a drain of the fifth PMOS and a source of the sixth PMOS by means of a first resistor, wherein a connection end serves as an output end of the built-in LDO regulator circuit. POWER modules having the same output voltage are connected to each other in parallel.

Abstract: A receiver includes an amplification block supporting carrier aggregation (CA). The amplification block includes a first amplifier circuit configured to receive a radio frequency (RF) input signal at a block node from an outside source, amplify the RF input signal, and output the amplified RF input signal as a first RF output signal. The first amplifier circuit includes a first amplifier configured to receive the RF input signal through a first input node to amplify the RF input signal, and a first feedback circuit coupled between the first input node and a first internal amplification node of the first amplifier to provide feedback to the first amplifier.

Abstract: According to an embodiment, the optical receiving circuit includes a current compensation circuit, a photodiode, and a transimpedance circuit. The current compensation circuit generates a first current having a positive temperature coefficient. The photodiode receives an optical signal, generates a first current signal including a photoelectric conversion current having a negative temperature coefficient, and outputs a second current signal which is the sum of the first current and the first current signal. The transimpedance circuit has a negative feedback resistor and receives the second current signal and generates an output voltage by current-voltage-converting the second current signal.

Abstract: An amplifier circuit includes a first transistor including a signal input portion into which a signal is input from the outside, and a load inductor connected between the first transistor and a power supply line. In addition, the amplifier circuit includes a feedback circuit, which is connected between any position between the load inductor and the first transistor and the signal input portion of the first transistor. The gain and linearity are determined as appropriate in accordance with the amount of feedback from this feedback circuit.

Abstract: A network element of a cable television (CATV) network, said network element comprising one or more amplifier units for amplifying downstream signal transmission for digital output into one or more output channels; means for detecting output power of all active digital output channels; means for providing a predetermined correlation between the detected output power of said active digital output channels and a corresponding minimum bias current for said one or more amplifier units; and means for adjusting the bias current of said one or more amplifier units on the basis of the predetermined correlation.

Abstract: A multi-radio access technology (RAT) envelope tracking (ET) amplifier apparatus is provided. The multi-RAT ET amplifier apparatus may be configured to enable concurrent communication of at least two radio frequency (RF) signals associated with at least two different RATs. Specifically, the multi-RAT ET amplifier apparatus includes an ET integrated circuit (IC) (ETIC) and a distributed ETIC (DETIC) configured to generate respective ET voltages for amplifying the two RF signals. In addition, the DETIC can be configured to utilize certain circuit(s) in the ETIC to help reduce a footprint of the DETIC. By amplifying the two different RF signals based on the respective ET voltages and sharing certain circuit(s) between the ETIC and the DETIC, it may be possible to improve overall efficiency and heat dissipation in the multi-RAT ET amplifier apparatus concurrent to reducing the footprint of the DETIC.

Abstract: Envelope tracking power amplifiers with advanced gain shaping are provided. In certain implementations, a power amplifier system includes a power amplifier that amplifies a radio frequency (RF) signal and an envelope tracker that controls a voltage level of a supply voltage of the power amplifier based on an envelope of the RF signal. The power amplifier system further includes a gain shaping circuit that generates a gain shaping current that changes with the voltage level of the supply voltage from the envelope tracker. For example, the gain shaping circuit can include an analog look-up table (LUT) mapping a particular voltage level of the supply voltage to a particular current level of gain shaping current. Additionally, the gain shaping circuit biases the power amplifier based on the gain shaping current.

Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases.

Abstract: A receiver includes an amplification block supporting carrier aggregation (CA). The amplification block includes a first amplifier circuit configured to receive a radio frequency (RF) input signal at a block node from an outside source, amplify the RF input signal, and output the amplified RF input signal as a first RF output signal. The first amplifier circuit includes a first amplifier configured to receive the RF input signal through a first input node to amplify the RF input signal, and a first feedback circuit coupled between the first input node and a first internal amplification node of the first amplifier to provide feedback to the first amplifier.

Abstract: In certain aspects, an amplifier includes a first transistor including a gate, a drain, and a source, wherein the gate of the first transistor is coupled to a first input of the amplifier. The amplifier also includes a second transistor including a gate, a drain, and a source, wherein the gate of the second transistor is coupled to a second input of the amplifier. The amplifier further includes a first signal path coupled between the first input of the amplifier and the source of the second transistor, a second signal path coupled between the second input of the amplifier and the source of the first transistor, a first load coupled to the drain of the first transistor, and a second load coupled to the drain of the second transistor.

Abstract: Certain aspects of the present disclosure are directed to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element, wherein the first inductive element is coupled in series with the third inductive element. In certain aspects, the circuit also includes a first switch coupled in parallel with the third inductive element, a capacitive element coupled in parallel with the fourth inductive element, wherein a notch is formed at least by the capacitive element and the fourth inductive element, the notch circuit coupled in series with the second inductive element, and a second switch coupled in parallel with the fourth inductive element.

Abstract: A method and apparatus for receiving reduced voltage swing signals is disclosed. A first amplifier may generate a first intermediate signal based on a difference between voltage levels of a first and second input signals, and a second amplifier may generate a second intermediate signal based on a difference in the voltage levels between the second and first input signals. A regenerative amplifier may increase a difference in the voltage level of the first and second intermediate signals using regenerative feedback and the voltage levels of the first and second input signals. A latch circuit may generate first and second output signals using the first and second intermediate signals.

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: One disclosure of the present specification provides a wireless device for supporting a first band for cellular communications and a second band for D2D communications. The wireless device may comprising: a main antenna; a first RF chain configured to process a first transmission signal and a second transmission signal wherein the first and second transmission signals are to be transmitted via the main antenna using uplink bands of the first and second bands respectively; a second RF chain configured to process a first reception signal, wherein the first reception signal is received via the main antenna using an uplink band of the second band; a third RF chain configured to process a second reception signal, wherein the second reception signal is received via the main antenna using a downlink band of the first band.

Abstract: An amplifier has an input port for receiving an input signal and an envelope port for receiving an envelope signal indicative of an envelope of the input signal, and an output port for delivering an amplified signal. The amplifier has a first transistor and a second transistor. A first biasing circuit is coupled to the envelope port and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage is coupled to the input port for receiving the input signal, to the first biasing circuit for receiving the first bias voltage, and to the gate of the first transistor. A second biasing circuit is coupled between the envelope port and the gate of the second transistor, and is arranged to generate a second bias voltage dependent on the envelope signal.

Abstract: A non-saturating receiver design and clamping structure for high power laser rangefinders of especial utility with respect to pumped, monoblock lasers. The receiver comprises a photodiode and a transimpedance amplifier having at least first and second stages. The first stage comprises a field effect transistor and the second stage comprises a non-saturating, non-inverting amplification stage including a differential pair of bipolar transistors having a feedback path coupling the second stage to the input of the first stage. A clamping structure for the receiver comprises a resistor coupling a cathode of the photodiode to a first voltage input and a clamping diode also coupling the cathode to a second lower voltage input. A capacitor having a capacitance Cs couples the cathode of the photodiode to a reference voltage line, wherein the capacitance Cs is greater than the capacitance of the photodiode CD.

Abstract: A radio frequency signal amplifying system includes an amplifier having an input terminal and an output terminal, an attenuator electrically connected to the input terminal of the amplifier, a peak power detecting module configured to apply a peak power attenuation signal to the attenuator by taking a peak power level of an input signal into consideration, and an average power detecting module configured to apply an average power attenuation signal to the attenuator by taking an average power level of an output signal from the output terminal into consideration. The attenuator is configured to generate the attenuated signal to the input terminal of the amplifier by taking the peak power attenuation signal, the average power attenuation signal, or the combination thereof into consideration.

Abstract: Apparatus and methods disclosed herein perform gain, clipping, and phase compensation in the presence of I/Q mismatch in quadrature RF receivers. Gain and phase mismatch are exacerbated by differences in clipping between I & Q signals in low resolution ADCs. Signals in the stronger channel arm are clipped differentially more than weaker signals in the other channel arm. Embodiments herein perform clipping operations during iterations of gain mismatch calculations in order to balance clipping between the I and Q channel arms. Gain compensation coefficients are iteratively converged, clipping levels are established, and data flowing through the network is gain and clipping compensated. A compensation phase angle and phase compensation coefficients are then determined from gain and clipping compensated sample data. The resulting phase compensation coefficients are applied to the gain and clipping corrected receiver data to yield a gain, clipping, and phase compensated data stream.

Abstract: This document discusses, among other things, a resistance multiplier configured to provide a more specific and controllable resistance value, the resistance multiplier including an amplifier configured to control a resistance across a first transistor using a received reference resistance value and to control a resistance across a second transistor using the resistance across the first transistor and a relationship between the first and second transistors.

Abstract: A variable feedback impedance is presented capable of providing high linearity (e.g. as represented by 1P2 and 1P3) and high linear range (e.g. as represented by P1dB) when used in a feedback path of an RF amplifier in the presence of high voltage amplitudes.

Abstract: A system includes a weighting element, a transconductance circuit, a feedback loop, and an auxiliary loop. In some implementations, the transconductance circuit may accept an input and provide a first portion of an output for amplification at a variable amplification level to generate an amplifier output. The feedback loop may provide a portion of the amplifier output as a first feedback to the input. The first feedback may be associated with an impedance that may vary with the amplification level. The auxiliary loop may provide a second feedback to the input to reduce the dependence of the impedance on the amplification level.

Abstract: A power amplifier system including a composite digital predistorter (DPD) ensuring optimized linearity for the power amplifier is described. In this system, a digital-to-analog converter (DAC), an analog filter, a first mixer, and the power amplifier are serially coupled to the composite DPD. A second mixer, a receive gain block, and an analog-to-digital converter (ADC) are serially coupled to the output of the power amplifier. A DPD training component is coupled between the inputs of the composite DPD and the ADC. The composite DPD includes a memory-based DPD, e.g., a memory polynomial (MP) DPD, a memoryless-linearizing DPD, e.g., a look-up table (LUT) DPD, and two multiplexers.

Abstract: A power amplifier module includes a first amplification transistor that amplifies and outputs a radio frequency signal, a second amplification transistor that is connected in parallel to the first amplification transistor and that has a smaller size than the first amplification transistor, a bias circuit that supplies a bias voltage or a bias current to the first and second amplification transistors, a current detector circuit that detects a current flowing in the second amplification transistor, and a bias control circuit that controls the bias voltage or the bias current supplied from the bias circuit to the first and second amplification transistors depending on the detection result of the current detector circuit.

Abstract: A digital predistortion apparatus comprising: a nonlinear device; a memory effect compensator; a constant value characteristic acquirer; a cost function generator; and a coefficient updater is described.

Abstract: To set an optimum offset voltage and detect an NRZ signal with a very small amplitude. An NRZ signal amplifying device 2 includes: input-side voltage detection means 13 for detecting a high-level voltage and a low-level voltage of an input signal to the main amplifier 12; output-side voltage detection means 14 for detecting the two signals inverted relative to each other; and offset voltage control means 15 for calculating a center voltage between the detected high-level voltage and low-level voltage, setting an offset voltage at which the center voltage is the center of an appropriate input range of the main amplifier 12 to the offset circuit 11, and finely adjusting the offset voltage, such that a voltage difference between the detected two signals inverted relative to each other and a polarity change point is close to 0.

Abstract: The digital predistortion system and method with extended correction bandwidth includes a predistortion system that uses a two-box architecture based on the cascade of a memory polynomial followed by a memoryless predistortion function. The memoryless predistorter is identified offline and used to perform a coarse linearization which cancels out most of the static nonlinearity of the device under test allowing for a reduced observation bandwidth for the synthesis of the memory polynomial predistortion sub-function.

Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

Abstract: The present disclosure relates to a front-end system for a radio device, the front-end system comprising a low-noise amplifier (LNA), arranged for receiving a radio frequency input signal (RFIN) and arranged for outputting an amplified radio frequency signal (RFOUT), wherein the low-noise amplifier comprises a first differential amplifier, and a mixer (MIX), arranged for down-converting the amplified radio signal (RFOUT) provided by the low-noise amplifier (LNA) to a baseband signal (BB), by multiplying the amplified radio signal (RFOUT) with a local oscillator (LO) frequency tone, said low-noise amplifier (LNA) and said mixer (MIX) being inductively coupled.

Abstract: A pre-distortion method includes: receiving an input data; and obtaining a pre-distortion output by inputting the input data into a pre-distortion function, wherein the pre-distortion function is determined according to a following power amplifier; and multiplying a reciprocal of a pre-distortion ratio of the output of the power amplifier to the input data by the output of the power amplifier. A pre-distortion apparatus includes a receiver, a pre-distortion unit and a gain compensating unit. The receiver is utilized for receiving an input data. The pre-distortion unit is utilized for obtaining a pre-distortion output by inputting the input data into a pre-distortion function, wherein the pre-distortion function is determined according to a following power amplifier. The gain compensating unit is utilized for multiplying a reciprocal of a pre-distortion ratio of the output of the power amplifier to the input data by the output of the power amplifier.

Abstract: A signal generation apparatus includes a digital-to-analog converter, a bias stage and a class AB output stage. The digital-to-analog converter is arranged for outputting a current as an input signal. The bias stage is coupled to the digital-to-analog converter, and is arranged for generating a bias signal according to at least the input signal. The class AB output stage is coupled to the bias stage, and is arranged for generating an output signal at an output node of the signal generation apparatus according to the bias signal, wherein the output signal includes a first signal component and a second signal component, both the first signal component and the second signal component correspond to the input signal, and there is a linear relation between the output signal and the input signal.

Abstract: A low noise amplifier comprises at least one amplifying transistor (Ts1; Ts2) configured in a common source configuration to receive an input signal (RFin) at a gate terminal and provide an amplified signal at a drain terminal and at least one feedback path arranged to couple a part of the amplified signal back to the gate terminal and comprising a feedback impedance. The low noise amplifier further comprises a self-coupled step-up transformer having at least one primary winding (Lp) connected to a supply voltage (Vdd) and the drain terminal of the at least one amplifying transistor and at least one self-coupled secondary inductor winding (Lf1; Lf2) arranged in the feedback path. The low noise amplifier provides a better suppression for out-band interference and at the same time it has a wider input match bandwidth, decent conversion gain and decent noise figure without increasing power consumption.

Abstract: An ultra-wideband low-noise amplifier circuit with low power consumption includes a cascode amplifier circuit module and an output combining circuit module. The cascode amplifier circuit module receives an input signal, and outputs a first output signal and a second output signal. The output combining circuit module receives the first output signal and the second output signal, and applies respective phase shifts to the first output signal and the second output signal for reducing a phase difference between the first output signal and the second output signal, so as to obtain a combined output signal.

Abstract: A radio communication circuit includes a power amplifier configured to amplify a signal and output the amplified signal, an envelope detector configured to extract an envelope of an input signal inputted to the power amplifier, an offset generator configured to generate an offset value for a power supply voltage to be applied to the power amplifier, based on a distortion amount in an output signal from the power amplifier, and a power supply voltage modulator configured to control the power supply voltage to be applied to the power amplifier based on the envelope extracted and the offset value generated.

Abstract: The present application discloses a feed-forward amplifier device and the method thereof. The device comprises: a splitter for splitting an input signal into two portions; a non-linear amplifier for amplifying the input signal and producing inter-modulation products; a carrier canceling unit for generating pure inter-modulation products; a linear amplifier for amplifying the pure inter-modulation products; and a coupler for generating final output signal by counteracting the inter-modulation products with the amplified pure inter-modulation products; wherein the splitter and the carrier canceling unit are provided in digital base band. According to the present disclosure, pure inter-modulation products can be generated and adjusted more flexibly and more accurately in digital base band, and hence ideal output signal may be generated.

Abstract: A noise-canceling LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises a first and a second amplifier branch, each having an input terminal connected to an input terminal of the LNA circuit. The first amplifier branch comprises an output terminal for supplying an output current of the first amplifier branch and a common source or common emitter main amplifier. The main amplifier has an input transistor having a first terminal, which is a gate or base terminal, operatively connected to the input terminal of the first amplifier branch, a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor, and an output capacitor operatively connected between the second terminal of the input transistor and the output terminal of the first amplifier branch.

Abstract: A method for controlling an input signal of a power amplifier is provided. The method comprise applying CFR to the input signal to obtain a processed input signal; determining a minimum CFR threshold; comparing the peak power of the power amplifier and an allowable peak power; and if the peak power is below the allowable peak power, determining a final CFR threshold by increasing the minimum CFR threshold, or if the peak power is not below the allowable peak power, reducing the average output power until peak power reaches the allowable peak power.

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

Abstract: A power supply system includes a high-speed power supply providing a first output, operating in conjunction with an externally supplied DC source or low frequency power supply which provides a second output. A frequency blocking power combiner circuit combines the first and second outputs to generate a third output in order to drive a load, while providing frequency-selective isolation between the first and second outputs. A feedback circuit coupled to the combined, third output compares this combined, third output with a predetermined control signal and generates a control signal for controlling the high-speed power supply, based on a difference between the third output and the predetermined control signal. The feedback circuit does not control the DC source or the low frequency power supply, but controls only the high-speed power supply.

Abstract: Apparatuses and methods are provided where a predefined voltage may be applied in a feedback circuit of a voltage regulator, the feedback circuit coupling and output terminal with an adjust terminal of the voltage regulator.

Abstract: A power amplifier apparatus includes an amplifier configured to amplify an input signal converted into an analog signal, a distortion compensator circuitry configured to perform a pre-distortion process to an input signal at a second sampling rate higher than a first sampling rate at which the input signal is converted into an analog signal, a remover configured to remove a frequency component exceeding a frequency band corresponding to the first sampling rate from the input signal subjected to the pre-distortion process, a first rate converter configured to convert a sampling rate of the input signal from which the frequency component is removed from the second sampling rate to the first sampling rate, and a first signal converter configured to convert the input signal the sampling rate of which is converted into an analog signal at the first sampling rate to supply the input signal converted into the analog signal to the amplifier.

Abstract: Systems and methods are provided for adaptive linearization of an amplifier system having a plurality of heterogeneous amplifier paths. An amplifier system includes a plurality of amplifier paths, each configured to provide an amplified output signal from an input signal, and a signal combiner configured to combine the amplified output signals from the plurality of amplifier paths to provide a system output, such that the system output is a non-linear function of the amplified output signals. A monitoring system is configured to sample the system output and normalize the sampled output to a signal level associated with the input signal. A signal processing component is configured to characterize the amplifier paths via an iterative adaptive linearization process, such that the system output is linear with respect to the input signal.

Abstract: A power amplifier system includes an input operable to receive an original value that reflects information to be communicated and an address data former operable to generate a digital lookup table key. The power amplifier system also includes a predistortion lookup table coupled to the address data former and a power amplifier having an output and coupled to the predistortion lookup table. The power amplifier system further includes a feedback loop providing a signal associated with the output of the power amplifier to the predistortion lookup table and a switch disposed in the feedback loop and operable to disconnect the predistortion lookup table from the output of the power amplifier.

Abstract: An integrated circuit is described for providing a power supply to a radio frequency (RF) power amplifier (PA). The integrated circuit comprises a low-frequency power supply path comprising a switching regulator and a high-frequency power supply path arranged to regulate an output voltage of a combined power supply at an output port of the integrated circuit for coupling to a load. The combined power supply is provided by the low-frequency power supply path and high-frequency power supply path. The high-frequency power supply path comprises: an amplifier comprising a voltage feedback and arranged to drive a power supply signal on the high-frequency power supply path; and a high-frequency-path supply module arranged to provide a high frequency supply to drive the amplifier, where the high-frequency-path supply module comprises a pulse-width modulator operably coupled to the high frequency supply via a filter and arranged to provide a filtered pulse-width modulated signal to the high frequency supply.

Abstract: An analog feedback amplifier is capable of suppressing extraneous phase fluctuations and broadening a bandwidth by preventing effects of a group delay element by using an amplitude regulator 21 and a delay line 24.

Abstract: Amplifiers with boosted or deboosted source degeneration inductance are disclosed. In an exemplary design, an apparatus includes an amplifier circuit and a feedback circuit. The amplifier circuit receives an input signal and provides an output signal and includes a source degeneration inductor. The feedback circuit is coupled between a node of the amplifier circuit and the source degeneration inductor. The feedback circuit provides feedback to vary an input impedance of an amplifier including the amplifier circuit and the feedback circuit. The feedback circuit may be programmable and may be enabled to provide feedback or disabled to provide no feedback. Alternatively, the feedback circuit may always be enabled to provide feedback. In either case, the feedback circuit may have a variable gain to provide a variable input impedance for the amplifier.

Abstract: This technique relates to a receiving device, a receiving method, and a program that can demodulate transmitted signals with high accuracy. A receiving device of this disclosure includes: an amplifying unit that amplifies a received signal; an adjusting unit that adjusts gain of the amplifying unit in accordance with power of the signal; a demodulating unit that demodulates the amplified signal; and a detecting unit that detects an interval from the signal, information having the same content continuously appearing in the interval. The adjusting unit restricts the process of adjusting the gain of the amplifying unit in accordance with a result of the detection of the interval. This disclosure can be applied to receiving devices that receive broadcast signals compliant with DVB-C2 via a CATV network.

Abstract: A device and method of predistortion linearization that account for both EVM and spectral mask are disclosed. The device and method are based on transforming the predistorter optimization problem from the time domain to the frequency domain, and weighting the equations according to one or more desired objectives. One objective focuses on abiding by the spectral mask, whereas another objective focuses on improving the EVM.