Abstract: A PLL circuit used in an apparat as for reading and writing data to a disk compensates for noise which causes a false clock signal or for missing clock signals which can be caused by a scratch or smudge on the surface of the disc. The PLL circuit includes a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal and generates a phase difference signal. A charge pump receives the phase difference signal and generates an output signal, which is filtered by a low pass filter. The filtered signal is provided to a voltage controlled oscillator, which generates an oscillation output signal. A divider divides the oscillation output signal and generates the feedback signal. A time information generating circuit generates time information of the oscillation output signal, indicating the time period where it is presumed the reference signal is or should be received.

Abstract: A frequency synthesizer using a multiphase reference signal source consists of three portions: a basic phase locked loop including a variable frequency oscillator, a loop filter, a phase detector, and a frequency divider; a generating circuit including a multiphase reference signal source for providing a reference signal to the basic phase locked loop; and a frequency discriminator and phase modulator. The frequency discriminator facilitates detection of whether the main loop of the frequency synthesizer is approaching a phase locking state for a proper change of the loop bandwidth. The phase modulator is employed to change the output phase of the reference signal source in order to speed up phase locking and make it applicable to creating signals with a rapid frequency switching speed, frequency tuning capability, and fine channel resolution.

Abstract: Provided are a phase comparator (BBD) 10 for generating a pulse of a signal UP0 or DOWN0 depending on lead or lag of the falling edge of a clock recovered from DATA, relative to the edge of DATA, an overrun detector circuit 20 activating an overrun signal OVR while the circuit 20 detects that lead or lag of the falling edge of the clock exceeds &pgr;/2, a state latch circuit 30 latching a state of either a signal UP0 or DOWN0 being active before the signal OVR transits active, and a selection circuit 40 outputting the signals UP0 and DOWN0 as signals UP and DOWN while the signal OVR is inactive, and outputting the signals UP0 and DOWN0 as the signals DOWN and UP while the signal OVR is active.

Abstract: A local clock used for synchronizing events in an industrial control system may be synchronized with a master clock according to synchronization signals received at a first period. Updating of the local clock is performed on a more frequent basis than the receipt of the update signals. By using the update signals to derive an error value which is incrementally applied to the clock at a much higher rate, the maximum deviation is reduced. The system works with clocks having discrete frequency outputs by adjusting the update rate so as to effectively produce a continuously variable output frequency for the local clock over an interval equal to the update rate.

Abstract: A phase difference detection circuit of a phase locked loop (PLL) for liquid crystal display which compares a phase between external synchronous signal and an internal synchronous signal from the PLL to generate a phase difference detection signal, including: a phase comparison unit for comparing the phase between the external synchronous signal and the internal synchronous signal to generate the phase difference detection signal; an equalization pulse detection unit for detecting an equalization pulse from the external and internal synchronous signals and generating a control signal for controlling the output of the phase difference detection signal from the phase comparison unit according to an equalization pulse detection signal; an output selection unit for masking the phase difference detection signal from the phase comparison unit in an equalization period and providing the phase difference detection signal in a non-equalization period according to the control signal form the equalization pulse detectio

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: A dual bandwidth PLL based clock generation circuit that enables device execution after frequency/phase lock has been safely achieved is provided. A PLL (410) generates a PLL clock output to a divider (430), which divides the PLL clock at a system clock output. A frequency detector (415) detects frequency/phase lock of the PLL and outputs a bandwidth control signal to selectively operate the PLL (410) in a wide or narrow bandwidth mode until the system clock is stabilized to within a predefined bandwidth of a target frequency while the PLL (410) is operating in the narrow bandwidth mode. The frequency detector (415) outputs a frequency lock signal that enables execution in a CPU (440) upon detecting that the PLL (410) has safely locked to a desired output frequency. Thus, the present invention provides a stable system clock for the system prior to the CPU (440) being allowed to begin its operation, thereby substantially avoiding system failures that may result from frequency overshoot of the system clock.

Abstract: Switching a clocked device from an initial frequency to a target frequency includes locking a first phase locked loop (PLL) to the target frequency while a second PLL is driving a clock distribution network at the initial frequency. The first PLL is then substituted for the second PLL on the clock distribution network.

Abstract: A system and method for providing master and slave phase-aligned clocks. Upon a failure of a master clock signal, the system switches over to a slave clock signal in phase alignment with the master clock signal. The master clock signal is from a first clock source, while the slave clock signal is from a second clock source. The second clock source comprises a phase locked loop (PLL) including a switch, which is coupled to selectively provide a control signal to a voltage controlled oscillator (VCO). The switch may also provide a reference control voltage to the VCO. The first clock source may be on a first clock board, and the second clock source may be on a second clock board. The clock boards are preferably hot swappable. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system.

Abstract: An apparatus and method enables elements of a phase locked loop (PLL) (300). The PLL 300 includes a plurality of elements (202, 203, 204, 205). Each element produces an output signal (207, 208, 209, 116 or 117). Each element has a response time (t3−t2) defined by the difference in time between a first time (t2) at which the element is enabled and a second time (t3), occurring after the first time (t2), at which the output signal of the element reaches a steady state condition. A voltage controlled oscillator (204) of the plurality of elements, having a first response time (t3−t2) is enabled at the first time (t2) responsive to a first control signal (302). A loop divider (205) of the plurality of elements, having a second response time less than the first response time (t3−t2), is enabled responsive to the first response time (t3−t2) and a second control signal (303). The present invention advantageously provides fast lock time for the PLL (300).

Abstract: A method is disclosed for calibrating the oscillation frequency versus control voltage characteristic of a voltage controlled oscillator (VCO). The method includes establishing an oscillation frequency of the VCO at a maximum target frequency value ft_H (point Q) when the control voltage Vc equals a predetermined reference voltage Vref which lies within the operating range of the control voltage Vc, and verifying that the oscillation frequency becomes a minimum target frequency value ft_L when the control voltage Vc is changed to a value between the minimum value Vclamp_L and the reference voltage Vref. An automatically calibrated PLL circuit including a VCO is disclosed which performs a calibration to set the oscillation frequency versus control voltage characteristic of the VCO.

Abstract: A PLL frequency synthesizer has: a reference frequency generator which issues a first frequency signal; a PLL section which outputs a phase error signal based on the first frequency signal and a second frequency signal; a first filter which smoothes the phase error signal output from the PLL section according to a first reference, and which outputs a first smoothed phase error signal; a second filter which smoothes the phase error signal output from the PLL section according to a second reference, and which outputs a second smoothed phase error signal; a switch which issues, in a switching mode, the first or second smoothed phase error signal output from the first filter or the second filter; an output frequency generator which issues a second frequency signal based on the first or second smoothed phase error signal to the PLL section; and a switch controller which controls the changeover of the switch.

Abstract: A dual-mode multiple signal source/local oscillator module is capable of operating in either an independent offset mode or a common offset mode. The module includes first and second coarse frequency sources, a first signal generator coupled to the first coarse frequency source, a second signal generator, and an offset switch coupled to the second signal generator. The offset switch connects the second signal generator to either the first coarse frequency source in the common offset mode, or the second coarse frequency source in the independent offset mode. Operation of the sources in the common offset mode provides the benefits of dynamic tracking which include reduction of receiver IF phase noise and spurious signal content, improved receiver IF settling speed, and higher measurement accuracy.

Abstract: The present invention is a timebase calibration system having a phase locked loop configuration. The system includes a phase detector having a first input receiving an output of an oscillator, and a second input which can be coupled to a frequency reference. The output of the phase detector is provided through a switch to a first input of a summer, while a second input of the summer is connected to a digital to analog (D/A) converter. The output of the summer is provided to a voltage control input of the timebase oscillator. The system further includes a digital voltmeter with an input connected to the output of the phase detector. With such a system, the output of the digital voltmeter provides a voltage proportional to the frequency error between the timebase oscillator and the frequency reference standard.

Abstract: A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: Disclosed is a dual band wireless phone, such as a cellular phone for a mobile communications system, with a dual band transmitter that includes a phase-locked loop (PLL). The dual band transmitter includes first and second power amplifiers and the PLL. The first power amplifier has a first input for a first signal at a first radio frequency band, and a first output for an amplified first signal. The second power amplifier has a second input for a second signal at a second radio frequency band and a second output for an amplified second signal. The outputs of the power amplifiers are connectable to an antenna. The PLL generates two output frequency ranges and includes a voltage-controlled oscillator (VCO) which has a first output connected to the first power amplifier and generates a first signal. A frequency multiplier has an input connected to the first output of the VCO and a second output connected to the second power amplifier.

Abstract: A master and slave arrangement of processors includes a clock signal synchronization apparatus. The clock signals of two (processor) assemblies in micro-synchronous operation are only allowed to exhibit an extremely slight phase difference. A system clock signal is generated by a voltage controlled oscillator, which is fed by phase detectors with a filter at the output of each phase detector. Switches are provided between the filter output and the voltage controlled oscillator input. The phase detectors compare the system clock signal and a reference clock signal. A delay is provided at the input of one phase detector.

Abstract: The invention relates to synchronization of network elements in a network that uses master-slave synchronization. The use of the known monitoring bit MCB (Master Clock Bit) is expanded in the method so that it is transmitted all the way from the master network element, for example the mobile switching center (MSC). If one of the network elements located between the master network element and a specific slave network element, for example a base station, does not accept the received signal as the synchronization source because of its quality, the network element in question forces the MCB bit located in the signal that the element transmits further to state 1. If the transmission unit of a specific slave network element is locked to the signal which includes the MCB in state 1, or if the element is forced to revert to using the internal clock because of a fault situation of the signal, the transmission unit activates the alert.

Abstract: A PLL frequency synthesizer is provided with: a voltage detector (9) for detecting the current value of a control voltage to be applied to a voltage-controlled oscillator (6); a storage device (7) which has prestored therein a plurality of set values of control voltages corresponding to a plurality of set values of frequency dividing numbers to be set in a frequency divider (2) and which selects that one of the plurality of set values of control voltages which corresponds to the frequency dividing number set in the frequency divider; voltage value comparator (8) for comparing the current value of the control voltage detected by the voltage detector (6) and the set value of the control voltage output from the storage device (7); and a switching circuit (10) whereby a phase difference signal indicative of the phase difference between a frequency-divided signal from the frequency divider (2) and a reference frequency signal, generated by a phase comparator (3), and the output signal from the voltage value compar

Abstract: The object of the invention is to provide a lock-in process and device for a YIG-tuned oscillator which takes into account ageing and hysteresis of the YIG-tuned oscillator. This object is attained in that during a predetermined frequency change, the frequency of the YIG-tuned oscillator (1) is preset by means of a microprocessor (17) that progressively changes the current (I.sub.SP) in the main tuning coil (13) of the YIG-tuned oscillator (1) by an iterative capture routine, until the capture range (.DELTA.FM) of the switched-on frequency-locked loop, which changes with the coil current (I.sub.SP), includes the new operating frequency (f.sub.SET). The switched-on frequency-locked loop then pulls the oscillator frequency into the capture range of the PLL and the PLL locks-in the oscillator frequency to the new operating frequency (f.sub.SET). The microprocessor (17) interrupts the capture routine when a PLL-LOCK detector (11) announces to the microprocessor (17) that the new operating frequency (f.sub.

Abstract: The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.

Abstract: A method and an apparatus for controlling a radar oscillator for use in the traffic field, in particular for a car radar, for generating a linear frequency sweep. A phase-locked linearization loop generates a linear frequency sweep controlling a phase-locked oscillator loop, which has a considerably broader bandwidth than the linearization loop.

Abstract: In a phase-locked loop with reference, feedback, and error signals, the trade-off between lock-up time and power dissipation is improved by one of the following methods: supplying a continuous error signal, instead of an intermittent error signal, to a charge pump during lock acquisition; employing a half-integer frequency divider and making multiple phase-and-frequency comparisons during each reference signal cycle; employing a prescaled feedback signal and making multiple phase-and-frequency comparisons during each reference signal cycle; providing multiple feedback loops and employing a selectable number of the loops during lock acquisition; and employing multiple feedback loops with prescaling of the reference and feedback signals.

Abstract: A phase locking method and apparatus use an applied drive signal to acquire and maintain phase lock, and to prevent false locking in the presence of spurious signals. Locking signal and spurious signal components of a feedback signal within the feedback path of a phase locked loop are filtered and summed with the drive signal having a frequency offset from the loop's reference signal and an amplitude less than that of the locking signal and greater than that of the spurious signals. The summed signals are limited so that the overall phase of the limited signal is determined by the signal of highest amplitude. When the drive signal amplitude exceeds the amplitude of the filtered locking signal, the phase of the limited signal is determined by the drive signal. When the amplitude of the filtered locking signal exceeds the drive signal amplitude, the phase of the limited signal is determined by the locking signal.

Abstract: A frequency standard generator includes a voltage controlled crystal oscillator (VCXO) for generating high stability output signal, a radio wave receiver to receive a radio wave which includes a high accuracy reference time signal, a time interval measuring circuit which measures a phase difference between the reference time signal and the output signal of the VCXO; a frequency control processor which determines control data based on the phase difference data to phase lock the output signal of the VCXO to the reference time signal, a frequency deviation data generator for compiling the phase difference data to obtain frequency deviation trend data of the VCXO, and a compensation data generator for generating compensation data based on the frequency deviation trend data to compensate frequency changes in said VCXO when the reference time signal is unavailable.

Abstract: An output clock signal is generated from a selected input clock signal using a phase-locked loop (PLL). The output clock signal is used to detect failures in the selected input clock signal. If a failure is detected, a backup input clock signal is used to generate the output clock signal. In one embodiment, a clock detector has a counter that is initialized based on the selected input clock signal and incremented based on the output clock signal. The clock detector detects a failure in the selected input clock signal if (1) the counter is reset too early or too late, as determined by the counter value, or (2) the signal level in the selected input clock signal does not change within a specified time period.

Abstract: A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.

Abstract: An electronic system such as a processor or computer system includes a phase-locked loop (PLL) having a PLL parameter modification circuit. In one embodiment, the PLL parameter modification circuit may be programmed to provide one of several current control signals to a charge pump. Additionally, the PLL parameter modification circuit may be programmed to alter a loop filter transfer function by selectively changing resistance and/or capacitance values of the loop filter. Each current control signal modifies the charge pump output control voltage to a VCO differently, and, thus, modifying the current control signals to the charge pump effectively modifies the bandwidth of the PLL. In one embodiment, the PLL parameter modification circuit modifies current control signals to the charge pump by selectively inserting and removing, in accordance with programmable register bit(s) states, diode configured transistors in a current mirror configuration. Thus, a ratio of the output current of the current mirror i.e.

Abstract: A phase locked loop (PLL) circuit performs a frequency pull-in operation with a simple structure. The PLL circuit has an oscillating part which oscillates at a frequency corresponding to a control input signal and a phase comparing part which detects a phase difference between an oscillation output signal of said oscillator and an input frequency signal and produces an error signal responsive to a detection value. The PLL circuit further includes a forcible pull-in part which adds values of the error signal and a forcible pull-in signal, and provides a signal based on a result of addition as the control input signal. The forcible pull-in circuit includes a reference value generating circuit which supplies a reference value determining a unit change width of an oscillation signal of the oscillating part, and a computing part which computes a value of the forcible pull-in signal based on the reference value.

Abstract: The invention relates generally to transmission of digitized information and more specifically to a digital receiver locking device that provides a decreased lock-in time and minimizes requirements to a permissible frequency and phase matching error. Outputs of a digital phase detector 1 are coupled, respectively, to an addition input of an analog adder 2 and a first information input of a multiplexer 3 having an output coupled to a subtraction input of the analog adder 2. An output of the adder 2 is connected via a low-pass filter to an input of a voltage controlled oscillator (VCO) 5 having an output connected to a clock input of a decision unit 6 whose information input is coupled, along with a first input of the phase detector 1 and a first input of a lock state detection circuit 7, to an input of the locking device. A second input of the phase detector 1 and a clock input of the decision unit 6 are coupled to an output of the VCO 5.

Abstract: A frequency synthesizer for generating two or more output frequency ranges using a Phase Locked Loop (PLL) circuit having a single voltage-controlled oscillator (VCO). In a first embodiment, a frequency multiplier is connected to the output of the VCO. The output of the VCO and the output of the frequency multiplier are selectably fed back, depending upon which output frequency is desired. The output frequency may be taken directly from the VCO or the frequency multiplier. When the output frequency is taken from the output of the frequency multiplier, a control signal adjusts the gain of the phase detector and/or loop filter in order to compensate for the loop gain caused by the frequency multiplier. In a second embodiment, instead of adjusting the phase detector and/or loop filter gain, the values of the N and M dividers are adjusted. In a third embodiment, a frequency multiplier is connected to the output of the VCO and multiplies the output by a predetermined multiplier value.

Abstract: A frequency synthesizer includes a first counter for counting cycles of an input clock and for generating a reference output bus, a VCO for generating an output signal, a second counter for counting cycles of the output signal and for generating a VCO output bus, and a phase detector for measuring the phase error between the reference bus and the VCO output bus and for generating a control signal which is applied to the control input of the VCO. The phase detector includes circuitry for computing a corrected bus by multiplying the VCO output bus with a correction coefficient proportional to the reciprocal of the modulo count of the second counter.

Abstract: A first phase comparator 22 of digital type and a second phase comparator 32 of sampling type are provided. Near a lock phase, an output current Iout2 is fed from the second phase comparator 32 to a voltage-controlled oscillator 14 through a change-over switch 40. In other phases, an output current Iout1 is fed thereto from the first phase comparator 22. When a reference signal fs is missing, a complementing circuit 50 complements a pulse to at least the reference signal fs input to the first phase comparator 22. A noise detecting/removing circuit 60 detects and removes noise from the reference signals fs, permits the reference signals fs to be fed to the first and second phase comparators 22 and 23, and halts the operations of the two phase comparators 22 and 32 for only a predetermined period of time after the noise has been detected.

Abstract: A method and apparatus for controlling an output frequency of a phase locked loop is accomplished by determining a plurality of divider ratios which are based on an input frequency, parameters, and a desired output frequency. Each of the divider ratios is representative of a ratio between the output frequency and input frequency of the phase locked loop. Having determined the plurality of divider ratios, another determination is subsequently made to determine whether the plurality of divider ratios enable the phase locked loop to produce the output frequency within a given frequency tolerance, i.e., within an allowable error. The determination is based on whether changing the divider ratio from the one of the plurality of ratios to an adjacent ratio causes the output frequency to change more than the allowable error. If so, the plurality of ratios needs to be recalculated based on a change in the input frequency and/or one of the parameters.

Abstract: A phase locked loop (PLL) circuit includes a phase comparator that compares the phases of an input signal and a feedback signal and generates UP and DOWN pulses that are related to the phase difference. A charge pump receives the UP and DOWN pulses from the phase comparator and either charges or discharges the tuning voltage of a loop filter. The voltage controlled oscillator (VCO) provides an output signal that has a frequency that is related to the tuning voltage. A frequency divider then divides the frequency of the VCO output by a factor of N and provides the output as the feedback signal to the phase comparator. The PLL includes pre-lock circuitry that responds to an active state of a pre-lock input signal by narrowing the dynamic range of the VCO to a pre-lock range that is centered around a predetermined final frequency and that deactivates upon achieving the pre-lock range.

Abstract: A voltage controlled current source provides controlled current to a current controlled oscillator in a high frequency phase-locked loop clock generator. The voltage controlled current source receives a first control signal and a set of second control signals indicative of a phase difference between the output signal of the clock signal generator and a reference frequency. It uses those control signals to adjust the current-controlled oscillator. A level shifter coupled to the current-controlled oscillator amplifies the oscillator signals to full rail and adjusts the duty cycle at its output to 50% to produce the clock signal generator output signal.

Abstract: A phase-lock loop (PLL) has an oscillator having a plurality of operating curves. During PLL auto-trim operations, the oscillator is automatically trimmed to an appropriate oscillator operating curve for use during normal PLL operations. In particular embodiments, the PLL is a charge-pump PLL having a phase/frequency detector (PFD) that generates error signals based on comparing an input signal and a PLL feedback signal; a charge pump that generates amounts of charge corresponding to the error signals; a loop filter that accumulates the amounts of charge to generate a loop-filter voltage; and a voltage-controlled oscillator (VCO), where the VCO output signal is used to generate the PLL feedback signal. During normal PLL operations, the loop-filter voltage is applied to the voltage input of the VCO.

Abstract: A phase locked loop circuit for absorbing characteristic variations of phase comparator components beforehand in adjusting mode. With the variations thus adjusted and co-opted, any intrinsic error of the phase comparator is prevented from appearing as a phase difference upon transition from adjusting mode to normal operation mode. The scheme inhibits lock range deviations or capture range variations in normal operation mode, permitting a stable phase locked loop function.

Abstract: A phase synchronous circuit, in the process of locking an internal signal to an input signal by a PLL loop, makes a frequency of the internal signal stepwise approximate to a frequency of the input signal under digital PLL control at a first stage, and adjusting a phase under analog PLL control at a next stage, thus controlling a variable frequency oscillator at the two stages. A gain with which an analog PLL control system is burdened can be thereby reduced, and a gain of VCO may not be set larger than required even if a frequency of an output signal f.sub.out is high.

Abstract: An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

Abstract: A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.

Abstract: An apparatus and method for reducing spurious sidebands in the tuning signal of phase locked loop frequency synthesizers and phase locked loops is disclosed. The frequency synthesizer includes an oscillator, a divider, a difference circuit and a sampling circuit. The oscillator produces a variable frequency oscillator signal in response to an applied tuning signal. The divider divides the variable frequency oscillator signal by a division factor to produce a reduced frequency signal. The difference circuit receives the reduced frequency signal to produce a difference signal corresponding to the phase difference between the reference signal and the reduced frequency signal. The sampling circuit intermittently samples the difference signal in response to a timing signal to produce a tuning signal which approaches a DC characteristic. The tuning signal serves to adjust the oscillator frequency in a direction to diminish phase differences in the reference signal and the reduced frequency signal.

Abstract: A universal synchronizer for use in a variety of telecommunications systems based on direct digital phase synthesis (DDPS) include digital and analog PLLs. The synchronizer may be used for wireless, optical, or wireline transmission systems and for a wide ranges of data rates. Digital phase detectors are used in the digital PLLs for comparing the phase of the local clock f.sub.L with the phase of a respective digital reference clock, and provides a respective phase error signal. A digital phase synthesis unit receives the phase error signal and a target phase error and produces a first and a second set of control signals for driving an error driver. The error driver generates the control voltage for adjusting the frequency of a VCXO that is used for all PLLs, to lock the respective PLL. The first set of control signal generates the control voltage for the digital PLLs, and the second set of control signals generates the control voltage for the analog PLLs and for the acquisition mode of operation of all PLLs.

Abstract: A multi-band phase locked loop employing multiple, switchable voltage controlled oscillators. A single PLL is provided having a different voltage controlled oscillator for each desired frequency band of operation. The transfer function of the phase detector in the phase locked loop is switched responsive to the particular band selected so as to maintain the loop natural frequency at the same point regardless of other changes in the loop transfer function that are associated with operating at alternate frequencies, such as, but not limited to, changes in the frequency slope of the voltage controlled oscillators and changes in the division ratio of the loop divider circuit.

Abstract: A mechanism for reducing a frequency transient appearing at the output of a voltage controlled oscillator (VCO) in a frequency synthesizer when a load is connected to the VCO. In accordance with the present invention, the magnitude and direction of (a) the frequency transient and (b) the frequency deviation of the VCO signal in response to a reference input voltage may be measured, and those measurements used to generate a frequency correction voltage which would cause the VCO signal to deviate in an equal amplitude but in an opposite direction to the frequency transient. The frequency correction voltage then can be applied to the VCO when it is connected to the load so as to substantially cancel the frequency transient.

Abstract: A phase-locked loop (PLL) frequency synthesizer is described which incorporates a fractional pulse swallowing circuit. The fractional pulse swallowing circuit does not add or delete pulses but extends or shortens pulses by a fractional amount. This avoids large phase errors generated by a phase detector in the PLL. In the preferred embodiment, the PLL uses a voltage controlled oscillator (VCO) formed of a ring oscillator. The outputs of the stages of the ring oscillator are applied to input terminals of a multiplexer. The multiplexer is controlled at certain times to output a different tapped signal from the ring oscillator to effectively adjust the phase of the signal output from the multiplexer. By so controlling the multiplexer, fractional pulses are subtracted or added at intervals to either increase or decrease the average frequency of the signal output from the multiplexer. The output of the VCO is fed back to the input of a phase detector along with a reference frequency.

Abstract: An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1.DELTA.t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) .DELTA.t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized.

Abstract: A PLL frequency synthesizer for realizing high-speed operation in a frequency synthesizer having a small channel interval .DELTA.f. There are provided n-number of phase comparators, feedback frequency dividers, and reference signal frequency dividers, and a timing generating section for outputting a signal causing each of the frequency dividers to become enabled every cycle of n.times..DELTA.f. An OR gate for superposing each phase comparison signal. Each phase comparison signal is sent to a charge pump after a cycle of n.times..DELTA.f, and the reference frequency is capable of being raised to n times the channel interval .DELTA.f. Further, a control section monitors lock detection of each phase comparator, thus implementing voltage control of each phase comparison system. When the synthesizer arrives at convergence-synchronization, the power sources to all systems are turned OFF except for the phase comparison system initiating the lock signal.

Abstract: A phase-locked loop includes a switched phase detector, a loop filter and an oscillator connected in series, as well as a device for technology compensation, in particular a course control device. An operating point is adjusted during a starting phase of the phase-locked loop through the use of the course control device in such a way that the damping and natural frequency of the phase-locked loop is independent of fluctuations in technology parameters.