Abstract: Techniques for mitigating VCO pulling are described. In an aspect, VCO pulling may be mitigated by (i) injecting an oscillator signal, which is a version of a VCO signal from a VCO, into a transmitter and (ii) using coupling paths from the transmitter to the VCO to re-circulate the oscillator signal back to the VCO. In one design, an apparatus includes a VCO and a coupling circuit. The VCO generates a VCO signal at N times a desired output frequency. The coupling circuit receives an oscillator signal generated based on the VCO signal and injects the oscillator signal into a transmitter to mitigate pulling of the frequency of the VCO due to undesired coupling from the transmitter to the VCO. The apparatus may include a phase adjustment circuit that adjusts the phase of the oscillator signal and/or an amplitude adjustment circuit that adjusts the amplitude of the oscillator signal.

Abstract: In one embodiment, a voltage-controlled oscillator is provided having an output signal whose frequency is responsive to a tuning signal and is independent of amplitude of oscillation. The voltage-controlled oscillator includes: a plurality of differential inverter stages coupled to form a loop, each differential inverter stage having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a feedback signal; and a control circuit configured to generate the feedback signal responsive to a reference signal such that an amplitude of the output signal is independent of the tuning signal and depends on the reference signal, and the frequency of oscillation is decoupled from the amplitude of oscillation.

Abstract: Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.

Abstract: Provided are a PLL apparatus for an OFDM system having variable channel band and an operating method thereof. The PLL apparatus includes a frequency divider for dividing an oscillating signal; a phase detector for detecting a phase difference between a reference signal and the divided oscillating signal from the frequency divider and outputting the phase difference signal; a variable loop filter for filtering a phase difference signal outputted from the phase detector; a voltage control oscillator for outputting the oscillator signal to the frequency divider according to the voltage control signal filtered from the variable loop filter; and a variable loop filter controller for varying a filtering band of the variable loop filter according to each of the channel bands.

Abstract: A reference voltage generator and a method for generating a reference voltage for a logic device using the reference voltage generator is provided. The voltage reference generator includes a ring oscillator having a plurality of logic gates and a phase/frequency detector. A first reference voltage is generated on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator. A second reference voltage is generated on the basis of a voltage swing of the oscillator circuit. Both reference voltages can be applied to the plurality of logic gates of the ring oscillator such that a constant delay is created through each logic gate of the logic device.

Abstract: A gain control system comprises a reference stage, a bias replication stage, an operational amplifier, an automatic gain control block, a gain stage, and a crystal oscillator in one embodiment. A negative feedback loop is formed by portions of the operational amplifier, the replica biasing stage, the gain stage, and the automatic gain control stage. The negative feedback loop operatively controls an amplitude of oscillation in the crystal oscillator. The automatic gain control block produces output currents at reference levels in proportion to an input current source. The output current reference levels provide a corresponding yet independent scaling of currents in the bias replication stage and the gain stage. By the scaling capabilities provided a high common mode of voltage is provided between the crystal oscillator and the voltage reference section while stable oscillating characteristics are provided over a broad frequency range.

Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.

Abstract: Provided is an LC resonance voltage-controlled oscillator (VCO) used for a multi-band multi-mode wireless transceiver. In order to generate a multi-band frequency, a capacitor bank and a switchable inductor are included in the LC resonance voltage-controlled oscillator. The LC resonance voltage-controlled oscillator employs an adjustable emitter-degeneration negative resistance cell in place of tail current sources in order to compensate for non-uniform oscillation amplitude caused by the capacitor bank and prevent the degradation of a phase noise due to the tail current sources.

Abstract: A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.

Abstract: A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

Abstract: The present invention relates to a phase-locked loop for frequency synthesis, which has a memory for a control value for the controllable oscillator of the phase-locked loop, which is connectable via a first switch to the control input of the controllable oscillator and is implemented to output a stored control value, and whose frequency divider is connectable at its output via a second switch to the reference oscillator.

Abstract: An oscillation frequency control part includes a voltage-to-current converting circuit converting an input voltage to a current having a value corresponding to the input voltage, and outputting a current in proportion to the current obtained from the voltage-to-current converting circuit. An oscillating circuit part includes a ring oscillator, wherein a current in proportion to the output current of the oscillation frequency control part flows through the ring oscillator so that the oscillation frequency in the ring oscillator is controlled by the output current of the oscillation frequency control part. The voltage-to-current converting circuit has linear voltage-to-current conversion characteristics in a predetermined range of the input voltage including a ground potential.

Abstract: An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention. The multi-mode loop filter includes, in one embodiment, selectable resistance circuitry for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values and selectable capacitance circuitry for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values.

Abstract: In one embodiment, a voltage-controlled oscillator is provided having an output signal whose frequency is responsive to a tuning signal and is independent of amplitude of oscillation. The voltage-controlled oscillator includes: a plurality of differential inverter stages coupled to form a loop, each differential inverter stage having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a feedback signal; and a control circuit configured to generate the feedback signal responsive to a reference signal such that an amplitude of the output signal is independent of the tuning signal and depends on the reference signal, and the frequency of oscillation is decoupled from the amplitude of oscillation.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: In the current-controlled oscillator performing an oscillation frequency control by using a differential amplifier circuit, resistors are inserted to each current path of a differential pair of the differential amplifier circuit, and thereby an inclination of output currents Ia, Ib of a differential pair is small in the linear line region. Further, by setting a reference voltage applied to a base of a transistor of one side of the differential pair lowly, the linear region is shifted to low voltage side, and thereby a saturation region of the low voltage side is not occurred. Moreover, when a comparison result of a phase of an output signal of the current-controlled oscillation circuit and a reference signal is converted to an oscillation frequency control voltage Vtune, by limiting an upper limit voltage of the Vtune by an output of a regulator in stead of a positive voltage power source Vcc of common circuit, the Vtune does not move to a saturation region upper than the linear region.

Abstract: A method and apparatus for providing a high speed buffer with high gain bandwidth and rail-to-rail operation is disclosed. Resistor-capacitor (RC) filters are added in current mirrors that are in the signal path. The effect of these filters is to create a frequency-dependent impedance that extends the gain bandwidth of the circuit.

Abstract: Method and system are disclosed for automated calibration of the VCO gain in phase modulators. The method and system of the invention comprises synthesizing, in a phase modulator, a signal having a given output frequency using a controlled oscillator having a frequency control input, a modulation input, and a feedback loop. A frequency control signal is applied to the frequency control input, and gain variation of the controlled oscillator is compensated for outside of the feedback loop via the modulation input. The method and system of the invention may be employed in any telecommunication system that uses phase and amplitude modulation, including EDGE and WCDMA systems.

Abstract: A communications system using a phase locked loop employing two-point modulation is disclosed. The phase locked loop further includes a master oscillator having an output operably coupled to a first input of the phase detector; a slave oscillator having an output operably coupled to a second input of the phase detector, and a forward-gain-adaptation module having a first input operably coupled to the raw-error terminal of the phase detector.

Abstract: A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.

Abstract: In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.

Abstract: A circuit for preventing a system malfunction in a semiconductor memory includes an oscillating circuit generating an oscillating clock signal by receiving an oscillating signal, a system clock generator generating a system clock signal by receiving the oscillating clock signal, and a malfunction preventing unit resetting an inner system by sensing an amplitude variation of the oscillating signal wherein the amplitude variation is caused by noise.

Abstract: Stereo recovery circuitry for a digital receiver is disclosed that provides increased accuracy and efficiency in recovering stereo signal information from transmitted stereo signals. The stereo decoder includes a digitally controlled oscillator that recovers a pilot tone signal from transmitted stereo signal information. By processing demodulated stereo signals on the digital side and digitally controlling the oscillator, the stereo decoder has increased efficiency and accuracy. In one embodiment, the oscillator may be a phase-locked-loop having a loop filter and an amplitude stabilized tunable resonator. Additional circuitry is disclosed for utilizing the pilot tone signal to recover left and right channel signal information from the demodulated stereo signals.

Abstract: The multiple fractional division frequency synthesizer includes a frequency generator, a voltage-controlled oscillator, a programmable variable N-divider, a phase comparator, an integration and filter circuit, a time window generator, a weighted current source, a phase accumulator, and a charge-pump circuit including plural transistors. The current source is connected to the charge-pump circuit to directly switch currents over to the emitter of one or more of the plural transistors of the charge-pump circuit.

Abstract: A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.

Abstract: A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal. A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block.

Abstract: A phase locked loop circuit and method that substantially decouples control of the phase/frequency and the amplitude of the oscillation output such that the frequency of the oscillation can be controlled independently of the amplitude. The phase locked loop circuit comprises a phase/frequency control loop and an amplitude control loop wherein both loops control an oscillator that oscillates at a certain frequency in response to a phase/frequency control signal generated by the phase/frequency control loop. In addition, the oscillation amplitude is determined by an amplitude control signal generated by the amplitude control loop. As with conventional circuits of this type, a parasitic gain is coupled from the amplitude control loop into the phase/frequency control loop, thereby causing interference between the loops that leads to stability problems.

Abstract: A phase locked loop for a voltage controlled oscillator includes a phase comparator receiving at its inputs a reference frequency signal and a frequency signal from the oscillator, and supplies logic values to command a charge pump. A charge re-injection circuit receives one of the inputs of the comparator and supplies a logic value to command the charge pump. The loop further includes a detector with a threshold value for a current representative of the current supplied by the charge pump. A logic output from the detector is applied to the charge re-injection circuit so that the duration of the charge re-injection is limited.

Abstract: A circuit and/or method comprising an oscillator circuit, a pulse detection circuit and a control circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The pulse detection circuit may be configured to generate a detect signal in response to the output signal. The control circuit may be configured to generate the second control signal in response to said detect signal.

Abstract: A tuning circuit includes an oscillator that receives an oscillating input signal and a control signal, and generates an oscillating output signal. The control signal is obtained from a frequency control circuit that compares the phases of the oscillating output signal and a reference signal. The control signal controls the transconductance of a transconductance element in the oscillator, thereby controlling the oscillator output frequency. The oscillating input signal is obtained from an amplitude control circuit that detects an amplitude limit of the oscillator output. The oscillator output amplitude is responsive to the oscillating input signal. Frequency control and amplitude control in this tuning circuit are mutually independent, so their respective control loops remain stable under all frequency and amplitude combinations.

Abstract: A device for suppressing spurious signals generated by a fractional-N synthesizer. The fractional-N synthesizer generates an output frequency where an underlying PLL circuit uses a frequency divider for dividing the output frequency by a frequency-division ratio to obtain a comparison frequency and performs phase-comparison operations between a reference frequency and the comparison frequency to control the output frequency. The output frequency is changed by a frequency interval smaller than the reference frequency by making a temporal change to the frequency-division ratio once in every predetermined number of cycles.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select desired loop gain.

Abstract: A method for correcting an amplitude error between an I signal and a Q signal which are outputted from a quadrature detector including a first multiplier for multiplying a reference signal and a measured signal, a first integrator for smoothing the output of the first multiplier to generate the I signal, a 90-degree phase shifter for generating an auxiliary reference signal from the reference signal, a second multiplier for multiplying the auxiliary reference signal and the measured signal, and a second integrator for smoothing the output of the second multiplier to generate the Q signal. The method includes the step of inputting the auxiliary reference signal, instead of the reference signal, to the first multiplier to obtain a first output signal and inputting the reference signal, instead of the auxiliary reference signal, to the second integrator to obtain a second output signal.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. An FM input signal including the carrier wave is supplied to a phase detector in the phase locked loop. The output of the phase detector is filtered and used to generate a signal for use in controlling a voltage controlled oscillator having an output also connected to the phase detector. The phase locked loop is tuned to a selected carrier wave frequency and a variable gain setting of a variable gain circuit in the phase locked loop is selected to select a desired loop gain. The signal for use in controlling the voltage controlled oscillator is varied by the variable gain circuit to alter the amount by which the frequency of the output of the voltage controlled oscillator changes in relation to a given output of the phase detector. The variable gain setting is selected to select a required bandwidth for demodulation.

Abstract: A circuit for causing an element to produce a substantially linear response to an input signal comprising an element for providing a response, a transistor oscillator circuit for providing an electrical output signal of variable amplitude to excite the element in response to the input signal, the transistor oscillator circuit normally causing the electrical output signal to vary non-linearly with respect to the input signal, and microprocessor means for correcting the non-linear relationship between the input signal and the electrical output signal to thereby cause the electrical output signal to vary substantially linearly with respect to the input signal when the input signal is applied to the microprocessor means.

Abstract: PLL apparatus for generating an oscillatory signal phase locked to a component of a further signal comprises a variable oscillator for generating the oscillatory signal and a source of the further signal. A phase detector responsive to the oscillatory signal and to the component of the further signal, provides a phase error signal which is coupled to the variable oscillator via a limiter. Circuit means are provided for controlling the limiting level of the limiter. The dual limiting substantially improves the loop noise tolerance and reduces the loop sensitivity to occasional phase reversals of the component of the further signal. Additional enhancements to loop stability and noise immunity are provided by an unlock detector which detects and totalizes phase rotations in a selected area of a phase plane and by a phase wrap detector which maintains a lock indication during phase angle wrapping.

Abstract: A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Abstract: A phase lock loop (PLL) is configured as a frequency synthesizer with a first programmable frequency divider placed in the input signal path and a second programmable frequency divider located between the output of an current controlled oscillator (ICO) and the second input of a phase detector. A charge pump receives control pulses from the phase detector to generate first and second currents to control the ICO. The control currents are low-pass filtered and summed before application to the ICO. To improve loop stability, the summation current to the ICO is duplicated and used to control the bias on the charge pump. With proper biasing, first and second control currents become dependent on the second programmable divider ratio and maintain the unity gain bandwidth of the loop constant at a value much less than the digital sampling rate.

Abstract: A clamp circuit for use in a phase-locked loop clock circuit, the phase-locked loop including a phase detector with inputs for reference clock signal and oscillator signal, a loop filter with an input connected to the phase detector, and a voltage-controlled oscillator with an output connected to the phase detector, the clamping circuit connected between an output of the loop filter and an input of the voltage-controlled oscillator, the clamping circuit connected between the loop filter and the voltage-controlled oscillator. The clamping circuit selectively provides, under the control of a clamping signal either a path for the loop through the clamping circuit or clamping the input of the voltage-controlled oscillator to varying potential. The varying potential is provided by a resistor capacitor network. When the loop is closed the capacitor is charged to an average of the loop control voltage for the oscillator.

Abstract: A high reliability phase-locked loop (PLL) is disclosed having a hyperactivity detection and correction circuit (HDC) to oversee the oscillator and the phase and frequency detector (PFD), and having a PFD reset gate that performs the required logic function to reset the PFD while not being vulnerable to an internal PFD race condition that plagues prior art phase-locked loop circuits. The HDC senses the oscillator control and signals an oscillator reset should the oscillator control rise to an abnormally high level above a predetermined limit while the PFD is not detecting the feedback signal. The oscillator reset signal then slowly propagates through an asymmetrical delay line and resets the oscillator control to a predetermined reset state. While the oscillator control is being reset, the HDC continues to monitor the oscillator control, and de-asserts the oscillator reset when the oscillator control drops to the predetermined reset state.

Abstract: A dual loop phase locked circuit is disclosed in which a first loop includes a phase detector, a filter, and a VCO; as a second loop includes a sweep voltage generator, a compensation circuit, and the filter of the first loop. Due to the compensation circuit, the VCO accurately tracks a signal from the sweep voltage generator, even though the filter has an electrical parameter that drifts with time and/or age and/or component selection.

Abstract: An actively biased oscillator (200) includes a set of current sensing components (214,216) for sensing the amount of current flowing into the first terminal of the amplifier; and a differential amplifier (212) responsive to the current sensing components for automatically adjusting the amount of current flowing into the second terminal of the amplifier.

Abstract: A multiple frequency scan oscillator control system includes a phase locked loop operative upon a scan oscillator to provide phase and frequency synchronization thereof to a periodic reference signal. A static phase error correction is operative to provide adjustment of the free-running or static frequency of the scan oscillator. An error amplifier includes a pair of intercoupled differential amplifier configurations one having a constant current source and the other having a frequency dependent current source which responds to a frequency dependent bias current to alter amplifier gain. A threshold detection circuit includes a differential amplifier pair coupled to a pair of switching circuits for establishing a threshold action in response to system error voltage to indicate large magnitude error voltages and signal the need for free-running frequency adjustment of the oscillator.

Abstract: A phase-lock loop includes a scaling element whose scale factor is adaptively adjusted as a function of the value of a state variable in the loop--illustratively, the magnitude thereof. That function is such that, after the adjustment has been made, the value taken on by the state variable is within a predetermined range. In particular embodiments, the scale factor and the state variable are simultaneously adjusted reciprocally, rather than simply adjusting only the scale factor and waiting for the normal operation of the loop to change the state variable, advantageously minimizing any transient degradation in loop performance that may occur as a result of the adjustment.

Abstract: The invention provides an arrangement for reducing waveform errors such as errors in phase or amplitude in output pulses produced by pulsed power output devices such as klystrons by generating an error voltage representing the extent of error still present in the trailing edge of the previous output pulse, using the error voltage to provide a stored control voltage, and applying the stored control voltage to the pulsed power output device to limit the extent of error in the leading edge of the next output pulse.

Abstract: A clock signal producing circuit for a data storing and reproducing system in which a reference clock signal having a predetermined frequency is generated, a first sync-signal detection signal is generated when the time between two adjacent pulses in the input signal which is measured by the reference clock signal becomes equal to the predetermined reference value, the clock edge pulse is separated from the input signal using the first sync-signal detection signal and then outputted, and a reproducing clock signal having a predetermined frequency coinciding with the generating timing of the separated clock edge pulse is generated.

Abstract: A regenerating device for regenerating a signal from a composite input signal, provided with a phase-locked loop comprising a first phase comparison circuit 1, a first low-pass filter 2 connected to the output thereof and a controlled oscillator 3. The control input of said oscillator 3 is connected to the output of the low-pass filter 2 while its quadrature output 3a is connected to one input of the phase comparison circuit 1. The input of the phase comparison circuit 1 forms the input of the regenerating device and the in-phase output of the oscillator 3 the output. Furthermore a second phase comparison circuit 4 and a second low-pass filter 5 connected thereto are provided, which correspond to the first phase comparison circuit and the first low-pass filter respectively. The input of the phase-locked loop and the in-phase output 3b of the controlled oscillator 3 are connected to the inputs of the phase comparison circuit 4.

Abstract: A phase-locked loop circuit (PLL) to which a phase-synchronization signal is intermittently supplied, both of the natural angular frequency of the PLL and the damping factor of the same are so determined as to prevent a phase difference produced at the next sampling point from exceeding the linear property range of a phase comparator even when the extraneous electrical disturbance enters the PLL. In addition, when the level of a clock control signal supplied to a variable frequency oscillator which varies the clock signal of the PLL in phase and frequency exceeds a predetermined value, the level of the clock control signal is limited to the predetermined value. As a result, it is possible to prevent the output signal of the phase difference from having any discontinuity.

Abstract: A circuit for generating a driving signal for an ultrasonic vibrating element including a voltage controlled oscillator for generating an oscillation signal which is supplied to the ultrasonic vibrating element as the driving signal, a phase difference detector for detecting a phase difference between the voltage and the current of the driving signal to produce a control voltage corresponding to the detected phase difference, said control voltage being applied to a control input of the voltage controlled oscillator, a comparator for comparing the control voltage from the phase difference detector with a reference voltage to generate an output signal when the control voltage exceeds the reference voltage, and a voltage setter for responding to the output signal to reset the oscillation frequency of the voltage controlled oscillator to a predetermined frequency which is lower than the optimum resonance frequency so that the ultrasonic vibrating element is energized in the most efficient manner.