Abstract: A method and apparatus for selecting an optimum VCO from an array of VCOs is disclosed. Each VCO in the array has an output range and a limit. In one embodiment, a search set of VCOs is designated as all VCOs in a system. The limit is compared to a tuning value which corresponds to a desired calibration frequency. The comparison divides the array of VCOs into a searched set and a non-searched set. The process is repeated until the non-searched set comprises only one VCO. In another embodiment, the VCOs are ordered such that there is a middle VCO. A VCO in the middle of the array is selected. The limit of the middle VCO is compared to a tuning limit. Based on the comparison, another VCO is selected. The process repeats N times, where N is the logarithm, base 2, of the total number of VCOs to be searched. at the end of the search, an optimum VCO will be found.

Abstract: Various systems and methods for clock generation are disclosed herein. As just one example, a system for clock generation is disclosed that includes a phase/frequency control circuit that provides a feedback control; a multi-range selector circuit that receives the feedback control; and a controlled oscillator that provides an output with a phase and frequency at least in part governed by the multi-range selector circuit and the feedback control. In various instances of the aforementioned embodiments, the controlled oscillator is a ring oscillator relying on inherent capacitance.

Abstract: A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

Abstract: Disclosed is a system and method for providing an oscillating signal of relatively precise frequency without using a signal provided by a crystal as a reference. Disclosed is a feedback oscillator circuit configured to output an oscillating signal having a frequency defined by a reference signal. The oscillating signal can be sent to one or more circuits including at least one frequency sensitive element. The frequency sensitive element produces an output signal which depends on the frequency of the oscillating signal. A controller controls the reference signal in order to cause an attribute of the output signal to have a value within a desired range.

Abstract: Exemplary embodiments of the invention provide a system, method and apparatus for spread spectrum functionality for a free-running, reference harmonic oscillator. In an exemplary embodiment, an apparatus comprises a reference oscillator adapted to provide a reference signal having a reference frequency; and a spread spectrum controller adapted to control the reference oscillator to generate a spread-spectrum reference signal at a plurality of different reference frequencies during a predetermined or selected time period. An exemplary apparatus may also include a coefficient register adapted to store a plurality of coefficients and a plurality of controlled reactance modules responsive to a corresponding coefficient of the plurality of coefficients to modify an amount of reactance effectively coupled to the reference oscillator.

Abstract: In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider. The TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.

Abstract: The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

Abstract: A radio frequency (RF) receiver for receiving transmissions of different modulations includes cycling between a first mode for receiving transmissions of a first modulation that occurs frequently and a second mode for receiving transmission of a second modulation that occurs infrequently. The example RF receiver is cycled between a first modulation for receiving a frequency shift keyed (FSK) transmission from a tire pressure monitoring (TPM) system and a second modulation for receiving an amplitude shift keyed (ASK) transmission from a remote keyless entry (RKE) system. The RF receiver cycles between different modulations to detect the most frequent FSK modulated transmissions while also detecting and receiving the relatively infrequent ASK modulated RKE transmissions without an undesirable delay.

Abstract: The digital controlled oscillator includes a variable capacitance section having a first capacitor array of a plurality of first variable capacitors and a second capacitor array of a plurality of second variable capacitors, and generates a signal having an oscillation frequency corresponding to the capacitance value of the variable capacitance section. The first capacitance change amount in the individual first variable capacitors is a value obtained by multiplying the second capacitance change amount in the individual second variable capacitors by an integer equal to or more than 2, and the number of second variable capacitors is equal to or more than a value obtained by subtracting 1 from the integer equal to or more than 2.

Abstract: The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of a charge pump and provides a signal to a digital control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). The analog comparator with the digital control circuit changes the VCO loads to select the best VCO range to achieve the incoming signal frequency lock. A single PLL with the VCO load selection method disclosed, with use of built-in hysteresis, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges to be covered in a stable fashion. This enables frequency locking of the PLL over a wide range of frequencies with a small die size and low power consumption.

Abstract: An apparatus includes a phase locked loop (PLL). The phase locked loop (PLL) has coarse tuning (CT), fine tuning-integer (FT-i), fine tuning fractional (FT-f), frequency modulator tuning-fractional (FMT-f), and narrowband (NB) modes of operation.

Abstract: Provided is an oscillating apparatus that includes a plurality of variable frequency oscillators, each of which is provided in correspondence with a different oscillating band from one another; and a selection section that selects an oscillating signal that is from a variable frequency oscillator provided in correspondence with a designated oscillating band, from among the plurality of variable frequency oscillators, and outputs the selected oscillating signal, where the selection section includes a plurality of selectors connected in a tree structure, each selector outputting a selected one of inputted two or more oscillating signals, and each of the plurality of variable frequency oscillators is connected to a selector positioned at an end of the tree structure of the plurality of selectors.

Abstract: A design structure for an integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Abstract: Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.

Abstract: A fractional-N divider receives an input signal and supplies a divided signal divided in accordance with an integer divide control signal determined from a divide ratio. A phase interpolator is coupled to the fractional-N divider to adjust a phase of the divided signal according to a fractional portion of the divide ratio. The apparatus, responsive to a request for a frequency adjustment of the generated signal in a programmable number of steps, is configured to adjust the frequency of the generated signal from a beginning frequency to an ending frequency in the programmable number of steps by adjusting the supplied divide ratio at each step.

Abstract: A multi-band wireless transceiver having a plurality of signal-processing paths, and further having a function of making wireless communication through a plurality of frequency bands by selecting one of the signal-processing paths, includes a band identification circuit for identifying a frequency band, the band identification circuit identifying a frequency band in dependence on a frequency-band information received from a controller which controls an operation of the multi-band wireless transceiver, and selecting one of the signal-processing paths in accordance with the identified frequency band.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages.

Abstract: A timestamp-based all digital phase locked loop is utilized for clock synchronization for Circuit Emulation Service (“CES”) over packet networks. The all digital phase locked loop at a CES receiver includes a phase detector, a loop filter, a digital oscillator and a timestamp counter. The all digital phase locked loop enables the CES receiver to synchronize a local clock at the receiver with a clock at a CES transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps. The phase detector is operable to compute an error signal indicative of differences between the timestamps and a local clock signal. The loop filter is operable to reduce jitter and noise in the error signal, and thereby produce a control signal. The digital oscillator is operable to oscillate at a frequency based at least in-part on the control signal, and thereby produce a digital oscillator output signal.

Abstract: In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.

Abstract: A wireless communication device is disclosed wherein the voltage swing of a local oscillator (LO) signal is controlled to prevent overstressing semiconductor devices in a mixer to which the LO signal is supplied. A quadrature divider supplies the LO signal to the mixer. Digital calibration methodology controls the current that the quadrature divider draws from a power supply to set the voltage swing of the LO signal that the quadrature divider generates.

Abstract: A plurality of varactors are coupled via a first electrode to a shared terminal that in turn can operably couple to a source of control voltage. A second electrode for each varactor couples to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.

Abstract: A controlled oscillation module includes a current source, an inductive load, a switching transistor section, and an adjustable parameter module. The switching transistor section is operably coupled to the current source and to the inductive load to convert a control signal into an output oscillation in accordance with an adjustable operating parameter of the controlled oscillation module. The adjustable parameter module is operably coupled to produce the adjustable operating parameter.

Abstract: A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.

Abstract: An integrated tunable resonance circuit is provided for providing a high-frequency output signal with a frequency dependent on a control signal, comprising a parallel resonance circuit with a first inductive element and an output for providing the high-frequency output signal, a switching unit with a controlled path, and a control terminal for switching between states, whereby the switching unit is designed to exhibit a predominantly capacitive behavior in a first state and a predominantly resistive behavior in a second state, whereby the resonance circuit is designed to drive the control terminal of the switching unit as a function of the control signal. The resonance circuit has a second inductive element which can be mutually coupled to the first inductive element, whereby the controlled path is connected parallel to the second inductive element. The invention relates furthermore to a voltage-controlled oscillator and to an integrated circuit.

Abstract: A multi-frequency signal source and a method for providing a multi-frequency signal source with phase-lock capability are provided. The multi-frequency signal source includes a plurality of single-section filters each configured to provide oscillation of a signal at a different frequency. The multi-frequency signal source further includes a phase lock component providing a reference signal to control the oscillation at each of the frequencies.

Abstract: An RC oscillation circuit and method capable of adjusting an oscillation frequency includes: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

Abstract: A programmable varactor apparatus may include multiple binary weighted varactors controlled by multiple digital varactor bits. A programmable varactor apparatus may include a plurality of binary weighted varactors, and a control to selectively disable one or more of the plurality of binary weighted varactors to decrease an effective capacitance of the programmable varactor apparatus. A method for changing an effective capacitance of a programmable varactor apparatus may include providing a plurality of binary weighted varactors, and disabling one or more of the plurality of binary weighted varactors to decrease the effective capacitance of the programmable varactor apparatus.

Abstract: In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.

Abstract: A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.

Abstract: A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal.

Abstract: A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks.

Abstract: The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into.

Abstract: An oscillator includes: oscillation units (11 through 1n) outputting oscillation signals of different frequencies; a transmission line (15) to which outputs of the oscillation units (11, 12) are connected, the transmission line having a characteristic impedance corresponding to an output impedance of an output terminal (Tout); and a low-pass filter 818) connected between the transmission line (15) and the output terminal.

Abstract: Aspects of a method and system for processing signals via an oscillator load embedded in an IC package are provided. In this regard, a hybrid circuit may comprise an oscillator, and a frequency of the oscillator may be controlled via a digital control word. Furthermore, the hybrid circuit may comprise an integrated circuit bonded to a multi-layer package and at least a portion of the oscillator may be within and/or on the multi-layer package. The at least a portion of the oscillator may be fabricated in one or more metal layers of the multi-layer package. The at least a portion of the oscillator in the multi-layer package may be fabricated utilizing microstrip and/or stripline transmission line. A frequency of the oscillator may be controlled via one or more inductors and/or capacitors in the portion of the oscillator in the multi-layer package.

Abstract: Aspects of a method and system for frequency tuning based on characterization of an oscillator are provided. In this regard, a frequency of an oscillator in an integrated circuit may be controlled based on a first digital control word, a frequency of a tuned circuit may be controlled based on a second digital control word, and the second control word may be determined utilizing a mapping between the first control word and the second control word. The frequency of the oscillator and the tuned circuit may be controlled by adjusting a capacitance of the oscillator and tuned circuit, respectively. The mapping may be based on a relationship between the oscillator and the tuned circuit, such as logical and/or mathematical relationship between the capacitance of the oscillator and the capacitance of the tuned circuit and/or the relationship between the frequency of the oscillator and the frequency of the tuned circuit.

Abstract: A system and apparatus for varactor bank switching for a voltage controlled oscillator, is disclosed. Varactor bank switching involves partitioning a varactor bank switch into two anti-parallel branches, wherein each branch comprises a pass-gate circuit that is series-connected to a fixed varactor or capacitor; and maintaining an output common mode voltage of an actual oscillator signal at the varactor-side terminal of each pass-gate circuit, such that a threshold voltage of the switch transistor in the pass-gate circuit is not exceeded and the switch remains in an off-state.

Abstract: An apparatus comprising a voltage controlled oscillator, a first charge pump, a second charge pump, a switch circuit and a comparator circuit. The voltage controlled oscillator may be configured to generate an output signal oscillating at a first frequency in response to a control signal. The charge pump circuit may be configured to generate a first component of the control signal in response to a first adjustment signal and a second adjustment signal. The second charge pump may be configured to generate a second component of the control signal in response to a first intermediate signal and a second intermediate signal. The switch circuit may be configured to generate the first intermediate signal and the second intermediate signal in response to the first adjustment signal and the second adjustment signal. The comparator circuit may be configured to generate the first and second adjustment signals in response to a comparison between (i) an input signal having a second frequency and (ii) the output signal.

Abstract: The present invention discloses a dual-band voltage controlled oscillator (VCO), comprising a plurality of resonant circuits; an inductor module; a plurality of switches of current source; a buffer circuit; and a output port. The dual-band voltage controlled oscillator (VCO) according to the invention uses the current source in such two VCOs with different resonant frequencies as the switch device to combine the two VCOs and uses the common inductor module for the two VCOs to save the chip size.

Abstract: A method of generating an output of a frequency synthesizer is disclosed. The method comprises the steps of generating an output of the frequency synthesizer based upon frequency synthesizer values and a reference clock signal; receiving a command comprising a first new frequency synthesizer value; locking to a new frequency based upon the first new frequency synthesizer value; and simultaneously loading a second new frequency synthesizer value while locking to the new frequency. A circuit for generating an output of a frequency synthesizer is also disclosed.

Abstract: Methods and systems for tuning an oscillator are disclosed and may comprise dividing a desired frequency range of a delay-cell based ring oscillator into segments, and tuning the delay-cell based ring oscillator over an ultra-wide frequency range by utilizing these divided segments. The enabled segment may determine the frequency range and the oscillator may be tuned within these segments. The delay may be adjusted utilizing a negative skew technique, and may be controlled by one or more digital codes. The oscillating frequency within each segment may be adjusted utilizing a control voltage or control current. The voltage or current may be buffered and utilized as a common supply of the delay cells.

Abstract: A digitally controlled oscillator device includes a programming input, a selection input and an oscillator core with a first capacitive element which is frequency determining and programmable. The first capacitive element is coupled to the programming input that receives a first data word by which an oscillating frequency of the oscillator device is programmed with a predetermined frequency step size. The oscillator device further includes a selection unit for selecting a mode which is coupled to the selection input that receives a mode selection signal. The mode is selectable from a plurality of modes depending on the mode selection signal and each mode from the plurality of modes is characterized by a predetermined frequency step size. The digitally controlled oscillator device also includes a deattenuation amplifier.

Abstract: The invention represents a parallel and distributed approach to clock recovery based on multiple mutually phase shifted sample clock signals (åS) defining a set of orthogonal clock phases. The phase shifted clock signals are used for obtaining an input data sample representation (åU). Input data transition detection is accomplished by determining, for each one of the above clock phases, whether input data samples within a detection window associated with the respective clock phase include an input data transition vector (I). A corresponding clock selection control signal vector (I) is generated based on the input data transition vector (I) to determine a clock selection master. In order to dynamically extract an output clock signal, to control signal vector (I) is then logically combined with a representation (åS?), preferably a rotated version, of the sample clock vector (åS).

Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide LC tank circuits having an inductance and a capacitance. In addition, the circuits include a flicker noise reducing switch that is operable to selectively incorporate the capacitance such that an output of the circuit operates at a frequency based on a combination of the inductance and the capacitance.

Abstract: A variable capacitance applied to a voltage controlled oscillator includes a switch capacitance bank including a plurality of controllable capacitor paths for selectively connected between a first node and a second node in parallel; and, a switch variactor bank including a plurality of controllable variactor paths for selectively connected between the first node and the second node in parallel; wherein each controllable variactor path provides a tunable capacitance value according to an input voltage.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.

Abstract: A system and a method for self calibrating a voltage-controlled oscillator (VCO). In the system, a mode controller generates a control signal for each of an automatic band selection mode, an automatic gain tuning mode, and a phase-locking mode, from a frequency comparison result between a reference clock signal and a divided clock signal which is generated by dividing a frequency of an oscillation signal, and thereby controls the VCO, so that the VCO may generate the oscillation signal which is automatically phase-locked in a target frequency with an optimal state.

Abstract: A frequency switching method is used to make switching among a plurality of frequency signal sources each providing a specific frequency range covering multiple bands. The method includes steps of providing a target frequency data; selecting one of the frequency signal sources to output a first clock signal; generating a first frequency data according to the clock signal of the first frequency to compare with the target frequency data; outputting a second clock signal with the highest band of another one of the frequency signal sources possessing a frequency range higher than that of the selected frequency signal source when the target frequency data is greater than the first frequency data; and outputting the second clock signal with the lowest band of the selected frequency signal source when the target frequency data is smaller than the first frequency data.

Abstract: Exemplary embodiments of the invention provide a system, method and apparatus for frequency calibration of a free-running, reference harmonic oscillator. An exemplary system comprises the harmonic oscillator, a frequency divider, a comparator, and a reactance modulator. The reference harmonic oscillator includes a plurality of switchable reactance modules controlled by corresponding coefficients, and provides an oscillation signal having an oscillation frequency, which is divided or multiplied by the frequency divider to provide an output signal having an output frequency. The comparator compares the output frequency to an externally supplied reference frequency using first and second predetermined levels of discrimination, and provides first or second comparison signals when the output frequency is higher or lower than the reference frequency.