Abstract: A satellite signal reception device includes: a local signal generator that generates a signal while switching between a signal having a first local frequency corresponding to a first positioning satellite signal and a signal having a second local frequency corresponding to a second positioning satellite signal based on a reference clock signal; and a frequency converter that converts a reception signal of the first positioning satellite signal into a first intermediate frequency signal by multiplying the reception signal of the first positioning satellite signal by the signal having the first local frequency, and converts a reception signal of the second positioning satellite signal into a second intermediate frequency signal of which at least a part of a converted frequency band is in common with the first intermediate frequency signal multiplying the reception signal of the second positioning satellite signal by the signal having the second local frequency.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: The present invention provides a frequency synthesizer for a wireless communication system. The synthesizer includes an oscillator that generates an electronic signal as well as frequency dividers, frequency selectors and mixers. The signal generated by the oscillator is sequentially divided by the frequency dividers to produce a first group of frequencies, and the selectors and mixers are then capable of mixing the first group of frequencies according to instructions from control bits to produce a second group of frequencies which constitute UWB band frequencies. In this manner, the synthesizer can generate all 14 UWB band frequencies or particular UWB band groups using a single oscillator. One of the frequencies generated by the dividers can also be used as the baseband clock signal without requiring an additional frequency source.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: Multiple carrier frequencies are provided from a phase locked loop, especially closely adjacent quadrature amplitude modulated subcarriers for multiplexed data communications. A quadrature voltage controlled oscillator (VCO) and cascaded frequency dividers provide feedback to a phase comparator to lock the VCO to a reference signal. In addition to frequency divider outputs for use as subcarriers, e.g., binary division factors of the VCO frequency, a quadrature mixer multiplies and adds corresponding quadrature components at two of the frequencies, to generate a differential signal at a difference frequency. The mixer may be outside of the feedback signal path but preferably is in the feedback path to suppress noise. A polyphase filter converts the mixer output to a quadrature signal useful as a subcarrier. The technique efficiently generates sequential integer multiples of a basic frequency, such as sixteen adjacent integer multiples of a frequency reference.

Abstract: The present invention relates generally to communications, and more specifically to a method and apparatus for generating local oscillator signals used for up- and down-conversion of RF (radio frequency) signals. A major problem in the design of modulators and demodulators, if the leakage of local oscillator (LO) signals into the received signal path. The invention presents a number of highly integratable circuits which resolve the LO leakage problem, using regenerative divider circuits acting on oscillator signals which are running at a multiple or fraction of the frequency of the desired LO signal, to generate in-phase (I) and quadrature (Q) mixing signals. Embodiments of these circuits also use harmonic subtraction and polyphase mixers, as well as virtual local oscillator TM (VLO) mixing signals. VLO mixing signals are signal pairs which emulate local oscillator signals by means of complementary mono-tonal and multi-tonal mixing signals.

Abstract: A method and device are provided for producing mobile radio signals, which utilize a direct conversion receiver, at least one first and one second local oscillator and one regenerative divider for processing signals according to different mobile radio standards. For generating the intermediate frequency for transmission according to at least one of the mobile radio standards, a division by four in addition to a division by three of the oscillator frequency is also possible.

Abstract: In an exemplary application, an apparatus according to a disclosed embodiment receives a radio frequency signal and outputs an intermediate frequency signal. Rejection of image components in the intermediate frequency signal is obtained without the need to preprocess the radio frequency signal with an image reject filter. Such an apparatus may also exhibit an image rejection performance that is robust to frequency deviation of a local oscillator.

Abstract: Radio equipment enabling radio communication with frequency conversion corresponding to signals of different frequency bands is disclosed. A local oscillator signal generator included in this radio equipment having a first signal generator, a second signal generator, and a frequency synthesizer generating a local oscillator signal. A first signal having first frequency is generated in the first signal generator, and a second signal having second frequency smaller than the first frequency is generated in the second signal generator. These first and second signals are synthesized, and the local oscillator signal either having the frequency derived from adding the second frequency to the first frequency, or having the frequency derived from subtracting the second frequency from the first frequency is generated.

Abstract: A low noise sinusoidal signal at a desired output frequency is synchronised using a first variable frequency oscillator (1) and providing a feedback control loop around the first oscillator (1) to generate a feedback control signal in successive frequ comparison steps using second and third frequency reference signals (44, 42). Each of the second and third frequency reference signals are derived from a first frequency reference signal, the second frequency reference signal (44) being compared with the output frequency of the first oscillator (1) to generate a frequency difference signal (43), and said frequency difference signal ( being compared in frequency with the third frequency reference signal (42) to generate said feedback control signal for the first oscillator (1), the frequency of the third frequency reference signal (42) being equal to the difference of the frequency of the se frequency reference signal (44) and the desired output frequency.

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Abstract: The invention relates to reference handover in clock signal generation systems and similar applications. The idea according to the invention is to introduce a so-called “virtual” delay in the control loop of a PLL for the purpose of forcing the control loop to shift the phase of the PLL output clock signal, while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal, towards a predetermined target phase relation with the primary reference signal. By utilizing a virtual delay, the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained. Preferably, the virtual is introduced by superimposing an external phasing control signal in the control loop of the PLL on the output signal/input signal of a control loop element.

Abstract: An apparatus for limiting intermediate frequency variation in a multiple conversion phase locked loop includes a reference oscillator and a voltage controlled oscillator (VCO). The reference oscillator generates a first reference frequency, while the VCO generates an output frequency. The output frequency is divided by a first VCO divider and mixed with the first reference frequency to generate a first intermediate frequency. A second VCO divider also divides the output frequency and mixes it with the first intermediate frequency to generate a second intermediate frequency, which is filtered and used to control the VCO. An algorithm processor generates the division constants of the first and second VCO dividers as a function of the reference frequency and the output frequency to limit intermediate frequency variation.

Abstract: A GPS frequency converter is provided, according to the present invention, to down-convert the frequency of an incoming GPS signal. The converter includes first and second mixers, the former of which receives the incoming RF signal and a signal from a local oscillator. The local oscillator signal is increased by a factor of 98 and then subtracted from the incoming RF signal to produce a first intermediate frequency signal (IF). The first IF signal is then passed to the second mixer which subtracts the frequency of the local oscillator therefrom to produce a second intermediate frequency signal (IF). The second IF signal is passed through a limiter and output as the frequency converted signal.

Abstract: A monolithic device is shown having a number of phase locked loops (PLLs) constructed thereon. At least one of the PLLs is constructed as a multiple loop having an output of one PLL loop tied back to the feedback path of the other loop of the pair. In this manner, tight resolution can be obtained in one loop while the bandwidth of that loop is coarse. The bandwidth of the second loop is tight, thereby giving good resolution to the first loop while still avoiding the problems inherent with noise injection locking from other PLLs on the same device.

Abstract: A handheld vector network analyzer (VNA) providing a wide bandwidth test signal F.sub.O utilizing a narrowband test signal synthesizer which provides the test signal through a frequency divider or harmonic generator. With a 550-1100 MHz narrowband test signal synthesizer, a test signal F.sub.O can range from 25 MHz to 3.3 GHz. To make a tracking synthesizer operate more independent of the test signal synthesizer, a LO signal is produced using the tracking synthesizer with its phase detector input connected through a frequency divider to the output of the test signal synthesizer. Synchronous detectors are further included which provide incident and reflected IF signals to take advantage of the maximum range of an A/D converter. To better enable operation in the presence of external signals, feedback is provided from the synchronous detectors to sweep the frequency of a reference oscillator.

Abstract: The output frequency of a PLL frequency synthesizer and the output frequency of a fixed oscillator are mixed together in a mixer to produce sum and difference frequencies. The sum frequency is used as a local frequency, and the difference frequency is fed back to the PLL frequency synthesizer. In addition, the output frequency of the fixed oscillator is divided in a predetermined ratio to use it as a local frequency for the second or other subsequent frequency converting stage on the receiver or transmitter side.

Abstract: A frequency synthesizer device which comprises a combination of: an oscillator, a phase comparator, a frequency generator having an input receiving the reference frequency of value OF and N outputs, with N being a whole number between 1 and N, each output being designed to deliver a frequency having a value equal to 2.sup.N FO, a phase-locked loop consisting of N links connected in series between the output of the oscillator and the first input of the comparator, each link comprising a mixer having a first input connected to one of the outputs of the frequency generator, a second input and an output, the second input of the current mixer being connected to the output of the preceding mixer and the second input of the mixer being connected to the output of the oscillator.

Abstract: A receiving circuit is designed for an MSK (Minimum Shift Keying) receiver and a QPSK (Quadrature Phase Shift Keying) receiver. The circuit provides a synchronous state determining device and a control voltage sweeping device for sweeping the output of a voltage oscillator. In the asynchronous state, a switch is turned off for interrupting a reproducing phase error signal so that the output of the voltage oscillator may be swept for causing the synchronous state. Then, the sweeping operation is stopped and the switch is turned on for controlling the voltage of the voltage controlled oscillator so that the low-frequency error component is removed from the phase error signal of the demodulating circuit. This results in implementing the simply-arranged demodulating circuit which keeps the proper demodulating performance against the shifted carrier frequency without any degrade and demodulates the input signal stably if the signal has a low C/N ratio.

Abstract: An antenna is employed to receive a (1540 f0) L1 GPS-satellite signal. In addition, a filter, an (RF) amplifier, a harmonic mixer, and a (sole) local oscillator are employed, the combination configured to mix the seventh harmonic of a 192 f0 local oscillator generated signal with the receive satellite signal to down-convert the frequency of the received GPS-satellite signal to a 196 f0 IF frequency. Further, another filter, an (IP) amplifier, and a mixer are employed, the combination configured to mix the fundamental of the 192 f0 local oscillator generated signal with the 196 f0 GPS-satellite signal to down-convert the frequency of the satellite signal to four f0. Finally, yet another filter and an amplifier are employed, the combination configured to filter and amplify the four f0 GPS-satellite signal.

Abstract: A radar transmitter chain employing injection locked oscillator, e.g., a magnetron, as an output stage. Problems arise with maintaining the injection locking bandwidth centered on the radar source transmit frequency. This alignment is maintained by allowing the magnetron (38) free running frequency to drift, along with its injection locking bandwidth and then to force the radar source frequency (30) to follow the magnetron frequency. A phase difference measurement (44) between the injection signal (35) and the magnetron output signal (37) provides the control for a feedback loop (60) which may control a tunable VCO (48) or selection from a bank of fixed frequency oscillators (78).

Abstract: An FM receiver having a phase-locked loop demodulator and a control voltage correction circuit for the local tuning oscillator. The correction circuit includes a comparator for comparing the output frequency of the phase-locked loop demodulator with the output signal from a reference oscillator, the output of the comparator being connected through an integrator to provide a control signal for the local oscillator as part of an automatic frequency control loop. The comparator output is also fed through an integrator to an adder connected between the demodulator output and the demodulator oscillator controlled input, for setting the demodulator oscillator at the center intermediate frequency when no carrier signal is being received.

Abstract: A multiple-loop microwave frequency synthesizer is provided with an upper and a lower phased-lock loop. The phased-lock loops are mutually connected to a novel sampling mixer and their outputs are connected to an up-converter for providing microwave frequency generated signals. The phased-lock loops are provided with a plurality of programmable frequency dividers connected to a processor controller to provide a wide range of adjustable frequencies up to 20 gigahertz at the output of the frequency synthesizer.

Abstract: In an RF receiver having a phase-locked loop demodulator and FLL tuning in its RF converter, the frequency of the VCO output signal in the phase-locked loop (PLL) demodulator is controlled indirectly by the FLL in the RF converter in response to a measurement of the VCO output signal in the phase-locked loop demodulator and comparison of such measured signal to a predetermined intermediated frequency. A microcomputer performs a refined FLL tuning algorithm to tune a selected RF carrier input signal and audio subcarrier input signals. The algorithm provides a means of assuring that the PLL demodulator is responding to an input signal derived from a carrier signal of a selected input frequency without having to use hardware to detect the presence of a carrier signal.

Abstract: AM receiver comprising a tuning oscillator (T0), a first phase detector (PD1) and a first loop filter (LP1) successively arranged in a first phase control loop. The tuning oscillator (T0) is synchronized with a reference oscillator (VCX0) coupled to the first phase detector (PD1) and applies a mixing frequency to a mixer stage (M) for conversion of a received AM signal into an IF-AM signal. The mixer stage (M) is coupled to an AM demodulator (SD) for demodulation of the base-band modulation signal. The reference oscillator (VCX0) is controllable and is disposed between a second loop filter (LP2) and a second phase detector (PD2) of a second phase control loop coupled to the mixer stage (M) for applying a local detection carrier synchronized with the IF-AM signal carrier to the AM demodulator (SD).

Abstract: A frequency converting circuit converts an input frequency into a desired frequency. To obtain the desired frequency, a first frequency converter converts the input frequency, by using an output frequency of a first local oscillator, into an intermediate frequency. The first local oscillator is a voltage controlled oscillator as a part of a phase locked loop circuit. A second frequency converter converts the intermediate frequency into the desired frequency by using an output frequency of a second local oscillator. A phase comparing circuit compares the phase of the output signal of the second frequency converter with that of the output signal of the first local oscillator. The phase comparing circuit is contained in the phase locked loop circuit. The result of the comparison is used for controlling the oscillating frequency of the first local oscillator.

Abstract: A Frequency synthesis stage comprises two phase locked loops. The first (O.sub.1, D.sub.1, M, CP.sub.1, D.sub.2) divides the frequency Fo+.DELTA. derived from preceding stages by N/Q, N being a variable integer, and adds to the result a standard frequency P which is in a fixed ratio with a value representative of large frequency steps so as to give an intermediate frequency F.sub.A, while the second (O.sub.2, M.sub.0, M.sub.1, CP.sub.2 D.sub.3) multiplies F.sub.A by NQ/r. P and Q are selected so that the product PQ is approximately equal to the mean of the limit values desired for the output frequency.

Abstract: A phase-locked loop is constituted by a controllable oscillator coupled through a phase detection arrangement and a low-pass filter to receive an input carrier applied to a signal input of the phase detection arrangement. In order to decrease the phase synchronization between a carrier locally generated in the loop and an input carrier, an unwanted DC offset generated during phase detection is reduced. The phase detection arrangement has first, second and third cascade-coupled mixer stages. An auxiliary mixing signal is applied from a signal generator to the first and third mixer stages. An input of one of the first and second mixer stages is coupled to the signal input of the phase detection arrangement and an input of the other of the two last-mentioned stages is coupled to an output of the controllable oscillator. The low-pass filter has a cut-off frequency lower than the fundamental frequency of the auxiliary mixing signal, and the fundamental frequency is lower than the frequency of the input carrier.

Abstract: A frequency synthesizer is disclosed having n identical digital module stages, each of which stages generates one digit of the final frequency number of the synthesized frequency output signal. Each digit module stage comprises a series arrangement of a phase lock loop, a digit adder, and a digit shifter. The present invention provides a synthesized frequency generator with components that are inexpensive and readily available commercially, and moreover the frequency synthesizer is digitally controllable such that it is compatible with other digital control circuits.

Abstract: A frequency synthesizing apparatus of the closed-loop design employing a first frequency mixing means to provide a continuous constant increment frequency coverage over a given output signal frequency range. The first frequency mixing means is responsive to the output signal and a first reference signal to provide a first difference signal both when the output signal frequency is higher than and lower than the first reference signal frequency. A frequency comparison means is responsive to the first difference signal and to an input signal, the input signal being continuously variable over a given input frequency range, to provide a first error signal for controlling the output frequency and stabilizing the closed loop. The first reference signal is comprising of a plurality of predetermined, selectable frequencies provided by a phase-locked loop employing a second frequency mixing means.

Abstract: The tuning control system of a double-conversion tuner includes a phase locked loop type of frequency synthesizer for controlling the frequency of a controllable oscillator comprising the first local oscillator of the double-conversion tuner according to the frequency deviation of the difference between the frequencies of the first and second local oscillators from a reference frequency in order to compensate for the drift of either one of the local oscillators. An up/down counter which counts in one sense in response to the first local oscillator signal and in the other sense in response to the other local oscillator signal is used to generate the frequency difference signal. Because the frequency of the first local oscillator is always greater from the frequency of the second local oscillator the up/down counter can be implemented in the form of a simple pulse swallower.

Abstract: A frequency synthesizer which is capable of providing very high output frequencies of the order of 500 MHz is designed to produce a very pure signal having very low noise. An overtone crystal oscillator which is constrained to oscillate at a harmonic frequency of the fundamental frequency determined by the physical dimensions of the crystal is mixed with a variable low frequency signal which is varied to provide the necessary output frequency steps. It is not possible to adjust the frequency of the overtone crystal oscillator without degrading its stability and introducing noise, and any departure of the frequency to the overtone crystal oscillator from its nominal value is compensated by adjusting the low frequency oscillator.

Abstract: Quadrature detectors are subject to errors due to both phase and amplitude mismatches. The disclosed invention comprises a system for sampling the I and Q channel output signals of a quadrature detector and processing these signals to generate a signal which has a predetermined relationship to the phase error in the in-phase and quadrature signals independent of amplitude mismatches in said signals. The necessary mathematical computations can be performed by analog or digital circuitry. Phase error correction can be accomplished by a servo loop which changes the relative phase of the reference signals to the I and Q channels or by mathematically correcting the I and Q channel output signals to reduce the phase error.

Abstract: An improvement in a digital frequency synthesizer comprising a voltage-controlled oscillator (VCO) for producing a signal S.sub.VCO having a frequency f.sub.VCO, a first signal generator for generating a plurality of signals S.sub.AS having a spectrum of frequencies f.sub.AS, all exceeding a given minimum frequency f.sub.M, a mixer responsive to S.sub.VCO and to S.sub.AS to produce an output signal having a frequency (f.sub.VCO .+-.f.sub.AS), a divide-by-N divider responsive to (f.sub.VCO .+-.f.sub.AS) to produce a signal S.sub.N having a frequency f.sub.N, a second signal generator for generating a first reference signal S.sub.R1 having a frequency f.sub.R1, a phase detector responsive to S.sub.N and S.sub.R1 to produce a d.c. control signal E.sub.c whose amplitude varies with the phase relation of S.sub.N and S.sub.R1, and a filter for supplying E.sub.c back to said VCO, the VCO being responsive to E.sub.c to produce an output signal S.sub.VCO of frequency f.sub.VCO where (f.sub.VCO .+-.f.sub.AS )=Nf.sub.

Abstract: A phase synchronizing circuit, wherein two phase detectors are used in quadrature to detect the phase of an input signal and to avoid hang-up when the phase of the input signal changes abruptly by 180.degree.. The two detected phase signals are then multiplied by a locally generated reference signal and re-combined, so that a synchronized output signal having reduced phase jitter results. This circuit is also incorporated in an N-phase PSK system, where it is used as a synchronizer and not as a demodulator. In a receiver for such a PSK system, the frequency of the received signal is multiplied by N, the phase synchronizer circuit of the invention is then used to extract the carrier (at a N times higher frequency), and a divider is then used to convert the synchronized carrier provided by the synchronizer circuit of the invention down to the original frequency.

Abstract: A wide band oscillator with phase lock loop is controlled by signals from an 40 MHz harmonics generator combined with the output of another phase lock loop controlled oscillator whose selectible outputs vary in MHz steps with a total range of 39 MHz. The phase lock loop of the wide band oscillator is additionally controlled by a d/a converter and by another phase lock loop controlled oscillator whose selectible outputs vary in one KHz steps. Each of these phase lock loops is digitally controlled from the input frequency selection and again therefrom via a digital-to-analog converter. The output of the wide band oscillator is combined with the output of a narrow band oscillator which may be FM modulated. Alternatively, an output amplifier for the combination difference frequency may be AM modulated.

Abstract: The invention provides a double superheterodyne receiver having the usual first and second frequency changers associated with first and second local oscillators. The second local oscillator is provided as a voltage controlled oscillator and means are provided for determining the difference frequency between the two local oscillators to produce a control signal which is applied to the second local oscillator to tend to maintain the difference frequency constant.

Abstract: A radio receiver comprises a frequency conversion circuit connected between a frequency-variable local oscillator and a divide-by-N programmable counter incorporated in a phase locked loop frequency synthesizer and adapted to continuously change the frequency to be divided by the programmable counter. Owing to the frequency conversion circuit, the local oscillator frequency is permitted to continuously change in the locked state of the phase locked loop so that the intermediate frequency offset adjustment of receivers, that is, the adjustment of the intermediate frequency of each receiver to the center frequency of an intermediate frequency filter used in the receiver can be made easily, and that a reception of such a broadcast station as having a carrier frequency which is not an integral multiple of a channel spacing frequency also can be made.

Abstract: The use of a digital frequency translator, using pulse snatching techniques, for multiplying the output frequency of a precise and accurate frequency synthesizer by a preselected certain numerical fraction permits the frequency synthesizer to be referred to a molecular clock with only a single VCXO phase lock loop.

Abstract: A microwave frequency synthesizer utilizing a phase locked loop for generating a wide range of microwave frequencies in response to a control signal, in combination with a network including a plurality of distinct frequency local oscillators that are appropriately selectable for mixing with the signal output of the phase locked loop for translating it into a desired range, thereby expanding the effective frequency range of the phase locked loop. The combination provides a stable source of microwave frequency signals over a wide frequency range. The combination allows a simple, low cost circuit implementation and may be switched between output frequencies at a very fast speed.

Abstract: A local oscillator having a variable frequency oscillator and a carrier frequency oscillator for use in communication systems that transmit and/or receive signals on multiple frequency bands, one crystal reference oscillator; a converter circuit for mixing the outputs of at least the variable frequency oscillator and the carrier frequency oscillator to produce an output having a frequency corresponding to the receiving frequency and a phase-locked loop circuit including a plurality of voltage control oscillators corresponding to the number of receiving frequency bands; a mixing circuit for mixing the output of a predetermined one of the voltage control oscillators corresponding to a predetermined one of the frequency bands with the output of the converter circuit to produce an output of fixed frequency corresponding to the one frequency band; a programmable counter that divides the output of the mixing circuit in accordance with a frequency dividing ratio corresponding to the one frequency band; and a phase c

Abstract: The output of a VCO, a referenced frequency signal and an offset frequency signal are mixed to provide a control signal for the VCO and a double offset frequency signal which is mixed with an output of the offset frequency source to provide a DC component having a positive polarity if the signals are inphase and the VCO is locked on one sideband and a negative polarity if the signals are out of phase and the VCO is locked on the other sideband. A sweep signal is activated and applied to the VCO in response to the VCO being locked onto the wrong sideband.

Abstract: A heterodyne phase lock system is disclosed having a plurality of oscillator circuits, a similar plurality of heterodyne (mixer-filter) circuits representing an input circuit, and a similar plurality of heterodyne circuits representing a control circuit, at least one of the oscillator circuits being a voltage controlled oscillator (VCO) circuit. The heterodyne circuits of the input circuit are cascaded, i.e., linked each to the other, successively, and the heterodyne circuits of the control circuit are likewise cascaded. Each oscillator is linked to a pair of heterodyne circuits, i.e., to one heterodyne circuit in the input circuit and to one heterodyne circuit in the control circuit, and applies a common output signal to said pair of heterodyne circuits.

Abstract: A comparator-discriminator is provided, suitable for use with a phaselock control system of a frequency synthesizer, to permit automatic tuning of a variable oscillator to a selected frequency lying within a frequency band for which a phaselock may occur. This system permits the frequency of the variable oscillator to lock-on to an arbitrary value in the range other than the preselected value, at which time the phaselock is broken by an injected signal, thereby permitting the shifting of the oscillator frequency to a value lying closer to the selected frequency value. Upon achievement of phaselock to the selected frequency, in a slightly more elaborate embodiment, the injected signal is inhibited and no further breaking of phaselock can occur.

Abstract: A phase locked loop type transmitter-receiver having a phase locked loop type synthesizer including a circuit in which a programmable counter, a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a mixer are connected in a closed loop; wherein the mixer is connected to a reference oscillator connected to the phase discriminator through a fixed frequency divider, the mixer being adapted to mix frequencies fed from the reference oscillator and the voltage-controlled oscillator thereby synthesizing sum and difference signals thereof, the difference signal being fed to the programmable counter and the sum signal being fed to a transmitting-side mixer and a receiving-side mixer.

Abstract: A phase locked loop synthesizer comprising a means for controlling a tuning means, wherein a phase difference between the outputs of a reference signal oscillator and a programmable counter means is detected by a phase detector to obtain a d.c. voltage corresponding to the phase difference, an output having a prescribed frequency is generated by a voltage controlled oscillator frequency is controlled by said d.c.