Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract: A high-accuracy oscillator obtains initial control bits to generate an initial signal and generates adjacent control bits to generate an adjusted signal from the oscillator based on the adjacent control bits. Characteristics of the initial signal and the adjacent signal are compared to a preset value to determine which of the initial signal and the adjusted signal is closer to a target signal. The closer of the initial signal and the adjusted signal to the target signal is output from the oscillator.

Abstract: A PLL circuit has a voltage control oscillator, a rough-adjusting loop part and a fine-adjusting loop part. The rough-adjusting loop part configured to perform a rough adjustment to the frequency of the oscillating signal based on a frequency-setting signal. The fine-adjusting loop part performs a fine adjustment to the frequency of the oscillating signal after the rough adjustment by the rough-adjusting loop part. The fine-adjusting loop part includes a phase comparator configured to detect a phase difference between the frequency-divided signal obtained by frequency-dividing the oscillating signal at the frequency divider and the reference signal while a switched state of each of the first switching parts at a moment of the completion of the rough adjustment at the rough-adjusting loop part remains unchanged.

Abstract: A command and control system is provided including a core unit, with a processor and a map display engine. The core unit is configured to exchange information with a multi-domain heterogeneous unmanned vehicle command and control module, a multi-sensor command and control module, and an asset tracking module. The asset tracking module estimates a location of an indeterminate object. A control unit exchanges information with an input device. A detecting unit detects modules that are associated with the core unit. A subscription unit logs parameters associated with the detected modules and determines types of data to send to the detected units based on the parameters. A script unit receives and implements command and control scripts for the detected modules. A display output provides display information of a combined representation of information from the detected modules and map information, including locations of the vehicles and sensors under control and the estimated location of the indeterminate object.

Abstract: A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.

Abstract: Equal numbers of variable capacitance elements, capacitance values of which are separately controlled according to a logic value of a corresponding bit of a delay control signal that is in a one-to-one relation with an oscillation frequency, are connected in parallel among differential outputs of all delay circuits excluding a differential non-inverting delay circuit at the end, which extracts a frequency signal to the outside. Bits of the delay control signal are connected in a one-to-one relation to the equal numbers of variable capacitance elements arranged on output sides of all the delay circuits, in a relation in which delay control signals continuous in terms of frequency are not connected to the equal number of variable capacitance elements arranged on an output side of one of the delay circuits.

Abstract: A phase interpolator includes a plurality of clock phase input sections, a plurality of clock phase switching sections, a plurality of current sources and a load. Each of the clock phase input sections is coupled to receive one of a plurality of reference clock phases (e.g., 0°, 90°, 180°, and 270°). The plurality of current sources is selectively coupled to the plurality of clock phase input sections via the clock phase switching sections based on a phase control signal. The number of current sources corresponds to the phase granularity between the reference clock phases. The load is coupled to a phase adjusted clock signal in accordance with the phase control signal.

Abstract: A jitter-less phase detector in a clock recovery circuit is disclosed. A first control signal generating circuit generates a first control signal by inverting and delaying input data signals through half clock. A second control signal generating circuit generates a high level second control signal when the data signal changes. A phase comparator generates an up signal having a high-level from the falling edge of the first control signal to the falling edge of the second control signal, and generates a down signal having a high-level from the falling edge of the second control signal to the falling edge of the first control signal, so as to control a pair of current sources to selectively discharge and charge a capacitor.

Abstract: In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.

Abstract: The VCO of a synthesizer operates with a coarse tuning and a fine tuning. During the coarse tuning, a binary search method is used to match the VCO frequency to one of a finite number of discrete reference frequencies. The coarse tuning operates without frequency division and phase comparison in a closed feedback loop, thereby speeding up the settling time and increasing the lock-in range. The fine tuning operates as a conventional analog PLL.

Abstract: A phase detector includes a Gilbert block for outputting a signal proportional to a phase difference between first and second input signals to a first output terminal, and a current source for determining a current in the first output terminal. The current source is controlled by a reference current signal. A converter outputs a current to a second output terminal in response to the signal output from the first output terminal. A variable current source varies the current output to the second output terminal. A controller controls the variable current source in response to the first and second input signals.

Abstract: Apparatus for generating an oscillating signal in a desired phase relationship with an input signal, including a mixer arranged to receive a pair of reference signals oscillating at a common frequency and having a phase offset between them, and to mix the reference signals in variable proportions according to the value of input weighting signals to generate an output signal. A comparator is to compare the phase of the output signal with that of the input signal to determine whether the signals are in the desired phase relationship and, if not, to output one or more control signals indicative of the required adjustment in the phase of the output signal to achieve the desired phase relationship. An adjustable ring oscillator including a plurality of stages is connected in a ring and arranged to propagate oscillations around the ring.

Abstract: Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Abstract: A phase detector includes a Gilbert block for outputting a signal proportional to a phase difference between first and second input signals to a first output terminal, and a current source for determining a current in the first output terminal. The current source is controlled by a reference current signal. A converter outputs a current to a second output terminal in response to the signal output from the first output terminal. A variable current source varies the current output to the second output terminal. A controller controls the variable current source in response to the first and second input signals.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined by counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: In a phase locked loop arrangement of a frequency synthesiser, a signal outputted from a voltage controlled oscillator is locked to a reference oscillator. A phase detector is arranged so that the frequency of the reference oscillator is a multiple of the frequency of the voltage controlled oscillator, which significantly reduces the phase noise emitted by the voltage controlled oscillator.

Abstract: A phase locked loop (PLL) is used in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract: A time discrete PLL-tuning system comprises a phase detector and a voltage controlled oscillator (VCO) for tuning the frequency (fVCO) thereof to a frequency equal to N/M times a reference frequency (fREF), with M a factor indicating the number of frequency steps in which a transmitter/receiver channel distance is divided and N the number of frequency steps in which the oscillator frequency is divided. The sampling frequency of the phase detector is substantial equal to the reference frequency (fREF).

Abstract: A signal generator and a method of generating a signal are disclosed that offsets phase and frequency of the output signal relative to the input signal by small increments, providing high resolution. The signal generator utilizes numerically controlled oscillators to instantly and independently offset phase and/or frequency.

Abstract: A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

Abstract: A PLL circuit used in an apparat as for reading and writing data to a disk compensates for noise which causes a false clock signal or for missing clock signals which can be caused by a scratch or smudge on the surface of the disc. The PLL circuit includes a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal and generates a phase difference signal. A charge pump receives the phase difference signal and generates an output signal, which is filtered by a low pass filter. The filtered signal is provided to a voltage controlled oscillator, which generates an oscillation output signal. A divider divides the oscillation output signal and generates the feedback signal. A time information generating circuit generates time information of the oscillation output signal, indicating the time period where it is presumed the reference signal is or should be received.

Abstract: There is disclosed a phase detector which triggers on both rising and falling edges of an input pulse signal. This effectively doubles the frequency of the input signal. When the phase detector is used in a phase locked loop, the doubled frequency means that a lower division ratio can be used, thereby reducing any noise contribution introduced thereby.

Abstract: A digital phase comparator comprises a first signal input (VCO) and second signal input (REF) as well as a first output (UP+) and second output (DOWN+). It is arranged so as to produce an output pulse (503, 504) to the first output and second output per each of the cycles of the periodic signals (501, 502) brought to the first signal input and second signal input. The duration of the output pulse produced to the first output is longer than the duration of the output pulse produced to the second output when the phase of the periodic signal brought to the first signal input is lagging with respect to the phase of the periodic signal brought to the second signal input. Correspondingly, the duration of the output pulse produced to the first output is shorter than the duration of the output pulse produced to the second output when the phase of the periodic signal brought to the first signal input is leading with respect to the phase of the periodic signal brought to the second signal input.

Abstract: The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direct modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints.

Abstract: A digital frequency multiplier is provided that continues to adjust its multiplied frequency after the desired multiplied frequency is reached, that can be tested during operation and that is easily scalable. The digital frequency multiplier comprises a frequency detector, a frequency adjuster and a ring oscillator (RO). The frequency detector is configured for receiving a reference frequency and an RO output frequency, and for continuously monitoring a difference between the reference frequency and the RO output frequency. Based on the continuously monitored difference, the frequency detector continuously outputs an adjusting signal to the frequency adjuster. In response thereto, the frequency adjuster outputs selection data to the RO that adjusts the oscillation frequency of the RO, and thus the multiplied frequency of the digital frequency multiplier. Testable and growable logic circuitry are provided within the RO that allow the digital frequency multiplier to be tested during operation and easily scaled.

Abstract: A PLL response time is accelerated with a frequency detector counter. The PLL utilizes both a phase frequency detector and the frequency detector counter. Initially, the operation of the PLL is controlled by the frequency detector counter and the output of phase frequency detector does not affect the PLL system. During this period, the PLL synchronizes to an input clock frequency. After the PLL reaches a predetermined frequency range, the frequency detector counter stops working. Thereafter, the phase frequency detector controls the operation of the PLL. During this period, the PLL synchronizes to both the frequency and the phase of the input signal.

Abstract: A voltage controlled ring oscillator has a current control circuit and an odd number of inverter circuits. Each inverter circuit has a current charge preventing circuit connected between a ground voltage and a connection node located between a current source transistor and a complementary transistor circuit and a current discharge preventing circuit connected between a high voltage power source and a connection node located between a current source transistor and a complementary transistor circuit.

Abstract: Phase-locked loop oscillators that are designed to set the clock rate of electronic circuits based on combinations of logic circuits and to be integrated, at the same time as these electronic circuits, into one and the same chip. There is proposed a phase-locked loop oscillator based purely on combinations of logic circuits so as not to make use of integration techniques different from those used for the electronic circuits based on combinations of logic circuits, for which they are designed to set the clock rate.

Abstract: In an oscillating circuit, an oscillator generates an oscillation signal with a frequency, increases the frequency of the oscillation signal in response to a frequency increase signal and decreases the frequency of the oscillation signal in response to a frequency decrease signal. A detecting unit receives the oscillation signal and a reference signal. The detecting unit outputs the frequency increase signal to the oscillator when a ratio of the frequency of the oscillation signal to a frequency of the reference signal is smaller than a first predetermined value, and outputs the frequency decrease signal to the oscillator when a ratio of the frequency of the oscillation signal to the frequency of the reference signal is larger than a second predetermined value.

Abstract: An improved apparatus for combining frequencies which is capable of generating a constant frequency when an external variation is applied thereto by implementing each block using a differential circuit, whereby it is adaptable to a mobile communication system, includes a phase frequency detector for comparing an input signal with a reference signal and for detecting a frequency or a phase error; a filter for differentially amplifying an output of the phase frequency detector for generating a lower frequency voltage corresponding to the error; a voltage control oscillator for generating a frequency corresponding to an output of the filter; a signal distribution unit for dividing the output of the voltage control oscillator into a predetermined times and for outputting a reference signal to the phase frequency detector; and a reference voltage generator for inputting reference voltages to the voltage control oscillator, respectively.

Abstract: A frequency synthesizer SYNT intended to supply an output signal Sout having an output frequency which depends on the average frequency, referred to as symbol frequency, of an input signal Sin beset with a strong phase noise. This synthesizer SYNT includes: a phase/frequency detector PHD comparing the symbol frequency with a predetermined fraction of the output frequency, and supplying a control signal; a low-pass filter LPF filtering the control signal; and an oscillator VCO supplying a signal Sout with a frequency which is adjusted by the filtered control signal Cs. Reference pulses having the symbol frequency are generated within the synthesizer SYNT by means of pulses from an internal clock, which pulses are validated by active states of the input signal Sin.

Abstract: A symmetric capture range is produced in a two-quadrant phase detector phase locked loop that utilizes nonsymmetric pulse waves. The phase detector is enabled only during VCO pulses. A latch stores the relative relationship between the leading edge of the input pulse and the center of the VCO pulse in the previous cycle. If the phase angle .theta. form the VCO pulse center to the leading edge of the input pulse is0 deg<.theta.<180 deg,then the phase detector incrementally decreases the VCO frequency at the next VCO pulse. If the phase angle .theta. is180 deg<.theta.<360 deg,then the phase detector incrementally increases the VCO frequency at the next VCO pulse.

Abstract: A frequency locked loop (FLL) having an oscillator whose output frequency controls the amount of charge provided by a switched feedback capacitor to a charge integrator whose output voltage controls the frequency of the oscillator. A switched reference capacitor provides a charge to the charge integrator which is a function of a reference frequency, so that the oscillator output frequency is a function of a product of the reference frequency times a ratio of the capacitance of the reference capacitor to the capacitance of the feedback capacitor. Plural reference capacitors, each responsive to a respective reference frequency may be provided so that the oscillator output frequency can be related to the sums or differences of the reference frequencies, the ratios of capacitors, the ratio of the reference voltages or a fixed multiplication factor.

Abstract: A phase detector for a phase-locked loop ("PLL") circuit under control of a local oscillating clock ("LOSC") signal and a method of operation thereof.

Abstract: A method and an apparatus are provided to achieve fast phase settling when a reference signal for a phase locked loop changes from a first frequency to a second frequency, such as during holdover recovery in a synchronous optical network. The present method acquires the second frequency with a phase locked loop (24). After the frequency is acquired, the integral register (39) of the phase locked loop (24) is loaded with the contents of the output frequency register (34) of the phase locked loop (24). The phase detector (28) of the phase locked loop (24) is then realigned to the reference signal.

Abstract: A digital frequency synthesizer includes a digital-to-analog (1), a low pass filter (2), and a controllable oscillator (3), where the oscillator output is the synthesizer output. K number of RS flip-flops (101-108) produce error signals which are coupled to the DAC. The S inputs of the flip-flops come from a phase-splitter (8) which is driven by the more-significant bits unit of an accumulator (5) which is clocked by a reference frequency. The R inputs of the same flip-flops get input pulses from a pulse distributor (9) which is driven by the synthesizer output. The frequency resolution can be increased by adding a less-significant bits accumulator (15), coupled to the more-significant bits unit.

Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop, which phase offset is due to circuit delays in the phase detector. Simultaneous "pump up" and "pump down" signals, present even during apparent phase lock because of such circuit delays, are peak sampled through long lime constant filters and summed to derive a compensating signal which is applied to the reference input to the differential amplifier which controls the local oscillator, thereby exactly counteracting the offset component of the voltage appearing at the signal input to the differential amplifier which is developed during normal operation of the phase detector, filter and summing circuit of the phase locked loop at apparent phase lock.

Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop. The phase offset is due to circuit delays in the phase detector which result in the issuance of simultaneous "pump up" and "pump down" signals, present even during apparent phase lock. A second pair of flip-flops (or a single flip-flop) of the same type used in the phase detector is sampled to obtain a compensating signal which is applied to the reference input of a differential amplifier in the loop filter. Each of the second pair of flip-flops is forced to assume a permanent state (for example, set) such that their respective Q and Q-bar outputs are always representative of the logic voltage levels at the corresponding outputs of the flip-flops in the phase detector from which the "pump up" and "pump down" are sourced.

Abstract: A controllable crystal oscillator of a receiver having a mixer producing an IF signal is controlled by a feedback loop that includes a phase detector. The IF signal is delayed by an odd multiple of .pi./2 and fed to one input of an exclusive-OR circuit, with the other input receiving the IF signal directly. The phase detection signal from the exclusive-OR circuit can be counted and converted to an analog voltage when the oscillator is a voltage controlled oscillator or it can be counted and used as a digital control signal when the oscillator is a data controlled oscillator.

Abstract: A phase-locked loop includes an input terminal (1) for receiving a binary signal, a phase comparator (3) having a first input (2) coupled to the input terminal (1), having a second input (4), and having an output (5) coupled to an input (9) of a control-signal-controlled oscillator (10) via a control-signal generator unit (7). An output (11) of the oscillator is coupled to the second input of the phase comparator. The phase comparator derives a first pulse (P.sub.1) and a second pulse (P.sub.2) in response to a signal transition from a first value to a second value in the binary signal applied to the first input and an oscillation signal applied to the second input, the first pulse having a pulse width which is a measure of the phase difference between the binary signal and the oscillation signal, and the second pulse having a pulse width proportional to 1/2.f.sub.o, where f.sub.o is the frequency of the oscillation signal.

Abstract: A comparator of phase between a digital signal and a clock signal adapted for the construction of a phase locked loop in integrated circuit form, that includes a first channel formed by a flip-flop and an exclusive OR gate, and a second channel formed by a second exclusive OR gate and a delay circuit whose delay is set to half the period of the clock signal. The first channel receives the digital signal and the clock signal and delivers a first detection signal of transition of the digital signal. The second channel receives only the digital signal and delivers a second detection signal of transition of the digital signal.

Abstract: A phase comparator circuit in which an output synchronized with the input signal may be accurately produced without producing a malfunction even in the absence of the synchronization signal, in which a detection unit 11 detects the phase information of an input signal, an error detection unit 12 detects the phase error with respect to the phase of the input signal, a switch 13 switches between the phase error from the error detecting unit and plural fixed values of the phase error +.DELTA..alpha. and -.DELTA..alpha.

Abstract: A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).

Abstract: A phase locked loop circuit is provided which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which do not have "dead zones". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is also provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: A voltage controlled oscillator (VCO) which may be adjusted to provide oscillatory signals for a wide range of frequencies includes a relaxation oscillator in which a ramp signal is compared to a reference threshold which exhibits hysteresis. The frequency of the oscillator is changed by varying the hysteresis range of the threshold level and by changing the rate at which the ramp is generated. At higher frequencies, the signal processing delay through the comparator is a factor in determining the frequency of the signal produced by the oscillator. Current sources internal to the oscillator are controlled by a reference potential that is generated from an externally supplied band-gap reference potential. The VCO is used in a phase-locked loop which includes a charge pump circuit that accumulates charge on a capacitor responsive to limited-width pulses applied to a current source which is controlled by the reference potential generated in the VCO.

Abstract: To demodulate an analog signal having information modulated by a carrier, the analog signal is chopped by a chopper, the chopped signal is digitized by a sigma-delta analog-to-digital converter to produce a series of digital samples at a sampling frequency, the digital samples are filtered in a digital decimating filter to produce data words, and the data words are modulated by an intermediate frequency signal to produce a detected information signal. The various frequency signals are generated by a phase-lock loop so that the intermediate frequency is the difference between the carrier frequency and the chopping frequency, and both the chopping frequency and the intermediate frequency are sub-multiples of the sampling frequency.

Abstract: A phase detector circuit (10) for generating an analog signal (VR) dependent upon the phase difference between two digital signals (VE, VA) includes two NOR circuits (20, 27) to the inputs (18, 26; 28, 24) of which the two digital signals are supplied on the one hand delayed and negated and on the other directly. The output signals of the NOR circuits (20, 27) control two current sources (S1, S2), one of which in the activated state furnishes a constant charge current (I1) for a storage capacitor (C) whilst the other of which leads a constant discharge current (I2) of equal magnitude away from said storage capacitor (C). The charge voltage at said storage capacitor (C) is an analog signal (VR) which represents a measure of the phase deviation between the digital signals (VE, VA).

Abstract: In methods and apparatus for controlling a phase relationship of two signals, a supplementary phase adjustment signal is generated. The supplementary phase adjustment signal has a zero value when an actual phase relationship of the two signals deviates from a desired phase relationship by less than a threshold phase deviation, and has a non-zero value when the actual phase relationship deviates from the desired phase relationship by more than the threshold phase deviation. The phase relationship of the two signals is adjusted in response to a sum of the supplementary phase adjustment signal and a phase adjustment signal which is proportional to the deviation of the actual phase relationship from the desired phase relationship. The methods and apparatus are particularly applicable to alignment of clock signals with data signals.

Abstract: A phase-lock-loop circuit for generating a clock signal at a frequency higher than a horizontal frequency of a video signal includes a phase detector. The phase detector includes a flip-flop that is set when a horizontal sync pulse occurs. An output of a counter that provides frequency division is decoded for resetting the flip-flop in each horizontal period. Other than for the flip-flop, and for the counting stages of the counter, only combinational logic components are used for producing a phase error indicative signal that is coupled via a low-pass filter to a control input of an oscillator of the phase-lock-loop circuit.