Abstract: Disclosed is a frequency multiplication apparatus including a first frequency multiplier receiving a first signal having a first frequency and outputting a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer), a second frequency multiplier receiving the second signal and outputting a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer), and a coupler connected between an output of the first frequency multiplier and an input of the second frequency multiplier and outputting a part of the second signal.

Abstract: Systems and methods disclosed herein provide for effectively eliminating the rotational and static phase skews between the in-phase (I) and quadrature (Q) clocks generated by phase interpolators in decision feedback equalizer based receivers. Embodiments of the systems and methods provide for (i) a ring oscillator that eliminates the rotational phase skews and (ii) a plurality of clock mixers that eliminate the static phase skews.

Abstract: A signal generation circuit includes a voltage controlled oscillator configured to generate a differential oscillator signal having an amplitude. A passive mixer has first differential inputs coupled to the voltage controlled oscillator to receive the oscillator signal. The passive mixer also includes second differential inputs. A filter circuit is coupled between the voltage controlled oscillator and the second differential inputs of the passive mixer. The filter circuit is configured to filter the differential oscillator signal as a function of the amplitude of the differential oscillator signal to thereby generate a filtered differential oscillator signal and to provide the filtered differential oscillator signal to the second differential inputs of the passive mixer.

Abstract: The disclosed signal generator circuit has a four-phase signal generator circuit generating four-phase signals with a first frequency; an eight-phase signal generator circuit performing ½ frequency division of the four-phase signals to generate eight-phase signals with a second frequency; a first to a fourth harmonic rejection mixer circuits multiplying a first four-phase signal and a second four-phase signal of the four-phase signals by a first to a third eight-phase signals and a third to a fifth eight-phase signals of the eight-phase signals with mutually different combinations; a subtractor subtracting between outputs of the first and the fourth harmonic rejection mixer circuits to generate a first output signal with a third frequency; and an adder adding between outputs of the second and the third harmonic rejection mixer circuits to generate a second output signal with a third frequency whose phase is different from the first output signal by ?/2.

Abstract: A dual-band wideband local oscillation signal generator includes an oscillation unit, a division unit, a poly phase filter (PPF), a switch unit, and a single side band (SSB) mixer. The oscillation unit is configured to generate a positive in-phase (IP) signal, a negative in-phase (IN) signal, a negative quadrature-phase (QN) signal, and a positive quadrature-phase (QP) signal. The division unit is configured to divide frequencies of the IP signal and the IN signal and generate an RF signal. The PPF is configured to receive the IP signal and the IN signals inputted to the division unit, and generate an LO IP signal, an LO IN signal, an LO QP signal, and an LO QN signal. The switch unit is configured to receive the generated LO signals and select a high band frequency signal or a low band frequency signal.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: The present invention provides a frequency synthesizer for a wireless communication system. The synthesizer includes an oscillator that generates an electronic signal as well as frequency dividers, frequency selectors and mixers. The signal generated by the oscillator is sequentially divided by the frequency dividers to produce a first group of frequencies, and the selectors and mixers are then capable of mixing the first group of frequencies according to instructions from control bits to produce a second group of frequencies which constitute UWB band frequencies. In this manner, the synthesizer can generate all 14 UWB band frequencies or particular UWB band groups using a single oscillator. One of the frequencies generated by the dividers can also be used as the baseband clock signal without requiring an additional frequency source.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n/m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q)fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

Abstract: Device and method for temperature compensation in a clock oscillator using quartz crystals, which integrates dual crystal oscillators. The minimal power consumption is achieved through an efficient use of a processor in charge of the synchronization of the two oscillators. The invention is particularly adapted for the provision of a precise reference clock in portable radiolocalization devices.

Abstract: A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The local oscillator signal for the mixer is derived from the same low phase noise source as the phase comparison frequency.

Abstract: A voltage-controlled ring oscillator comprises a ring oscillator having a plurality of differential delay stages for generating signals having a common programmable oscillation frequency with different phases, and a pair of single-sideband mixers coupled to the differential delay stages for producing in-phase and quadrature phase signals having a frequency that is higher than the oscillation frequency.

Abstract: A frequency synthesizer with a single PLL and multiple SSB mixers is presented. The frequency synthesizer includes a single PLL outputting a reference signal that is fed to a plurality of dividers coupled in sequence. The outputs from the dividers are mixed by the SSB mixers to produce signals with different frequencies. These signals with different frequencies can be selected through use of multiple selectors.

Abstract: A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.

Abstract: A voltage-controlled ring oscillator comprises a ring oscillator having a plurality of differential delay stages for generating signals having a common programmable oscillation frequency with different phases, and a pair of single-sideband mixers coupled to the differential delay stages for producing in-phase and quadrature phase signals having a frequency that is higher than the oscillation frequency.

Abstract: Methods and systems for reducing interference in a signal are disclosed herein. Aspects of the method may comprise generating a first local oscillator signal. The generated first local oscillator signal may be phase-shifted to generate a second local oscillator signal and the second local oscillator signal may be phase-shifted to generate a third local oscillator signal. The first, second, and third local oscillator signals may be combined to generate a combined local oscillator signal, where a third harmonic and/or a fifth harmonic may be eliminated from the combined local oscillator signal. The generated second local oscillator signal may be multiplied by a factor of square root of two (?{square root over (2)}). The first and third local oscillator signals may be added to the multiplied second local oscillator signal. An input signal may be mixed with the generated combined local oscillator signal to generate a mixed output signal.

Abstract: A frequency synthesizer with a single PLL and multiple SSB mixers is presented. The frequency synthesizer includes a single PLL outputting a reference signal that is fed to a plurality of dividers coupled in sequence. The outputs from the dividers are mixed by the SSB mixers to produce signals with different frequencies. These signals with different frequencies can be selected through use of multiple selectors.

Abstract: A frequency synthesizer in an ultra wide band (UWB) wireless communication system which transmits and receives data through multiband includes a frequency generation means which generates a plurality of frequency signals; and a frequency adjustment means which receives the plurality of frequency signals from the frequency generation means and generates center frequencies of all or part of sub-bands within the UWB through the frequency adjustment. Since all of the center frequencies of the sub-bands are generated, the utilization of the sub-bands can be enhanced for the wideband wireless communication. Furthermore, it is possible to enable the stable UWB communications by flexibly utilizing all of fourteen sub-bands since the sub-bands suffer less from the frequency interference in a complicated and variable wireless frequency environment.

Abstract: A radio mode selectivity block 41 for a detector 1 for detecting a buried current carrying conductor comprises a plurality of beat frequency oscillators 53 to center the bandwidth of detection of the detector 1 on target very low frequency (VLF) frequency bands. The frequencies of the beat frequency oscillators are chosen to fall within the VLF frequency bands used in a number of countries, so that the detector 1 can be used in radio mode in these countries without the need for local configuration.

Abstract: An oscillator circuit and a method of generating an oscillating signal are disclosed. An oscillator comprises a first flip-flop and a second flip-flop coupled with the first flip-flop to provide an oscillating signal. A method of generating an oscillating signal comprises providing the oscillating signal as a first clock input to a first flip flop, inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop, using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level, and using the combined output to sustain the oscillation of the oscillating signal.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An oscillator circuit and a method of generating an oscillating signal are disclosed. An oscillator comprises a first flip-flop and a second flip-flop coupled with the first flip-flop to provide an oscillating signal. A method of generating an oscillating signal comprises providing the oscillating signal as a first clock input to a first flip flop, inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop, using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level, and using the combined output to sustain the oscillation of the oscillating signal.

Abstract: A clock generator for reproducing data recorded onto an optical disk, and more particularly, an apparatus for stably generating a clock signal synchronized with an input signal and a method of generating a clock signal. The apparatus generating a clock signal includes a voltage controlled oscillator, a phase compensator, a frequency compensator, and an adder. The voltage controlled oscillator generates a clock signal of a frequency that varies with a control voltage signal. The phase compensator receives an input signal and the clock signal, detects a phase difference between the input signal and the clock signal, and generates a first control voltage corresponding to the phase difference. The frequency compensator receives the input signal and the clock signal, detects a frequency difference between the input signal and the clock signal, and generates a second control voltage corresponding to the frequency difference.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A microwave synthesizer includes a drift-cancel loop having a narrow-band input, a low-frequency comb input, a wide-band input, and an output for providing an adjustable-frequency output signal. A narrow-band synthesizer is coupled to the narrow-band input, and a comb generator is coupled to the low-frequency comb input. Instead of using a wide-band synthesizer to drive the wide-band input, as conventional topologies have done, the instant invention employs a highly stable, low noise high frequency oscillator. The output of the oscillator is mixed with the output of the comb generator to produce low-noise, high frequency combs. The low-noise, high frequency combs are then used to drive the wide-band input of the drift-cancel loop. Significant reductions in phase noise can be achieved as compared with conventional designs.

Abstract: A low-power digital frequency synthesizer combining direct digital frequency synthesis techniques with serrodyne frequency translation principles to produce a wideband frequency response with high spectral purity. A conventional direct digital synthesizer is used to generate a high-resolution analog carrier signal from a low-speed digital clock signal. The carrier signal is phase modulated by a low-resolution signal generated from a high-speed digital clock signal. The modulation signal is a higher frequency signal than the carrier signal. The phase modulation is accomplished by exact decoded gain elements. The spectral purity of the resulting high-resolution output signal is unobtainable by conventional direct digital synthesizers, while providing significant power savings.

Abstract: The frequencies of N oscillators are summed to provide a signal generator output signal. Because the phase noise power spectral densities of the oscillators add as power, the frequency summed output exhibits a noise degradation over a single oscillator of only 10 log(N). The signal generator is implemented to assure independence of the oscillator noise contributions, with phase locking the oscillators to a common frequency for ease of spurious signal control.

Abstract: A frequency synthesizer in which a PLL synthesizer 50 generates signals of frequency steps of an integer times a target frequency step. A base band generator 2 digitally generates sine wave signal components of the target frequency step. The outputs from the PLL synthesizer 50 and the base band generator 2 are cross-modulated by use of a quadrature modulator 1 to change the frequency of the output signals with a change step of the base band generator 2.

Abstract: A local oscillator system carries out a frequency switching method, in which local signals with fewer spurious components can be obtained. The local oscillator system is provided with frequency generators for generating signals with different frequencies and frequency dividers connected to the frequency generators. The dividers divide the frequency of the signals to output the frequency-divided signals while operating in an active mode and output undivided signals while the dividers are operating in inactive mode. The dividers are controlled so that one of the dividers is in the active mode and the remaining dividers are in the inactive mode. The output signals from the dividers are combined with each other to form a single output signal and then the single output signal is sent to a filter. The filter selects a component having a desired local frequency from the single output signal. Spurious components caused by unselected frequencies are removed by the filter because they are not divided.

Abstract: A selector circuit (11) generates generator polynomial information (SD) by performing a predetermined logic operation in response to a random number signal (S1). A quasi-random code generator circuit (1) outputs a quasi-random code (RP) by using a generator polynomial determined based on the generator polynomial information (SD). An exclusive-OR gate (6) scrambles an input digital signal (DI) by calculating the exclusive-OR of the input digital signal (DI) applied to its first input and the quasi-random code (RP) applied to its second input, to output a scrambled output digital signal (DO). The generator polynomial may be changed for each packet, whereby a digital signal processing system is permitted to transmit and receive the scrambled digital signal which is difficult to decode.

Abstract: A frequency synthesizer includes three subfrequency synthesizers: a first synthesizer generating a first subfrequency varying in units of a frequency step, a second synthesizer generating a second subfrequency varying in units of a frequency step being N times the first frequency step, and a third synthesizer generating a third subfrequency varying in units of the first frequency step. One output signal is obtained by mixing the first subfrequency and the second subfrequency. A second output signal is obtained by mixing the second subfrequency and the third subfrequency.

Abstract: A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits. The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler to obtain a final output frequency quadruple the ring oscillator frequency.

Abstract: A digitally controlled oscillator (100) having a first oscillator circuit (108) for providing an oscillator signal F.sub.o of a defined frequency and a digital divider (110) for dividing the oscillator signal F.sub.o by a selectable number controlled by a digital word for providing a clock signal F.sub.clk. A second oscillator circuit (104) receives the clock signal F.sub.clk and provides a low frequency signal F.sub.c. The second oscillator circuit includes a digitally controlled resonator element (112) for determining the frequency of the low frequency signal and has a center frequency dependent upon the clock signal. Circuitry (118, 120, 138) is included for providing first and second pairs of quadrature phase shifted signals derived from the clock signal F.sub.clk and the low frequency signal F.sub.c and from the oscillator signal F.sub.o, respectively.

Abstract: A differential mixer oscillator employing two transistors in a differential pair as the sustaining amplifier for a quartz crystal resonator at some first high frequency. The bias current of the differential pair is modulated at a second high frequency derived from some second frequency generating source, typically a second quartz crystal resonator, and the product terms are available at the collectors of the two transistors for selective filtering. The differential mixer oscillator may be employed in multiples, and with a variety of current sources, such as a Colpitts oscillator circuit.

Abstract: An apparatus and method is disclosed which phase locks a frequency-agile modulated output signal to any selected channel of a comb generated output. The phase error of an input signal is tracked, the input signal is modulated up to a carrier output frequency, and the modulated output frequency is locked to the comb generator output by subtracting the input signal and negating the phase error.

Abstract: A method and apparatus for generating high frequency signals, comprising generating a fundamental frequency signal over a predefined tuning range using a direct digital synthesizer with a digital to analog converter operating at a predetermined sampling frequency and mixing the fundamental frequency with a high frequency reference signal in a mixer connected to the converter and a reference source. The reference frequency signal is provided by the reference source at a high frequency which is a multiple of the digital to analog converter sampling frequency and is the difference between a desired high frequency output and the fundamental frequency. Where desired a low pass filter is disposed between the synthesizer and the mixer and a band pass filter is disposed between the mixer and any output elements. A divide by N element can be connected between the reference source and the digital to analog converter to provide a sampling clock signal for the converter.

Abstract: A frequency synthesizer system generates a clock signal having an adjustable, accurate and stable frequency. The synthesizer produces a first reference frequency FR and an adjustable first intermediate frequency F1 equal to the frequency FR divided by a selectable number (N2/N1) which permits course adjustment of the frequency in steps over a prescribed range. The frequencies FR and F1 are then mixed and filtered to produce a second intermediate frequency FR+F1. The system also generates a second reference frequency F3 which is finely adjustable over a range in the order of magnitude of the frequency difference between two successive steps of the first intermediate frequency F1. This second reference frequency is mixed with the second intermediate frequency and the result is filtered to produce a final frequency FR+F1+F3.

Abstract: A radio frequency (RF) signal generator is disclosed which generates a baseband signal at a fixed center frequency and having required modulation characteristics. The baseband signal is translated to a desired output frequency signal by mixing with a step-variable local oscillator signal. Fast frequency modulation is achieved by using a fast tuning oscillator as the source of the baseband signal. The output frequency is generated while preserving all modulation characteristics of the baseband signal and to thereby provide high performance modulation having characteristics at a fixed frequency.

Abstract: A generator circuit according to the invention generates two 90.degree. phase-shifted frequency-variable sinusoidal signals by mixing the output signal of a fixed-frequency oscillator and of a continuously variable oscillator with the aid of two multipliers operating as mixers. The fixed-frequency signal is applied to the second multiplier via a 90.degree. phase shifter. The output signal of the multipliers which contains the sum and the difference frequency of its input signals, is respectively fed to a low-pass filter or to a band-pass filter, which suppresses the sum frequency or the difference frequency respectively. By the 90.degree. phase shifter, the sinusoidal signal is phase-shifted with respect to the sinusoidal signal by exactly 90.degree.. During the continuous variation process, the signal as applied to the 90.degree. phase shifter remains stable in its frequency, whereas the output signal of the continuously variable oscillator as fed directly to the two multipliers, is changed in its frequency.

Abstract: A frequency synthesizer for adding large frequency steps to an initial frequency. A first phase lock loop divides the input frequency Fo+.DELTA.(.DELTA. being the sum of smaller frequency steps) by a rational division factor and adds to the result a standard frequency P in a fixed integral ratio with the large frequency steps to form an intermediate frequency Fi. A second phase lock loop (O.sub.S -E-G-D.sub.3 -CPF.sub.2 -FL.sub.3) multiplies the intermediate frequency by a rational factor, equal to (N+1)/D. This second loop first divides (in D.sub.3) the intermediate frequency by an integral fixed ratio D and then compares (in CPF.sub.2) the result Fi/D to a beat between the output frequency Fs and a harmonic N-Fi of the intermediate frequency.

Abstract: In a signal generator based on Direct Frequency Synthesis, a first reference frequency generator generates a signal of a reference frequency. A plurality of second reference frequency generators, respectively, generates K signals with different frequencies Asin(.omega..sub.1 t+.psi.), Asin(.omega..sub.2 t+.psi.) . . . Asin(.omega..sub.K t+.psi.), which are in phase at time point (t=0), in response to the output signal of the first reference frequency generator. A switching circuit selectively switches the output signals from the plurality of said second reference frequency generators. A timing pulse generator generates timing pulses to operate said switching circuit at time T as given by .vertline..omega..sub.i+1 T-.omega..sub.i T.vertline.=2l.pi. (l:integer) where i=1, 2 . . . K-1.

Abstract: A decimal frequency synthesizer in which, for each decade, two identical sets of four arithmetic progression frequencies are generated by programmed frequency divisions effected in parallel from a standard frequency and applied to two mixers. The first mixer further receives the frequency from the preceding decade and is followed by a divide-by-2 divider, whereas the second mixer is further receives the output of said divider and is followed by a divide-by-5 divider.

Abstract: The circuit arrangement described measures the time when a frequency F.sub.o, changing towards a desired frequency value, differs by not more than a predetermined amount (e.g. 100 Hz) from the desired value. Initially F.sub.o is mixed with the sum of 10 MHz and the new desired value for F.sub.o. The lower sideband is selected and thus produces a frequency F.sub.1 which is thus always 10 MHz when F.sub.o reaches its desired value (which may be variable). The circuit therefore has to measure when F.sub.1 comes within 100 Hz of 10 MHz. Initially F.sub.1 is multiplied by a predetermined multiplication factor (.times.100) and the product subtracted from a reference frequency. The latter is the sum of a fixed frequency of 300 KHz and of 10 GHz (i.e. 10 MHz multiplied by 100). This therefore produces an output frequency F.sub.2 whose value differs from 300 KHz by 100 Hz.times.100 (or 10 KHz) when F.sub.1 differs from 10 MHz by 100 Hz.

Abstract: A frequency generator for generating a large number of closely and evenly spaced frequencies over a large bandwidth including a first digitally controlled oscillator and a second digitally controlled oscillator, and a combiner for mixing the frequencies from said first and second digitally controlled oscillators, wherein the sampling rate of the digitally controlled oscillators differs by a small predetermined amount. Switching speed is extremely rapid.

Abstract: A frequency synthesizer described is made up of cascaded stages each receiving a 10 MHz reference. The first stage has a multiplier producing harmonics in the range 200 to 290 MHz, and any one can be selected by a controllable bandpass filter. A divide by 100 divider feeds an output variable in 100 KHz steps in the range 2 to 2.9 MHz to the next stage. This stage has a multiplier and a bandpass filter which can be set to produce an output variable in 10 MHz steps between 180 and 270 MHz. A divide by ten divider feeds a frequency in the range 18 to 27 MHz into a phase-locked loop also receiving the output from the first stage, so as to set a VCO to produce an output which, after division by a divide by ten divider is variable in 10 KHz steps in the range 2 to 2.9 MHz. Four further stages operate similarly, so that the fourth produces an output variable in 1 MHz steps between 2 and 2.999999 MHz. The seventh or final stage produces an output variable between 20 and 30 MHz in 1 Hz steps.

Abstract: A microwave frequency synthesizer utilizing a phase locked loop for generating a wide range of microwave frequencies in response to a control signal, in combination with a network including a plurality of distinct frequency local oscillators that are appropriately selectable for mixing with the signal output of the phase locked loop for translating it into a desired range, thereby expanding the effective frequency range of the phase locked loop. The combination provides a stable source of microwave frequency signals over a wide frequency range. The combination allows a simple, low cost circuit implementation and may be switched between output frequencies at a very fast speed.