Abstract: Antenna systems for receiving transmitted signals comprising at least a first tuned antenna disposed in a known relationship spatially with a second antenna, with the first tuned antenna electrically connected to the second antenna, are disclosed. The antenna system may be configured to allow the antennas to reliably discriminate between left-hand and right-hand polarized circular signals.

Abstract: A method for generating a digital signal of tunable frequency may include generating a periodic first analog signal, determining a sign of a first difference between a value of the first analog signal and a first control value to determine sign flips, wherein the first control value is a variable value, and generating the digital signal of tunable frequency on the basis of the determined sign of the first difference, wherein the digital signal of tunable frequency is generated such that a subset of switches of the signal level are coincident with a respective sign flip of the determined sign of the first difference.

Abstract: An oscillation circuit includes: a ramp voltage generating unit configured to generate a ramp voltage; and a clock signal generating unit configured to generate a clock signal. The clock signal generating unit includes: a bias unit configured to apply one of the ramp voltage and a fixed voltage, as a bias voltage, to a resistor; and an oscillator configured to determine an oscillation frequency of the clock signal in response to a bias current flowing through the resistor.

Abstract: A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.

Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.

Abstract: Frequency multipliers having corresponding methods and multifunction radios comprise: N multipliers, wherein N is an integer greater than one; wherein the multipliers are connected in series such that each of the multipliers, except for a first one of the multipliers, is configured to mix a periodic input signal with an output of another respective one of the multipliers; wherein the first one of the multipliers is configured to mix the periodic input signal with the periodic input signal.

Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).

Abstract: A periodic signal generator is configured to generate high frequency signals characterized by relatively low temperature coefficients of frequency (TCF). A microelectromechanical resonator, such as concave bulk acoustic resonator (CBAR) supporting capacitive and piezoelectric transduction, may be geometrically engineered as a signal generator that produces two periodic signals having unequal resonant frequencies with unequal temperature coefficients. Circuitry is also provided for combining the two periodic signals using a mixer to thereby yield a high frequency low-TCF periodic difference signal at an output of the periodic signal generator.

Abstract: An apparatus includes a stable local oscillator, which includes a first control loop. The first control loop includes a first voltage-controlled oscillator configured to generate a first output signal and a first phase-locked loop. The apparatus also includes a frequency up-converter configured to increase a frequency of the first output signal. The apparatus further includes a second control loop configured to receive the up-converted first output signal. The second control loop includes a second voltage-controlled oscillator configured to generate a second output signal and a second phase-locked loop. The second control loop may further include a mixer having a first input coupled to the frequency up-converter, a second input coupled to the second voltage-controlled oscillator, and an output coupled to the second phase-locked loop. A reference frequency source may be configured to generate a signal identifying a reference frequency and to provide that signal to the phase-locked loops.

Abstract: A frequency synthesizer includes: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal (2) RF having a fixed frequency, the first control device (30) controlling the frequency of the first controlled oscillator (1) on the basis of a first reference frequency; a second oscillator (3) controlled by a second control device and producing a second clock signal (4); the second control device (31) controlling the frequency of the second controlled oscillator (3) on the basis of a second reference frequency; and an integer frequency divider (5) dividing the frequency of the second clock signal (4) by a variable integer factor N1 and producing a third clock signal (6), the frequency of which is continuously variable by modifying the factor N1 and the control of the second oscillator.

Abstract: A quadrature VCO includes a first oscillator unit and a second oscillator unit. Each of the first and second oscillator unit is composed of a DC bias source, a complementary cross-coupled pair, an LC resonator unit, a frequency-doubling sub-harmonic coupler unit, and a ground terminal. When the LC resonator units of the first and second oscillator units are operated, four signals of different phases can be outputted via the output terminals. In this way, the output phase difference of the two oscillator units can keep 180 degrees and allow the two oscillator units to mutually inject signals to generate quadrature output signals.

Abstract: A system includes at least a first array connected to a second array. The first array includes an odd number, greater than one, of unidirectionally-coupled non-linear first array elements. The second array includes an odd number, greater than one, of unidirectionally-coupled non-linear second array elements. The second array elements are unidirectionally-coupled in a direction opposite the coupling direction of the second array elements. The first array is configured to receive an input signal and down-convert the input signal. The second array is configured to receive the down-converted input signal, further down-convert the down-converted input signal, and output a down-converted output signal. The down-converted output signal is down-converted to a multiple of the frequency of the input signal proportional to the number of arrays of the system. The system may operate at frequencies greater than 1 GHz and may be contained in a microchip or on a printed circuit board.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A first and a second resonator are fabricated monolithically adjacent to one another. The first resonator is the reference resonator. The resonant frequency of the second resonator is offset by a difference frequency Fo from the first resonator. Each resonator is included within an oscillator. A mixer receives the output of both oscillators. A low pass filter receives the mixer output and generates a clock signal whose frequency is equal to the difference frequency Fo.

Abstract: A circuit comprising a DC current source and at least two spin torque oscillators, the at least two spin torque oscillators being electrically coupled to each other and to the DC current source. A circuit comprising phase shifting means is connected in such a way as to cause a phase shift between current and voltage through the spin torque oscillators. An advantage is that the controlled phase shift significantly increases the tolerance for deviating anisotropy fields, which makes manufacturing of spin torque oscillator devices much more feasible in practice.

Abstract: A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: A harmonic oscillator comprises a transmission line resonator in which an oscillation frequency depends on an electrical length of a transmission line and both ends of the transmission line are electrical open ends; an active element for oscillation as a negative resistance connecting to the transmission line resonator; an output line connected to a midpoint portion of the transmission line resonator; and electrical and/or physical suppressing means for suppressing a voltage displacement distribution of second harmonic among the even-order harmonics. The suppressing means is provided at a position which is at least a minimum voltage displacement portion for the second harmonic between the midpoint portion and either ends of the transmission line resonator.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

Abstract: Certain spatio-temporal symmetries induce one array of a two-array coupled network of oscillators to oscillate at N times the frequency of the other array, where N is the number of oscillators in each array.

Abstract: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

Abstract: A CMOS single-ended frequency doubler with improved subharmonic rejection and low phase noise which allows a single ended reference signal to be utilized in a Balanced Colpitts oscillator. The input is reproduced with a 180-degree phase shift for the opposite Colpitts transistor. This is achieved by adding two PMOS transistors. One transistor is placed as a follower, which reproduces any voltage shift applied to its gate to its source. Another transistor is a matching transistor for balance. By applying the single-ended signal to the gate of the follower transistor, it is reproduced at the source. The rest of the circuit takes advantage of the summing of two period currents with a 180-degree phase shift. The present invention achieves superior performance for frequency doubling due to the squaring of the gate voltage in the corresponding drain current. As a result, the double frequency component is further enhanced.

Abstract: A clock multiplier unit (CMU) used for a high speed communications system is supplied with an input reference clock and utilizes a narrowband phase-locked loop (PLL) to multiply the reference clock to supply a higher speed output clock used, e.g., as a FIFO read clock. The narrowband PLL sufficiently attenuates jitter in jitter frequencies of interest thereby allowing a relaxation of the jitter requirement for the input reference clock. The low speed clock used to write the FIFO may also be used as the reference clock. The bandwidth of the PLL may be selectable to accommodate reference clocks with different jitter specifications. The narrowband PLL transfer function may also be used to meet overall jitter transfer function requirements.

Abstract: A phase-locked loop system and method are provided. The system may include an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem coupled to the error detector. The voltage-controlled oscillator subsystem is typically configured to produce a primary output signal that tends toward a predefined frequency relationship with the reference signal, and to produce a feedback signal that is routed in a feedback loop back to the error detector. The voltage-controlled oscillator subsystem typically includes a multiple output voltage-controlled oscillator having a plurality of VCO outputs. The voltage-controlled oscillator subsystem is typically configured to form the feedback signal from a plurality of the VCO outputs.

Abstract: In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: A frequency multiplication circuit is disclosed. The circuit includes a ring oscillator formed of an even number of phase shifting stages. Each phase shifting stage provides a high frequency output comprised of harmonics of the oscillation frequency of the oscillator. An input signal having a first frequency is injected into a feedback node of the oscillator, thereby injection locking the oscillator to the input signal such that the oscillation frequency of the oscillator is equal to the first frequency. An output signal is extracted from two of the phase shifting stages. One of the harmonic frequencies may be isolated in the output signal, thereby providing a clean output at a multiple of the input frequency. When the circuit is operated at high frequencies, the output signal consists substantially of the second harmonic frequency and the circuit operates as a frequency doubler.

Abstract: An electronic circuit generates additional clock edges from a reference clock signal utilizing switch-capacitor techniques. The electronic circuit includes a first capacitance circuit and a second capacitance circuit separated by a switch. During a first time period, the switch is open and the first capacitance circuit is charged. During a second time period, the switch is closed and at least a portion of the charge stored in the first capacitance circuit is transferred to the second capacitance circuit. The amount of charge transferred depends upon the relative sizes of the capacitance circuits. During another time period, the second capacitance circuit is discharged until its associated potential reaches a threshold level corresponding to a threshold set by a level detector. Upon reaching the threshold level, the level detector outputs a logic signal. A high frequency clock signal is produced by combining the logic signal with the reference clock signal.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: A frequency multiplier circuit outputs a desired frequency, wherein a frequency of a reference clock is divided by 4 by a frequency divider, the frequency of a unit clock is divided by 2 by another frequency divider and the output of these dividers are provided to an AND gate. A variable frequency divider divides the frequency of an output from the AND gate by n. An up-counter counts the number of pulses of the output from the variable frequency divider. Another variable frequency divider divides the frequency of the unit clock by the number of pulses to output a signal having a frequency of the reference clock multiplied by n.

Abstract: An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

Abstract: A frequency multiplier (120) having a tunable resonant circuit (122), is anticipated for use with a frequency synthesizer (100) having a Voltage Controlled Oscillator (110). The VCO control line (116) voltage establishes the VCO (110) fundamental frequency (.function.o) as well as the resonant circuit (122) center frequency, such that the resonant circuit (122) frequency response will track a desired harmonic component within the multiplier output (130) even as the VCO control line (116) voltage and the fundamental frequency (.function.o) change in response to control line variation.

Abstract: A frequency multiplier (120) having a tunable resonant circuit (122), is anticipated for use with a frequency synthesizer (100) having a Voltage Controlled Oscillator (110). The VCO control line (116) voltage establishes the VCO (110) fundamental frequency (.function..sub.o) as well as the resonant circuit (122) center frequency, such that the resonant circuit (122) frequency response will track a desired harmonic component within the multiplier output (130) even as the VCO control line (116) voltage and the fundamental frequency (.function..sub.o) change in response to control line variation.

Abstract: A pure MOS-implementable oscillator requires no trimming to make the oscillation frequency Vdd independent, but permits trimming to compensate for process and fabrication variations. A current generator creates a core reference current Iosc0, mirrored programmable trim currents, and dynamic reference voltages that do not require a constant Vdd source. A programmable delay unit provides value-programmable capacitors that receive mirrored currents A.times.(M/N).times.Iosc0, where A is a MOS channel W/L ratio constant, and M and N are integers. The currents create ramp-like voltage signals across the capacitors, the slewrate being A.times.(M/N).times.Iosc0/capacitance. A comparator unit compares the ramp-like signals, which ramp-down from Vdd, against a (Vdd-Vt) reference voltage (Vt being a MOS threshold voltage). The comparator unit outputs complementary signals that toggle a set-reset flipflop, whose output is the oscillator output signal.

Abstract: A portable emergency position indicating radio beacon (EPIRB) that transmits two signals at different frequencies whereby one frequency is twice the frequency of the other and wherein the beacon incorporates a push-push frequency multiplier to multiply the generated signal and to cancel odd and higher order even harmonics in the multiplied signal so as to improve efficiency, decrease power dissipation, improve the circuit quality factor, and decrease wave distortion. The improved frequency doubling circuitry allows for an EPIRB of reduced housing volumetric size and reduced battery size without reducing signal output power.

Abstract: An oscillation circuit has a free-running oscillator operating at a predetermined frequency. A signal generator generates a trigger signal in synchronism with an input signal. The trigger signal is supplied to the free-running oscillator to bring the signal level in the oscillator to a reference level. The oscillator keeps its frequency even when there is no input signal, the frequency being approximately equal to an integer multiplied by the frequency of the input signal.

Abstract: Disclosed is a low noise microwave frequency synthesizer having a plurality of rapidly switchable output frequencies. Two banks of oscillators are selectively mixed to yield a range of output signals of low phase noise and low spurious noise. The first bank of oscillators comprises low noise, highly stable oscillators of a frequency range below the desired synthesized output signal. The second bank of oscillators comprises low noise, highly stable oscillators of a frequency range lower than the first bank. The signal from the second bank of oscillators is frequency multiplied to a desired frequency range by a low multiplication factor and then mixed with the signal from the first bank of oscillators. Multiplied phase noise is reduced by using a low multiplication factor. The upper sideband of the mixed signals is output as the synthesized output signal. Rapid switching between oscillators in both banks provides a frequency range of synthesized output signals which may be rapidly stepped through as desired.

Abstract: The broadband injection locked oscillator system comprises a first voltage controlled oscillator having a signal output for a first signal controlled to have a first frequency in a first relatively broad frequency range, and a second voltage controlled oscillator having a signal output for a second signal controlled to have a second frequency in a second relatively broad frequency band. The output of the second oscillator is coupled to a signal input of the first oscillator to injection lock the first oscillator to the second oscillator. The second frequency is harmonically related to the first frequency when the injection lock occurs.

Abstract: A pulse oscillator circuit comprises a first pulse oscillator, which may be in the form of a monostable multivibrator, that is capable of generating a first pulse. A second pulse oscillator, which may be in the form of an astable multivibrator, is operatively connected to the first pulse oscillator and is operated for the period for which the first pulse is present. The second pulse oscillator generates a second pulse of a pulse width that is narrower than the width of the first pulse.

Abstract: A frequency converter utilizing a novel four terminal semiconductor device having an emitter grounded current amplification characteristic which is V-shaped wherein the gate terminal of the four terminal device is biased to the low point of the emitter grounded current amplification characteristic and wherein a signal which varies in time is applied to the gate terminal to cause the emitter grounded current amplification factor to fluctuate at both sides of its low point. A tuning circuit is provided in series with the emitter-collector terminals of the four terminal device and is tuned to twice the frequency of the input signal applied to the gate terminal.

Abstract: A device for generating a signal varying in frequency from 1 to 18 GHz at a onstant output power. The device utilizes a tracking automatic level loop and reacquire loop which provide automatic alignment of a YIG multiplier filter with a YIG voltage-controlled oscillator (VCO). Adjustability of output power level control is provided in the tracking automatic level loop with a provision for LED display when the device loses lock.

Abstract: A circuit arrangement for multiplying the repetition rate of an input signal by digital techniques is disclosed. A digital counter driven by a high speed clock generates a count proportional to the input period. This count or a different count generated by translating the input count is stored repetitively at the end of each input period. A second counter is used to count the same reference pulses and produce an output pulse when its count equals the stored count.Alternatively, one of the counters can be reset to a non-zero value at the end of each of its operation cycles, thus allowing a match to be reached in an appropriate output period.