Abstract: An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A quadrature oscillator with phase error correction including a local oscillator that generates a single-ended clock signal, a single-ended to differential converter that converts the clock signal to a differential clock signal, a quadrature generator that converts the differential clock signal into I and Q carrier signals, a phase error detector that measures a phase error between the I and Q carrier signals, and a feedback amplifier that modifies the differential clock signal based on measured phase error. The feedback amplifier applies the measured phase error as a DC offset to an AC differential clock signal. A transconductor converts the differential clock voltage signal into two pairs of differential current clock signals, where the quadrature generator generates I and Q current signal outputs from the two pairs of differential current clock signals.

Abstract: An oscillator circuit is provided with delay cells having supply voltage terminals and being interconnected in a ring for providing a first oscillator signal. If the delay cells have supply voltage terminals in common a second oscillator signal can derived from the respective common supply voltage terminals. The first ring oscillator signal, which is possibly available in quadrature, has a low frequency providing a low power consumption to the oscillator circuit. The two highly sinusoidal oscillator signals are generated simultaneously and have a frequency, whose ratio depends on the number of delay cells in the oscillator circuit. The oscillator circuit can be easily implemented on a limited chip area for application in transmitters/receivers operating in the GHz range.

Abstract: A digital PLL circuit is formed by a first digital PLL circuit, a signal generation circuit that generates a plurality of signals that have the same frequency as the output of the first PLL circuit but differing phases, and the second digital PLL circuit having a signal selecting circuit that can select the signals from the signal generation circuit, a frequency divider circuit that divides the output signal of the signal selecting circuit, a phase comparator circuit that compares the phase between the a signal used as a reference and the output signal from the frequency divider circuit, an up/down counter that detects the phase difference of the phase comparison circuit, and a digital filter that is provided between the up/down counter and the signal selecting circuit, the second PLL circuit selecting the signals from the signal generation circuit based on the output from the up/down counter.

Abstract: A push—push oscillator is formed by (a) a resonator circuit including a transmission line having one-half wavelength and both ends of the line being left open, and a capacitance for frequency control coupled to the transmission line in parallel, and (b) two oscillators electrically identical to each other and their input sections being coupled to both the ends of the transmission line. Further, this oscillator can take out an output signal of even-order-harmonics from a midpoint of the transmission line in a transmitting direction as well as take out two fundamental waves from respective output sections of two branch oscillators. This push—push oscillator operating with a high frequency is downsized and simplified from a conventional one. Its phase-noise-characteristics and noise immunity are also improved.

Abstract: A clock system produces a high-speed clock signal based on a low-speed clock signal inputted from the outside through the use of a frequency amplifier therein in order to thereby reduce power consumption at a clock buffer. In order to perform the above process, the clock system is composed of an external clock source for producing a clock signal having a frequency of f, a plurality of Rambus DRAMs and a controller, which are synchronized by the clock signal derived from the external clock source. By using the clock system, it is possible to reduce power consumption at the clock buffer and to decrease occurrence of a high frequency noise at a clock pin, and thus, a high qualified system design is also accomplished.

Abstract: Disclosed is a dual band wireless phone, such as a cellular phone for a mobile communications system, with a dual band transmitter that includes a phase-locked loop (PLL). The dual band transmitter includes first and second power amplifiers and the PLL. The first power amplifier has a first input for a first signal at a first radio frequency band, and a first output for an amplified first signal. The second power amplifier has a second input for a second signal at a second radio frequency band and a second output for an amplified second signal. The outputs of the power amplifiers are connectable to an antenna. The PLL generates two output frequency ranges and includes a voltage-controlled oscillator (VCO) which has a first output connected to the first power amplifier and generates a first signal. A frequency multiplier has an input connected to the first output of the VCO and a second output connected to the second power amplifier.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: a voltage tunable inductive-capacitive (LC) oscillator, a charge pump, and a phase detector. The oscillator, detector, and charge pump are coupled together to form a PLL.

Abstract: A clock generator having a ring structure and a chain structure. The ring structure is formed of an even number of serially connected distributed oscillator elements, and the chain structure is formed of an even number of serially connected distributed oscillator elements. The chain structure is coupled across an odd number of oscillator elements in the ring structure. The ring structure and chain structure, when connected together, generate a clock signal that can be extracted from any of the distributed of oscillator elements.

Abstract: A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising: a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Also, a PLL circuit for recovering a clock signal from incoming data, comprising: a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; a first pair of outputs from the sampler, for use in a phase detector (along with a reference clock of the adjacent clock signals and the incoming data), capable of producing an adjustment output.

Abstract: The present invention relates to a radio receiver, particularly to a receiver for use in single-frequency applications, such as GPS, and to a frequency generator, which may be used in such a radio receiver, or elsewhere. The frequency generator comprises a tuned circuit connected between the emitter of the transistor and ground, such that a voltage signal at the basic frequency appears on the emitter terminal of the transistor. This arrangement has the advantage that the two frequencies appear on separate ports, and provides a radio receiver including radio receiver circuitry for connection to digital signal processing circuitry, reducing the complexity of the overall circuit. Additionally, there is a radio receiver wherein separate first and second local oscillator signals are generated from the terminal of s single transistor, avoiding the need for cascade multiplication stages, again reducing the size and complexity of the overall circuit.

Abstract: It is an object to obtain a semiconductor device capable of changing a delay time of an output signal of a PLL circuit with respect to an external clock signal after installed in a system. An external clock signal is inputted to an input terminal (1.) An address value is inputted to an input terminal (3.) A decoder (9) selects one of a plurality of delay times in a voltage-controlled oscillator (8) according to the address value. The phase of a signal outputted to an output terminal (2) is delayed with respect to the external clock signal at the input terminal (1) by the delay time selected. Accordingly, it is possible to change the delay time of the output signal of the PLL circuit with respect to the external clock signal after installation in a system.

Abstract: A Pierce oscillator has been modified to replace the large capacitor with an amplifier element in order to make it more compact. A first amplifier element has a control terminal and a main current path extending between first and second output terminals. A network feeds back the signal at the first output terminal of the first amplifier to the control terminal of the first amplifier element and includes a series-arranged piezoelectric oscillation element. The oscillator also includes a reactive circuit element such as a resonant LC circuit or inductor (herein called an output dipole) coupled to the first output terminal of the first amplifier element and a DC current defining element coupled to the second output terminal of the first amplifier element.

Abstract: A method of recovering a clock signal which is embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit, first operating the data sampler circuit to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase, second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also disclosed.

Abstract: An integrated oscillation circuit used for frequency conversion circuit in which UHF frequency conversion and VHF frequency conversion are selectively energized to use a common IF amplifier. The integrated oscillation circuit is used for a local oscillation circuit. The integrated oscillation circuit including a connection terminal connected to an external resonance circuit and an input line of a mode switching signal which is set at a different level in response to an operation mode, an oscillation element, a bias terminal of which is connected to the connection terminal, a detection circuit detecting the level of the mode switching signal applied to the bias terminal of the oscillation element, and a switching circuit turning on and off a power source for driving the oscillation element in response to the level detected at the detection circuit.

Abstract: A voltage controlled oscillator operable on two widely separated frequency bands, such as 900 MHz and 1.8 GHz for example. The voltage controlled oscillator includes two negative resistance generators (32, 34) which share a common tunable tank circuit (26) and a common impedance matched combiner circuit (28) which provides the RF output (36). The VCO uses only one varactor (30) to tune both frequency bands. Separate negative resistance generators (32, 34) are used to provide optimum frequency selectivity within each frequency band.

Abstract: A voltage controlled ring oscillator (10) integrated with a phase locked loop (101) using CMOS technology. The ring oscillator (10) provides a frequency multiplied harmonic output frequency (42) at a frequency of 2.5 GHz or more while operating at only one-third of that frequency. The ring oscillator (10) uses an odd number of inverter stages (12, 14, 16) and provides high frequency CMOS operation by utilizing the phase shifted signals of the ring frequency at each ring inverter output (20, 24, 28). The ring oscillator (10) draws minimal current and is incorporated in a frequency synthesizer (100) used in a radio communication device (200).

Abstract: A circuit with a phase-locked loop circuit which generates audio clock signals with zero ppm error from reference clock signals at a reference frequency is presented. The phase-locked loop (PLL) circuit has a first programmable divider circuit connected to the circuit input terminal, a first fixed divider circuit connected to the PLL output terminal and a second programmable divider circuit connected to the first fixed divider circuit, among other elements. The circuit also has several second fixed divider circuits, each second fixed divider circuit connected to the PLL output terminal, and a multiplexer selectively connecting the second fixed divider circuits to the circuit output terminal responsive to a programmable control signal. By properly selecting the integer divisors for the fixed and programmable divisors, the circuit can generate clock signals at any one of the audio sampling frequencies from a video clock signal.

Abstract: A balanced and buffered oscillator and transmitter arrangement includes a first and second oscillator, each of which include a resonator for generating a reference signal, an amplifier for amplifying the reference signal, a resonant tank for generating an oscillating output signal in response to the amplified reference signal, and a buffer circuit for buffering the respective oscillating output signal such that the effects of a parasitic impedance are minimized.

Abstract: The present invention teaches an oscillator and transmitter. The balanced oscillator comprises a resonator for generating a reference signal having a resonating frequency, a first oscillator for providing a first oscillating output in response to the resonating frequency, and a second oscillator for providing a second oscillating output in response to the resonating frequency. The second oscillating output has a magnitude equal to the first oscillating output while oscillating 180 degrees out of phase with the first oscillating output. The transmitter comprises an antenna for radiating the first and second oscillating output signals.

Abstract: Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.

Abstract: A low noise high-frequency clock generator using a low speed voltage controlled oscillator which includes 2m differential delay elements connected in series in an inverting configuration, where m is an integer greater than 0. The output of the 2mth delay element is coupled to the input of the first delay element in a non-inverting configuration. M 2-input exclusive NOR gates are provided wherein respective input pairs are taken from positive terminal inputs of adjacent delay elements. The clock generator also includes an m-input OR gate coupled to the m-outputs from the respective m exclusive NOR gates for generating the clock generator output signal. The delay elements have a variable delay associated therewith controlled by a control delay signal DCS. Changes in the delay associated with each delay element changes the frequency of the clock generator output signal wherein the output frequency is equal to 1/(2d), where d is the time delay associated with each delay element.

Abstract: A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal.

Abstract: A balanced oscillator and transmitter circuit is provided which includes a pair of balanced Colpitts-type oscillators for generating an enhanced power radiating output signal. The balanced oscillators share a series resonance input tank. Each oscillator has an amplification stage which preferably includes a Colpitts-type configured transistor. The transmitter circuit further includes first and second output tanks having first and second radiating elements which may include a pair of inductors. An oscillating current signal is generated by the oscillator and is commonly transmitted through the pair of radiating elements. Each radiating element transmits radiating output signals which are combined and summed in total to provide an efficient radiating output signal. Alternately, the first and second output tanks may include a center-tapped transformer coupled to a third radiating element.

Abstract: A clock circuit for supplying an output clock signal to a logic circuit, includes a phase difference-to-voltage converter producing a voltage signal corresponding to a phase difference between a basic clock signal and a feedback clock signal, a voltage-controlled phase controller controlled by the voltage signal from the phase difference-to-voltage converter and outputting a first clock signal, a clock supply circuit receiving the first clock signal, and supplying a second clock signal, as the output clock signal, through to the logic: circuit, a dummy clock circuit having a dummy capacitance circuit, receiving the first clock signal, and outputting a third clock signal, and a selector selectively supplying the phase difference-to-voltage converter, with a selected one of the output of the clock supply circuit and the output of the dummy clock circuit, as the feedback clock signal.

Abstract: In a device for encoding a pulse phase difference or controlling an oscillation frequency based on delayed signals sequentially output by a delay circuit, the encoding of a pulse phase difference or the oscillation control can be simultaneously performed using a single delay device. There is provided a frequency converter including a ring oscillator consisting of inverting circuits interconnected in the form of a ring, a pulse phase difference encoding circuit for encoding the cycle of a reference signal into a binary digital value based on a pulse output by the ring oscillator, an arithmetic circuit for multiplying or dividing the binary digital value by a predetermined value to generate control data and a digitally controlled oscillation circuit for generating a pulse signal in a cycle in accordance with the control data based on the pulse output by the ring oscillator, the ring oscillator being shared by the encoding circuit and oscillation circuit.

Abstract: A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.

Abstract: To demodulate an analog signal having information modulated by a carrier, the analog signal is chopped by a chopper, the chopped signal is digitized by a sigma-delta analog-to-digital converter to produce a series of digital samples at a sampling frequency, the digital samples are filtered in a digital decimating filter to produce data words, and the data words are modulated by an intermediate frequency signal to produce a detected information signal. The various frequency signals are generated by a phase-lock loop so that the intermediate frequency is the difference between the carrier frequency and the chopping frequency, and both the chopping frequency and the intermediate frequency are sub-multiples of the sampling frequency.

Abstract: In this invention, in arranging a balance type input terminal group or output terminal group in an integrated circuit, the formation is provided with one terminal for grounding and two signal terminals adjacent to this grounding terminal on both sides. In connecting the output terminal group of the first integrated circuit and the input terminal group of the second integrated circuit with each other in such formation, the grounding terminals themselves and signal terminals themselves are respectively connected in one to one. Further, in the integrated circuit formed as mentioned above, among the bonding wires connecting the balance type input terminal group or output terminal group with an electrode group of an inner chip, the two bonding wires connecting the chip with the signal terminals are wired symmetrically with the bonding wire connecting the chip with the grounding terminal as a center.

Abstract: A voltage controlled ring oscillator whose frequency does not depend on the number of stages in the ring oscillator. The inventive voltage controlled ring oscillator comprises N inverters connected in series with the output of the Nth inverter being coupled into the input of the first inverter. The output of each inverter is connected to a transconductance amplifier. The outputs of all transconductance amplifiers are summed. The oscillation period of the circuit is 2t.sub.d, (where t.sub.d is the delay of one inverter) which is independent of the number of inverters in the ring oscillator.

Abstract: A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal.

Abstract: A circuit and method for minimizing electromagnetic emissions which employ a cancellation signal to produce electromagnetic fields which are opposites of the fields produced by the digital circuit. The circuit and method of the present invention are particularly suited for use in digital systems which produce constant-frequency and constant-amplitude clock signals for driving a circuit load. The circuit includes a cancellation circuit for producing the cancellation signal, which may include the same oscillator used to produce the clock signal. An amplitude-adjust circuit adjusts the amplitude of the cancellation signal, and a phase-adjust circuit adjusts the phase of the cancellation signal.

Abstract: A ring oscillator has a plurality of oscillator outputs, each of which carries an oscillating signal of a given frequency and thus repetition period but with a phase shift of a predetermined fraction of the repetition period from any one of the oscillator outputs to a next oscillator output in a predetermined repetitive sequence. The inputs of a selector are each connected to a respective one of the oscillator outputs. The selector includes a number of individually actuatable selector switches that are so actuated as to establish a connection between the selector output and only any selected one of the selector inputs at any time. The actuation is accomplished in a first mode, in which the selector switches maintain the connection, or in a second mode in which the selector switches intermittently index the connection in the predetermined repetitive sequence among the selector inputs.

Abstract: Electronic apparatus generates first and second output signals having a quadrature phase relationship therebetween. A local oscillator signal with a reference phase is applied as an input to first and second signal branches. The second signal branch includes a phase control circuit for subjecting input signals passing therethrough to a determined phase shift. The phase control circuit is responsive to an applied DC control signal to adjust any phase shift error through the phase shift circuit from a predetermined phase shift to assure that the second output signal exhibits the required quadrature phase relationship to the first output signal. A memory/microprocessor combination stores a digital value that is indicative of a DC control signal which must be applied to the control circuit to alter the phase shift through the phase control circuit to the predetermined phase shift. The microprocessor accesses the digital parameter and applies it to the phase control circuit through a digital to analog converter.

Abstract: A multimode oscillator is disclosed which employs a single gain loop for exciting at least two modes of a resonator to cause the oscillator to oscillate simultaneously at at least two frequencies. The multimode oscillator comprises the resonator, an amplifier to provide gain at the appropriate operating frequencies to support simultaneous oscillation at such frequencies and an equalizing network with amplitude and phase characteristics versus frequency to support the simultaneous modes of oscillation. The single loop oscillator permits separate control of the two simultaneous different frequencies of oscillation. In order to minimize thermal hysteresis, at least the active portion of the feedback loop does not include inductors. In some applications, the multimode oscillator may include one or more rejection networks to suppress unwanted oscillations. The useful outputs of the multimode oscillator are one or more of the operating frequencies, harmonics and intermodulation products.

Abstract: Generation of multiple, harmonically related frequency outputs is achieved using a digital asymmetrical harmonic waveform generator, such as a high speed digital frequency divider, for example. The digital frequency divider is used with a division ratio that provides a nonsymmetrical waveform that generates a fundamental and odd and even harmonics of the fundamental derived from a reference frequency signal. The harmonically related frequency outputs from the digital frequency divider may be buffered, filtered, and mixed with the reference frequency signal to obtain a series of clean, single frequency tones suitable for use as frequency conversion local oscillator signals. The result is a small, low power, low cost multiple frequency tone generator.

Abstract: A voltage controlled oscillator comprises a plurality of differential amplification stages each arranged to introduce a phase shift between its differential input signal and its differential output signal. The frequency at which the desired phase shift occurs can be controlled by adjusting the control signal Vc. The stages are arranged such that the output of one amplifier becomes the input to the next amplifier, making the phase shift additive. Further, a phase shift of 180.degree. may be introduced by inverting the output from one stage before inputting it to the next stage. The total phase shift introduced by the stages is 360.degree.. In this way, an oscillating signal of varying phase shift is produced at the output of each stage. Each stage comprises a standard differential amplifier, well known in the art, having a matched pair of p-channel transistors and a matched pair of n-channel transistors.

Abstract: A two-stage direct conversion receiver. A first mixer (13) converts the incoming signal to an intermediate frequency (IF) signal. A second mixer (16) converts the IF signal to a baseband signal. A detector (17), receiver logic circuit (18), and alerting device circuit (19) act upon the baseband output signal. A two port oscillator (14) provides a fundamental frequency output (FO) and a tripled output frequency (3 FO). The tripled output frequency is again tripled (9 FO) by a frequency multiplier (15) and is provided as a mixing signal to the first mixer (13). The fundamental frequency output is provided to a phase locked loop (20, 21, 22). The output frequency (FV) of the phase locked loop is doubled (2 FV) by a frequency multiplier (23) and provided to a phase shift circuit (24). The output of the phase shift circuit (24) is provided as the second mixing signal to the second mixer (16).

Abstract: A ring oscillator comprises a plurality of amplifiers connected in a multi-stage connection and each including a pair of output terminals from which first output signals are issued respectively; a pair of input terminals to which another pair of output terminals of a last stage amplifier are connected, respectively, and an amplifying circuit arranged between the output terminals and the input terminals. An oscillating signal can be generated by taking out the respectively corresponding second output signals from the amplifiers and combining these second output signals. The ring oscillator is constructed such that the second output signals are taken out from any middle output terminals in the amplifying circuit, other than the output terminals and the input terminals.

Abstract: A push-push oscillator including a resonator having a transmission line and a capacitance connected to the transmission line in parallel; an oscillating circuit responsive to the resonator for oscillating and for producing first and second outputs having an antiphase relation therebetween; an in-phase combining circuit for summing the first and second outputs of said oscillating circuit to produce a summed signal; and an antiphase combining circuit responsive to two components from the resonator having an antiphase relation for producing a differential signal in accordance with a difference between the two components. Alternatively, the in-phase combining circuit is connected to the resonator and the antiphase combining circuit is connected to the oscillating circuit. The antiphase combining circuit outputs a fundamental wave component of the resonator. The in-phase combining circuit outputs a second harmonic wave component.

Abstract: A clock producing apparatus for a D/A converter switches the clocks in accordance with the inputted sampling frequencies. A deterioration in the S/N caused by unnecessary spectra which are caused by the inputting of different sampling frequencies is prevented.The selecting operation is effected by the selecting circuit so as to obtain the selected input sampling frequencies, and at the same time, the clock signals are prevented from being inputted to the frequency dividing circuits corresponding to the input sampling frequencies which are not selected. Therefore, unnecessary spectra are prevented from being generated.

Abstract: A digital oscillator generates pairs of sampled sinusoidal signals having precisely established phase relationships, e.g., in near-perfect quadrature. The digital oscillator has first and second, interconnected multiplying-integrating modules. Each module has a multiplier for multiplying an input signal by a first coefficient, and a digital integrator for integrating the product over a period of time and thereby generating a different one of the sampled sinusoidal signals. Setting the multiplier coefficients appropriately controls the amplitudes of the generated sinusoidal signals. Likewise, the frequencies and phases of the sinusoidal signals are controlled in response to the values of the multiplier coefficients and to the period of integration. In a preferred embodiment, the first module has a delay-free-forward-path ("DFEP") integrator, and the second module uses a delay-forward-path ("DFP") integrator.

Abstract: A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits. The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler to obtain a final output frequency quadruple the ring oscillator frequency.

Abstract: A multimode oscillator is disclosed which employs a single gain feedback loop for exciting at least two modes of a resonator to cause the oscillator to oscillate simultaneously at at least two frequencies. The multi-mode oscillator comprises the resonator, an amplifier to provide gain at the appropriate operating frequencies to support simultaneous oscillation at such frequencies and an equalizing network with amplitude and phase characteristics versus frequency to support the simultaneous modes of oscillation. The single loop oscillator permits separate control of the two simultaneous different frequencies of oscillation. In order to minimize thermal hysteresis, at least the active portion of the feedback loop does not include inductors. In some applications, the multimode oscillator may include one or more rejection networks to suppress unwanted oscillations. The useful outputs of the multimode oscillator are one or more of the operating frequencies, harmonics and intermodulation products.

Abstract: A microwave voltage controlled oscillator (12) and isolation amplifiers (14, 16) are formed as a monolithic circuit on a single GaAs substrate. Only a single external inductor (34) is required to set the oscillation frequency. Optionally, an external resonator (38) may be used instead of an inductor. Off-chip active bias control (LIMin, 18) is provided for convenient frequency tuning.

Abstract: An ultra low noise oscillator circuit including a crystal and having two outputs. At the two outputs, the signal is correlated and the noise outside of the crystal bandwidth is decorrelated. Summing the two outputs in a hybrid circuit significantly reduces oscillator phase noise by almost 3 dB. In addition, these outputs can be used to perform a single oscillator noise test on the oscillator or crystal.

Abstract: An oscillator includes first and second transistors and a parallel resonant circuit. The resonant circuit has first and second ends. The first end of the resonant circuit is connected to a base of the first transistor and a collector of the second transistor. The second end of the resonant circuit is connected to a base of the second transistor and a collector of the first transistor. A voltage dropping device is connected between the first end of the resonant circuit and a power supply for providing a voltage drop to expose the first and second transistors to driving voltages lower than a voltage of the power supply.

Abstract: An oscillator is provided with an internal, high gain hysteresis effect so as to offset the linear regions of the waveform and to avoid spikes upsetting the count of a reference divider controlling the oscillator. The crystal (10) and capacitor (11) are connected between the base of one (T.sub.1) and the collector of the other (T.sub.2) transistor of a long-tailed pair, signals appearing at the collector thereof being fed via emitter followers (T.sub.5, T.sub.6) to a further long-tailed pair (T.sub.7, T.sub.8) having tapped collector resistors (R.sub.1, R.sub.2). The signal appearing at the tapping point of one of the further pair (T.sub.7) is fed to the base of a transistor (T.sub.3) whose collector-emitter resistor lies in the load circuit of one of the transistors (T.sub.1) of the first long-tailed pair.

Abstract: A crystal oscillator comprising a crsytal and an inverter amplifier which utilizes a current mirror to provide a voltage output having a frequency double the frequency of the voltage waveform present in the inverter amplifier.