Abstract: An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control.

Abstract: A phase-locked loop (PLL) circuit capable of attaining high-speed frequency transition with enhanced reliability. To this end, outputs of a reference signal source (1) and voltage-controlled oscillator (VCO) circuit (3) are frequency-divided by frequency divider circuits (2, 4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal; where the error signal does not fall within the range of a pulse width of this window signal, a level generator circuit generates a boost voltage having its potential near the control voltage value of the VCO (3) for use in generating of a target frequency.

Abstract: An improved charging pump circuit includes first, second, third and fourth switches connected together in series across an associated power supply, a first capacitor connected between the first and second switches and the ground, and a second capacitor connected between the third and fourth switches and the ground. One of the first and second switches responds to a first drive signal for turning into a conductive condition while holding the other switch in a non-conductive condition. Likewise, one of the third and fourth switches responds to a second drive signal for turning into the conductive condition while holding the other switch in a non-conductive condition. The time spent for charging or discharging the load capacitor can be substantially reduced by using the first and second capacitors whose capacitances are much smaller than the capacitance of a load capacitor, and accordingly jitter can be reduced in a PPL circuit in which the charging pump circuit is included.

Abstract: A PLL including a phase comparator, a VCO, and a charge pump further includes a reset circuit. The reset circuit detects whether both of the charge pump transistors are in an ON state, and if so, generates a reset signal which inhibits the UP and DOWN signals generated by the phase comparator. The reset circuit includes first and second detection circuits and a signal generating circuit.

Abstract: In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit.

Abstract: An improved apparatus for combining frequencies which is capable of generating a constant frequency when an external variation is applied thereto by implementing each block using a differential circuit, whereby it is adaptable to a mobile communication system, includes a phase frequency detector for comparing an input signal with a reference signal and for detecting a frequency or a phase error; a filter for differentially amplifying an output of the phase frequency detector for generating a lower frequency voltage corresponding to the error; a voltage control oscillator for generating a frequency corresponding to an output of the filter; a signal distribution unit for dividing the output of the voltage control oscillator into a predetermined times and for outputting a reference signal to the phase frequency detector; and a reference voltage generator for inputting reference voltages to the voltage control oscillator, respectively.

Abstract: A phase-locked loop (PLL) circuit has a phase comparator for comparing the phases of a local clock frequency and a reference frequency to generate a control signal indicative of a direction of adjustment of the local clock frequency for reducing the phase difference between the two frequencies. A voltage controlled oscillator (VCO) of the PLL responds to application of a control voltage thereto to generate an oscillation signal frequency from which the local clock frequency is derived. A loop filter responds to the control signal from the phase comparator to develop a control voltage for application to the VCO to adjust the local clock frequency in the direction indicated by the control signal to reduce the relative phase difference.

Abstract: A phase-locked loop employing a charge pump 7 for synthesizing RF channels permits a low supply voltage to be used by using two amplifier stages 5a, 5b, between the charge pump and a VCO4. Stage 5a may be a high impedance common emitter pair of complementary transistors allowing a wide voltage swing. Stage 5b may be an operational amplifier with resistive feedback to provide gain less than unity and a low impedance output to provide feedback around a loop filter 6 to source the current from charge pump 7 entering an inverting input of stage 5a. Alternatively, stages 5a, 5b may be reversed.

Abstract: A method and circuitry for detecting when a PLL achieves phase and frequency-lock to a reference frequency with minimal hardware and power dissipation are disclosed. The invention takes advantage of existing blocks within a PLL to reduce the amount of circuitry required while at the same time reducing error due to mismatch. In one embodiment, the present invention combines a coarse lock-detect circuit with a fine lock-detect circuit to achieve fast response when the input reference is lost, while filtering occasional minor phase hits due to external or internal noise.

Abstract: A phase-locked loop circuit for providing external clock signals to a processor is disclosed. The phase-locked loop circuit includes a phase/frequency detector, a voltage-control oscillator, and two charge pumps. The phase/frequency detector receives an input reference signal and provides a first differential output and a second differential output. The voltage-controlled oscillator has a feed-forward current input and is utilized to generate an output clock signal, wherein the output clock signal is also utilized as a feedback signal for the phase/frequency detector. The first charge-pump, coupled between the phase/frequency detector and the voltage-controlled oscillator, receives the first and second differential outputs from the phase/frequency detector and provides a differential voltage control signal for the voltage-controlled oscillator. The second charge pump is utilized to produce a stable system response by increasing the loop dumping.

Abstract: The capture range and stability of a phase locked loop are improved by adjusting the free running frequency of a voltage controlled oscillator in response to the output signal of the phase locked loop. The output signal is filtered and amplified, and then compared to a reference signal from the voltage controlled oscillator which is indicative of the free running frequency. A direct current level capture circuit compares the filtered and amplified output signal with the reference signal and generates a control signal which adjusts the free running frequency so as to equalize the output signal and the reference signal. The control signal is generated by sequentially and consecutively enabling a series of filter reset circuits. A switch control circuit controls two feedback paths between the phase detector and the voltage controlled oscillator. The first feedback path includes a low pass filter and is selected by the switch circuit for normal operation.

Abstract: A differential charge pump is provided for use with phase locked loop (PLL) circuits including a differential loop filter and a common mode bias circuit for maintaining a predetermined bias voltage value on a high voltage filter side of the loop filter. The differential charge pump includes a reference current source. First and second current mirrors are coupled to the reference current source for providing a first mirror current and a second mirror current. A first switching transistor coupled to the first current mirror receives an input UP signal conducts current from a first side of the loop filter. A second switching transistor coupled to the second current mirror receives an input DOWN signal and conducts current from a second side of the loop filter. The first and second current mirror and switching transistors are formed by N-channel metal oxide semiconductor (NMOS) devices. The differential charge pump enables a large differential output voltage with low phase error.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal.

Abstract: A phase lock loop includes a voltage controlled oscillator (VCO), a phase comparator for comparing the phases of the output of the VCO and a reference signal, a charge pump circuit, including a plurality of current sources, for supplying a control voltage by charging or discharging a capacitor based on the outputs of the current sources, and a current source controller for controlling the current output of the current sources by a n-bit current control signal. Charge current and discharge current by the charge pump circuit are controlled in n bits so that a rapid synchronization during lock-in and a low jitter after lock-in can be obtained.

Abstract: The phase-locked loop circuit provided by the present invention has a voltage-controlled oscillating circuit that has a nonlinear characteristic representing the relation between the control voltage applied to the voltage-controlled oscillating circuit and the frequency of a signal generated thereby. With a voltage lower than a predetermined voltage V1 applied to the voltage-controlled oscillating circuit, the rate of change in frequency with a change in control voltage applied to the voltage-controlled oscillating circuit is high. As a result, the loop gain of the phase-locked loop circuit can be changed at a high speed. The phase-locked loop circuit is designed so that, when a forcible pulling-in operation is started after the phase locked state is lost due to removal of an input signal, the control voltage applied to the voltage-controlled oscillating circuit is set at a low potential from the beginning in order to increase the loop gain.

Abstract: An oscillator circuit having a phase control circuit performing phase control on the oscillation signal based on a signal representing a phase difference between a signal input from outside and the oscillation output so that the oscillation frequency follows the frequency variation of the signal input from outside. The phase control circuit includes a phase shifting circuit for forming the oscillation signal into first and second signals having a phase, difference of approximately 45.degree.. The phase control circuit subtracts the second signal from the first signal vectorially to form a third signal, and also inverts the second signal to form a fourth signal. Depending on the level of the phase difference signal, the phase control circuit outputs a composite signal of either the second and third or the third and fourth signals.

Abstract: A transmitting and receiving apparatus configured in superheterodyne form, includes a receiving circuit for receiving a signal on one channel of a predetermined pair of channels and a transmitting circuit for transmitting a signal on the other channel of the predetermined pair of channels. The receiving circuit has a first voltage-controlled oscillator including a first oscillating transistor and generating a local oscillated signal used for receiving the signal on one of the channels, and a first current control means for controlling a collector current of the first oscillating transistor. The transmitting circuit has a second voltage-controlled oscillator including a second oscillating transistor and generating a signal of the frequency of the other channel, and a second current control means for controlling a collector current of the second oscillating transistor.

Abstract: A dual VCO phase-locked loop in which one VCO forms part of a standard phase-locked loop, the VCO being controlled by a loop control voltage and its output being divided and compared with an input reference signal for maintaining lock. A second VCO is indirectly controlled by the loop control voltage and tracks the output of the first VCO within .+-.5% over combined variations in power supply voltage from 3.0 V to 3.6 V, in ambient temperature from 20.degree. C. to approximately 125.degree. C., and in manufacturing process variations over 5 process corners (typical, fast-fast, slow-slow, slow-fast and fast-slow). A control current is developed for the VCO forming part of the closed loop and is coupled to the second VCO using a current mirror. An offset current is combined at the second VCO with the coupled control current. The offset current is intentionally made a compensating function of the variations in power supply voltage, ambient temperature and manufacturing process.

Abstract: Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a pre-mixer tracking filter incorporated into an emitter-coupled logic configured buffer of a carrier frequency generator, using a MOSFET-implemented current-controlled resistance component of a resistor-capacitor network and an associated current control stage. The MOSFET-implemented resistance components of the filter are controlled by the same control current that establishes the carrier generator's output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and effectively independent of process parameters.

Abstract: A phase locked loop including an in-phase detector (IPD), a quadrature phase detector (QPD), a frequency detector (FD), a squelch, a filter, and a voltage controlled oscillator (VCO). The in-phase detector has an IPD sample input, an IPD input, and an IPD output, where the IPD sample input is coupled to a data input. The quadrature phase detector has a QPD sample input, a QPD input, and a QPD output, where the QPD sample input is coupled to the data input. The frequency detector has a first FD input coupled to the IPD output, a second FD input coupled to the QPD output, and a FD output. The squelch has a squelch input, an enable input, and a squelch output where the squelch input is coupled to the IPD output and the squelch enable is coupled to the FD output. The filter has a filter input coupled to the squelch output and a filter output. The voltage controlled oscillator has a VCO input coupled to the filter output, a VCO in-phase output, and a VCO quadrature output.

Abstract: A semiconductor IC used for synthesizer having a phase locked loop PLL, a voltage controlled oscillator (VCO) and a mixer (MIX) for intermediate frequency is formed on a one chip silicon wafer. A semiconductor IC used for synthesizer having a VCO portion and an internal circuit such as PLL on a silicon wafer chip includes a differential buffer circuit which separates the VCO portion from the internal circuit. A capacitor (C1) is connected to an output of the VCO portion. A constant voltage source (V1) may be connected to respective input of the differential transistors (Q4, Q5). Transistors (Q6,Q7) provide emitter follower output circuits in the differential buffer. Respective emitters of the transistors (Q6,Q7) are connected to corresponding constant current sources (I1,I2).

Abstract: A PLL that enables smooth switching of loop bandwidth over a wide range. By switchably inserting a resistance between the output of a current-mode charge pump and a loop filter of the PLL, current sources of the charge pump are made to appear as voltage sources, and a suitably small trickle current may be obtained for wideband acquisition. During tracking, the resistance is bypassed, such that the current sources again function as current sources for narrowband tracking. More particularly, in accordance with one embodiment of the invention, a phase locked loop having a current-mode charge-pump loop filter including a current source is operated by, during narrowband operation, switching a resistive element into a current path of the current-mode charge-pump loop filter. The resistive element has a sufficient resistance to change an operating point of the current source on a V-I curve characterizing the current source.

Abstract: Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order to avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of, which is added in an adder circuit (ADD) to that coming from the first loop, for producing voltage pulses when both signals are not at the same frequency, provoking a non-locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.

Abstract: A charge pump that receives complimentary metal-oxide semiconductor (CMOS) input signals, has high noise immunity, low static error and works at low power supply voltages. The charge pump includes a current switch for receiving a control signal from a control circuit and for generating a charge signal, a loop filter having a first and second node, and a common-mode loop for sensing the charge signal from the current switch and for providing a voltage level adjustment signal to the first node of the loop filter in response thereto. The common-mode loop includes a sensing circuit for sensing the voltage level at the first and second node, an averaging circuit for producing an averaged voltage signal, a comparing circuit for comparing the averaged voltage signal to a reference signal to produce a feedback control output signal, and a feedback current source for adjusting the voltage level at the first node of the loop in response to the feedback control output signal.

Abstract: A charge pump with which a dynamic range of control voltage can be set broadly and a phase locked loop using the charge pump. The charge pump includes first, second and third transistors having respective first terminals for supplying constant currents to an output terminal. A second terminal of the first transistor is connected through a resistor to a power source. Second terminals of the second and third transistors are grounded through respective first and second T/M circuits (transmission gate analog switch circuits). A DOWN signal is applied to the first T/M circuit, and an inverted UP signal is applied to the second T/M circuit, in order to supply or draw out current via the output terminal.

Abstract: A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for detecting when the output signal of the low-pass filter in the loop has either risen to a voltage which is relatively close to the power voltage of the circuit or has fallen to a voltage which is relatively close to the ground voltage of the circuit. In either case the circuitry reverses the significance of the phase frequency detector output signals that control whether the output voltage of the low-pass filter rises or falls. Alternatively or in addition, the phase frequency detector may be reset. Coarser adjustments may be made to the loop circuit downstream from the low-pass filter in response to a recurrence of the low-pass filter output voltage reaching either of the detected voltages mentioned above.

Abstract: According to the preferred embodiment, a self-biased phase-locked loop is provided that overcomes the limitations of the prior art bias methods and apparatus. In general, a self-biased current controlled semiconductor device, typically a current controlled oscillator, is self biased by the use of a first feedback path, typically provided by a phase-locked loop, where the feedback path provides a control current for controlling the current controlled device. A second feedback path, typically a pair current mirrors, serves as a bias loop having unity gain. The bias loop provides a bias current that is responsive to the control current. This device has the advantage of being self biasing, thus no other biasing circuitry is required.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.

Abstract: A signal of a locking detector of a synthesizer indicates in a first state that a loop is locked, and in a second state that the loop is unlocked. The synthesizer may be temporarily deactivated by switching off the operating voltage of a voltage controlled oscillator by means of a switching signal. The alarm circuit of the synthesizer includes a first detector, a state of the output of which changes with a delay, in response to the change of the signal of the detector conveyed to the detector, and a second detector, the state of the output of which changes with a delay, in response to the change of the switching signal conveyed to the detector, and a device generating the alarm signal. The device provides the output signal of the alarm circuit in response to the output signals of the detectors. By selecting appropriate delay-times for the detector, it is possible to achieve the intended operation.

Abstract: An apparatus and method of increasing the voltage of a charge pump (111) used in a synthesizer charge pump network (100). The invention enables a voltage boost network (123) to be connected to a charge pump (111) and utilizes a capacitor which is charged and discharged synchronously with the charge pump to allow the charge pump (111) to effectively operate at a higher voltage than ordinary supply (V2). The invention allows the synthesizer charge pump network (100) to be operated in a low voltage condition without providing switching of external voltages greater than supply thereby eliminating EMI and increasing operating efficiency.

Abstract: A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.

Abstract: A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing.

Abstract: An RC oscillator includes an RC network for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: An active filter includes a capacitor and a resistor coupled in parallel to an input terminal; a first current conveyor coupled between the capacitor and an output terminal; a second current conveyor coupled between the resistor and the output terminal; and a second capacitor coupled between the output terminal and ground. Proportionality constants between input and output currents of the current conveyors can be adjusted to reduce capacitance in the active filter and reduce the area required to fabricate the active filter in an integrated circuit. The active filter can replace a conventional loop filter in a phase-locked loop of a data separator integrated circuit. In a phase-locked loop, the polarity of a charge pump can be reversed to compensate for current reversal by the current conveyors in the active filter.

Abstract: A timing generating circuit (9) receives a reference signal (f.sub.REF) and an operation control signal (S.sub.0) as inputs and outputs a generation control signal (S.sub.1). The generation control signal (S.sub.1) is inputted to the prescaler (31), the programmable divider (41) and a phase comparator (51). The generation control signal (S.sub.1) goes "H" when the operation control signal (S.sub.0) goes "H" and then the reference signal (f.sub.REF) is counted predetermined times, and a raw signal (f.sub.RAW) is divided to start generating a signal to be measured (f.sub.0) after the generation control signal (S.sub.1) goes "H", so that a phase difference .delta. between the reference signal (f.sub.REF) and the signal to be measured (f.sub.0) at the start is constant irrespective of the timing of the operation control signal (S.sub.0) attaining "H". Accordingly, it is not necessary to set the timing of the operation control signal (S.sub.

Abstract: A low noise amplifier (LNA)/mixer/frequency synthesizer circuit for the front end of a RF system. The LNA/mixer/frequency synthesizer circuit is fabricated as an integrated circuit utilizing 0.6 .mu.M CMOS technologies. The LNA within the circuit is provided a bias current from a power supply. Due to the CMOS construction of the LNA, a significant amount of unused power is available within the LNA. The frequency synthesizer requires the same bias current as does the LNA. The frequency synthesizer is directly coupled to the LNA, wherein the unused bias current of the LNA is used to supply the required bias current to the oscillators within the frequency synthesizer. Since the bias current used by the frequency synthesizer is drawn from the surplus of the LNA, a RF system front end is provided that has greatly reduced power requirements. The LNA is coupled to the frequency synthesizer, via an inductor.

Abstract: A phase comparator (91) makes a phase comparison between a frequency-divided signal from a frequency divider (98) and a reference oscillation signal from a reference signal oscillator (90). The phase error signal obtained from the comparison is passed through an LPF (92) to yield a frequency control signal, which is applied to a VCO (94). An oscillated signal from is frequency-multiplied by a frequency multiplier (96). The multiplied output oscillation signal SO is frequency-divided by the frequency divider (98) and output to the phase comparator (91). The multiplied output oscillation signal SO is sent out to a receiver circuit (43) and a transmitter circuit (45).

Abstract: A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, a biasing circuit for providing a bias voltage to each of the voltage controlled inverting delay cells, and a source-follower transistor for providing a control voltage to the biasing circuit and voltage controlled inverting delay cells. Each of the voltage controlled inverting delay cells includes a first and a second plurality of transistors which define two outputs of the voltage controlled inverting delay cell, and a clipper transistor connected between the two outputs to short them together whenever a difference between a bias voltage provided to a gate of the clipper transistor by the biasing circuit and a voltage on either one of the two outputs exceeds a threshold voltage of the clipper transistor.

Abstract: The voltage-controlled oscillator according to the invention has a plurality of first amplifier elements 100 and a plurality of phase correctors 101. Each of the first amplifier element 100 is provided with a pair of input signal lines, a pair of output signal lines and one or more control signal line 104 and can function as a differential amplifier and control the delay time for which a differential signal is transmitted from the pair of input signal lines to the pair of output signal lines by the control signal of the control signal line 104.

Abstract: A circuit design extending the range and linearizing the transfer characteristic of a fast voltage controlled oscillator (VCO). In addition, a multi-range VCO is described. Range extension is achieved by modifying the delay cell of a current controlled ring oscillator. The VCO transfer characteristic is linearized by piece-wise linear current control added to the delay cell. Additionally, a VCO capable of multi-range operation is provided. With the addition of multiple current sources which control booster inverter current, and by selectively enabling the additional current sources, a VCO with multiple frequency ranges can be achieved.

Abstract: In accordance with a loop open/close control signal, an analog switch closes or opens a loop including a voltage controlled oscillator, a variable frequency divider, a phase comparator, and a first loop filter, the analog switch, and a second loop filter. In order to reduce the change of frequency caused when the open loop state is set immediately after the output frequency is changed, the second loop filter uses a capacitor which shows properties of a small change of capacitance in response to an applied voltage and a small hysteresis. In another embodiment, the voltage controlled oscillator includes a second diode, one terminal of which is grounded, connected in reverses parallel to a first diode switch which switches the output oscillation frequency ranges of the voltage controlled oscillator.

Abstract: The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control

Abstract: Disclosed herein is A-phase-locked-loop PLL circuit including a voltage controlled oscillator (VCD) controlled in oscillation frequency by a control voltage, a divider dividing in frequency an oscillation signal of the VCO by a frequency division ratio to produce a frequency-divided signal, a phase comparator producing a phase comparison signal indicative of a difference in phase between a reference signal and the frequency-divided signal, and a filter converting the phase comparison signal into the control voltage to be used for controlling the VCO. The oscillation frequency of the VCO is thereby changed from a current frequency by variation of the frequency-division ratio and locked to a new frequency after a locking period of time elapses. There is further provided a control circuit which changes a time constant of the filter circuit a plurality of times during the locking period of time, this control circuit operating in response to the output of the phase comparator.

Abstract: A PLL frequency synthesizer, which comprises a voltage controlled oscillator, and a comparison frequency divider for dividing a frequency of the output signal from the voltage controlled oscillator to output a comparison signal. A phase comparator in the synthesizer compares a phase of a reference signal to be fed thereto with a phase of the comparison signal, and generates first and second phase difference signals, based on the compared result. The synthesizer further includes a charge-pump circuit operated based on the first and second phase difference signals, and having an output terminal connected to the voltage controlled oscillator. The charge-pump circuit includes a first bipolar transistor connected between a high-potential power supply and the output terminal, and a second bipolar transistor connected between a low-potential power supply and the output terminal. The first and second bipolar transistors are controlled based on the first and second phase difference signals, respectively.

Abstract: A low power clocking circuit includes a crystal oscillator for generating a digital signal having a first frequency. The first frequency is relatively slow which allows the crystal oscillator to consume reduced power. The phase detector signal is coupled to control a charge pump circuit that generates a voltage on an output node for controlling a voltage controlled oscillator. The VCO generates a clock signal having a second frequency that is higher than the first frequency. The charge pump circuit includes an active mode and a power down mode and is operatively coupled between a first supply voltage and a second supply voltage. As typically provided, the charge pump includes a capacitor network coupled to the output node for maintaining the output voltage. The charge pump includes a voltage control circuit having an up input for increasing the output voltage and a down input for decreasing the output voltage.

Abstract: A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator.

Abstract: A phase-controlled loop system having a charge pump circuit including a current mismatch measurement circuit and a current compensation circuit for equalizing the amplitude of positive current pulses and the amplitude of negative current pulses output when the phase-controlled loop system is in phase-locked condition. The current mismatch measurement circuit includes duplicate complementary current sources with characteristics and biasing substantially identical to that of the primary current sources providing the positive current and the negative current to the output node of the charge pump circuit. At the common connected node between the duplicate complementary current sources an error current is produced having an amplitude equal to the difference between the amplitude of the positive current pulses and the amplitude of the negative current pulses to the output node.

Abstract: A digital controlled oscillator (14) generates an oscillator clock that is phase locked to a reference clock. A control circuit (12) generates a reset signal from the reference clock that sets the edges of the oscillator signal in line with an edge of the reference clock. The reset signal must have correct timing and duration. A course tune detector (16, 18) monitors the oscillator clock and generates course tune control signals (CT) that adjust the reset signal pulse width and the oscillator signal frequency by adding and removing capacitors from the inverters in the control circuit and digital controlled oscillator. A phase comparator (22) compares the reference clock and the oscillator clock. A fine tune detector (20) monitors the phase comparison and generates fine tune control signals (FT) that make fine adjustments to the pulse width of the reset signal and the frequency of the oscillator signal.

Abstract: An oscillator provided with an oscillation circuit provided with two oscillation transistors comprising a differential pair and a resonance circuit connected in common to the bases of the oscillation transistors. The bases of the oscillation transistors are short-circuited by a coil, a center tap coil is connected in parallel to the resonance circuit, and variable capacitive diodes in the resonance circuit are driven by a coil connected to a mixing circuit. Due to this, it is possible to prevent the occurrence of low frequency noise, possible to realize a completely balanced operation, possible to avoid the oscillation carrier flowing into the power source and ground, and possible to reduce the noise in a television picture.

Abstract: A phase-locked variable frequency oscillator arrangement includes a voltage controlled oscillator (VCO) which is controlled by a control signal produced by charging or discharging of a capacitor in a charge pump circuit, the charge pump circuit including current sources driven by up or down command signals from a phase detector which detects the phase of the VCO output. When the command signals are simultaneously active, a logic gate circuit supplies a reset pulse to the phase detector via a delay device which is adapted to the rise times of the current in the current sources. The delay device includes a transistor (the "annexed" transistor) which forms a switched pair with one of the transistors which form the current sources. The reset signal is produced when the current of the annexed transistor reaches a selected fraction of its normal current, after being turned on by the logic gate circuit.