Abstract: In order to generate a carrier frequency Fc, a digital modulator must operate (to satisfy the Nyquist criteria) at a system sample rate Rs which is at least twice the carrier frequency Fc. However, digital modulator structures are provided herein that facilitate the use of M quadrature modulators which modulate, at a reduced modulation rate Rs/M, respective ones of M polyphase cosine elements and M polyphase sine elements with respective ones of interpolated I elements and interpolated Q elements to thereby form M polyphase modulated elements. The modulated elements are then sequentially selected in a multiplexer to form a modulated digital signal. The reduced modulation rate simplifies modulator design and lowers fabrication costs.

Abstract: A method and system for transmitting digital data by means of phase modulation is characterized in that the data are coded at the transmitting end with a code after the fashion of the Differential Manchester Code and are then phase-modulated, and in that a demodulation without phase recovery is carried out at the receiving end. The receiving-end expenditure can thereby be reduced.

Abstract: A 2N-QAM macrocell for generating constellations with 2N symbols, where N is the number of bits in the digital data word [D0:DN−1] applied to the macrocell. Since the digital data word is applied directly to the macrocell, the need for a digital mapping chip is thus eliminated thus reducing the complexity and power consumption of the circuit. An important aspect of the invention is that the 2N-QAM macrocell is amenable to being fabricated as a single microwave monolithic integrated circuit (MMIC) or integrated circuit (IC). As such, a QAM circuit can be formed from two MMICs; the 2N-QAM macrocell and a quadrature hybrid phase shifting device formed on separate MMIC to form a 2N-QAM circuit or one MMIC containing both the 0/90 degree phase shifter and the 2N-QAM circuit. The phase shifting device is used to provide the in-phase and quadrature phase components of the local oscillator signal.

Abstract: A BPSK encoder is provided with a first circuit which processes a carrier signal and a binary signal to be encoded, and produces an output binary signal having synchronous phase shifts representing a change in the value of the signal to be encoded. Also, the first circuit is provided with a sampling signal from a second circuit. The second circuit includes a delay circuit to deliver a shifted carrier signal that is smaller than the half-period of the carrier signal, and a logic gate for the logic combination of the carrier signal and the shifted carrier signal. The logic gate also delivers a binary sampling signal having at least two leading or trailing edges at each period of the carrier signal.

Abstract: A device and method capable of QPSK(Quadrature Phase Shift Keying) modulation, which up-converts a baseband signal to an IF(Intermediate frequency) signal. A phase compensator receives a digital I-signal (In-Phase signal) and a digital Q-signal (Quadrature-Phase signal) from a I/Q local signal forwarder. The phase compensator delays at least one of the received signals an amount necessary to realize a 90° phase difference between two baseband signals used to form a Quadrature Phase Shift Key output, effectively compensating for relative delays in the two baseband signals that would otherwise result in a phase difference that differs from the requisite 90° phase difference.

Abstract: There is disclosed a digital modulator whose modulation parameter can be controlled and in which modulation data or modulated signals are prevented from generating interference signals with adjoining circuits through control when power supply is turned on or system is changed. The digital modulator has a device for detecting that the power supply is turned on, and the transmission data is modulated with fixed data in response to an output of the detecting device for a time required for completing a required system constitution setting. The digital modulator also has a device for detecting the presence of the control for changing the system after the power supply is turned on. In response to an output of the detecting device, modulation is performed with the fixed data for a time from the start till the completion of the setting with a predetermined time added thereto.

Abstract: Dibits (i.e., pairs of bits) in an input data stream are converted into a modulation signal (e.g., a &pgr;/4-DQPSK modulation signal) using a technique that relies on pre-computed filter output values to reduce the processing required to generate each sample in the modulation signal. The pre-computed filter output values are stored in one or more look-up tables, which are accessed in real time during signal conversion to retrieve values as needed. In one implementation, the dibits, which are represented by complex values in a complex symbol space, are converted into two streams of state variables: one stream for the even symbols and one stream for the odd symbols. In addition, a third stream of state variables identifies whether each of the corresponding symbols is an even symbol or an odd symbol. The three streams of state variables are used to generate address pointers that are used to access the pre-computed filter output values from the look-up tables.

Abstract: A low frequency signal generating portion 1 generates a first discrete signal (a signal sampled at a first sampling rate f1). A band pass portion 2 operates at a second sampling rate f2, performs a frequency selecting operation to a second discrete signal generated when the first discrete signal generated by the low frequency signal generating portion 1 is inputted, and generates a modulated signal with a prescribed center frequency.

Abstract: A quadrature modulator with set-and-forget carrier leakage compensation. The quadrature modulator comprises an in-phase and a quadrature branch. In the in-phase and quadrature branches, real-time digital signals are converted to analog signals, the analog signals are filtered, and the filtered analog signals are modulated with a carrier signal and a ninety degrees phase shifted version of the carrier, respectively. The modulated in-phase and quadrature signals are added so as to form a quadrature amplitude modulated signal. Preferably upon powering up of the quadrature modulator, in the in-phase and quadrature branches, carrier leakage is measured. The measured carrier leakage is supplied to comparators, which toggle, when carrier leakage is minimal in the respective in-phase and quadrature branches.

Abstract: The invention concerns a modulating electronic circuit with m phase status m.gtoreq.2 comprising a distribution line (6) with n similar dephasing cells (Ci) n.gtoreq.2, each comprising a transistor supplying on a derivative output (ODi) an out-of-phase signal (SDi); a secondary switching/modulating stage (4) controlled on the basis of a control signal; means for summing in phase the signals derived the switching/modulating stage (4).

Abstract: Ramp period detecting circuit 101 outputs signal Tc that indicates the start and end of the ramp period. Two-dimensional quadrature coordinates (I.alpha.,Q.alpha.) and (I.beta.,Q.beta.) are output alternately. Coordinate accumulator 106 accumulates I.alpha. which is +1 or -1 corresponding to each odd piece of two-bit data; coordinate accumulator 107 accumulates Q.alpha. which is 0 corresponding to each even piece of two-bit data. Response waveforms from a digital lowpass filter (or rise/fall ramp waveforms) corresponding to signal Tc and outputs from coordinate accumulators 106 and 107, namely accumulated values of I.alpha. and Q.alpha., are alternately read from storage unit 112.

Abstract: An improvement in spread spectrum modulator systems, and more particularly further improvements in spread spectrum BPSK, or Binary Phase Shift Keying, Modulation systems, the present invention contemplating the utilization of an exclusive OR logic gate to replace an RF mixer stage in the SS transmitter, thereby providing enhanced gain at a lower energy consumption, with lesser cost and suppressed carrier output when compared to prior systems, as well as compatibility with CMOS low power logic modulation drive circuitry. The present system teaches a new, superior, and less costly BPSK transmitter than contemplated by the prior art, providing a less complicated system while outputting increased gain over prior art modulators.

Abstract: A modulator device is disclosed for a spread spectrum communication system which generates a modulated signal from incoming data. The device includes a QPSK portion for separating the incoming data into two data channels and for further spreading the two channels over a wide bandwidth according to a predetermined spreading code. A phase mapping element coupled to the QPSK portion for processing both channels in order to minimize spectral regrowth of the modulated signal by preventing the RF envelope deviation from going close to zero. Pulse shaping elements coupled to the phase mapping element for further processing each channel in order to improve the modulator spectral efficiency and minimize adjacent channel interference. A quad-mixer coupled to the pulse shaping elements for combining both channels into a recombined signal and for further modulating the recombined signal according to a predetermined carrier frequency.

Abstract: In an amplitude modulator, a delta sigma modulator converts a digital or analog modulation signal into a binary signal. The binary signal and a carrier signal are sent to a multiplication circuit. The phase of the carrier signal is changed to normal phase or opposite phase. The resultant carrier signal is output as an amplitude modulation wave. An orthogonal modulator sends a local oscillation signal to a phase shifter. The phase shifter outputs two carrier signals with phases which differ by 90.degree. each other. The modulation signal and carrier signals are sent to the amplitude modulator. The amplitude modulator outputs an amplitude modulation signal. These signals are sent to an analog signal composing unit. The analog signal composing unit composes the input signals and outputs an amplitude and phase modulation signal.

Abstract: A FSK modulator which uses the combination of a state machine and a toggle flip-flop to generate the FSK signals. The state machine has a loop having a predetermined number of states. The number of clock cycles that the state machine takes to traverse the loop depends on the state or level of the signal at the input to the modulator. The flip-flop converts the state machine output signal to a signal having a rectangular waveform.

Abstract: A phase modulator that generates four different kinds of phases according to input data, using a counter and an adder. There is provided a phase modulator with a serial-to-parallel data converter for converting serial data into two parallel data which are reduced by half of the clock velocity; and a digital phase signal generator for generating digital signals having a phase difference, using a counter and an adder. In this manner, the digital signals have digital values similar to sine waves having a phase difference.

Abstract: A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a ROM based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a fixed FIR filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.

Abstract: A spectrally efficient quadrature amplitude modulator comprising means for providing in-phase (I) and quadrature-phase shifted (Q) bit-streams from an input serial bit-stream, means for selectively suppressing the amplitudes of bits in the I and Q bit-streams in response to transition conditions for the I and Q signals, individual bit-shaping functions for the I and Q signals, and means for quadrature modulating a carrier signal with the I and Q signals. The resultant modulated carrier signal exhibits improved bandwidth efficiency and other desirable power spectral properties, including reduced spectral regrowth after amplitude limiting.

Abstract: A finite impulse response (FIR) filter is provided for shaping a one bit serial digital data pulse train in a digital data transmission system. The filter comprises (i) a delay element for sequentially receiving binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits representing a most recent history of the past n data bits received by the delay element during the past n data cycle intervals; (ii) a sampling element for sampling the data pulse train at a rate of m samples per bit, and (iii) a memory device having at least (n 30 m) address lines for providing at least 2.sup.(n+m) address locations. The n data bits and m samples provide an input to the address lines, the memory device in response providing a specific precomputed and stored output value for each possible combination of address line inputs.

Abstract: A .pi./4 shifted DQPSK modulator includes a mapping/filtering circuit (6) equipped with a mapping function and filtering function. The mapping/filtering circuit (6) allows phase information which is obtained for each symbol to be shift-input to its shift register (61, 62, 63) and sequentially reads out filter-processed filter factor data corresponding to 256 samples initially stored in a factor memory circuit (7) and allows the filter factor data to be converted to numerical values based on position information corresponding to 10 symbols output in parallel manner from the shift register (61, 62, 63). According to this circuit (6), it is possible to obtain filtered mapping data MF. Therefore, the modulator has less number of gates of the filter and can be embodied with a very simplified compact circuit configuration.

Abstract: A digital quadriphase-shift keying modulator is described which generates a modulated intermediate carrier frequency (IF) based on a desired number of samples for each input information bit. The design includes a ROM (or RAM) look-up table which stores digitized waveforms. The inphase and quadrature components of a complex baseband signal are translated to an IF at a multiple of the sampling rate simply by alternating the inphase and quadrature samples and alternating signs. The real IF output is produced by summing the inphase and quadrature signals.

Abstract: The preferred embodiment modem is an all hardware modulator which receives as its input two baseband drive signals, I and Q, which can come from a ROM filter or any other digital filter. Instead of storing modem responses in a ROM, multiplexers for the I and Q channels are used in combination with a control circuit to essentially perform as sine/cosine modulators for the baseband signal. The inputs into the I channel multiplexer include a non-inverted I signal, an inverted I signal, and a mid-value signal. The Q channel multiplexer has applied to it a non-inverted Q signal, an inverted Q signal, and a mid-value Q signal. Two-bit counters are applied to the control terminals of the I and Q multiplexers, where the 2-bit counters are clocked by a sample frequency. In one embodiment, the sample frequency is chosen to be four times the carrier frequency. The counter for the Q channel begins one count behind the I channel counter, thus giving a 90.degree. phase shift for the Q channel.

Abstract: A low power consumption BPSK modulator uses only a single input transformer which is not required to be center-tapped, and a switching arrangement including four junction field effect transistors. An advantage of the subject invention is that the DC switching current is reduced by a factor of approximately 1500 with respect to a conventional diode ring modulator. The carrier signal loss of the subject apparatus is lower than that exhibited by a ring modulator due to the use of only a single transformer, and due to the low on-resistance of the JFETs. An extremely important advantage of the subject invention in the field of cordless telephone handsets is that the subject apparatus can be made relatively small due to the necessity for only one transformer.

Abstract: A low power consumption BPSK modulator uses only one center-tapped transformer and a single-pole double-throw (SPDT) switching arrangement including four field effect transistors and a pair of termination resistors. An advantage of the subject invention is that the DC switching current is reduced by a factor of approximately 1500 with respect to a conventional diode ring modulator. An extremely important advantage of the subject invention in the field of handheld battery-powered communications equipment is that the subject apparatus can be made relatively small due to the necessity for only one transformer.

Abstract: A digital pulse shaping and phase modulation network is used for reducing out-of-band spectral energy. This network is used in conjunction with a NCO (numerically controlled oscillator) which includes a linear phase input port. This circuit converts rectangular data pulses into a user programmed shape. The shape pulses are then modulated onto the carrier via the linear phase port. Depending on the preprogrammed pulse shape, the out-of-band spectral energy is significantly reduced.

Abstract: A phase lock loop (PLL) circuit and method in which a PLL circuit locks on a variable input phase by providing an instantaneous phase value of a signal from an oscillator at periodic intervals, and by providing phase corrective signals to the oscillator at the same periodic intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase. The PLL circuit may also lock on a predetermined frequency by providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.

Abstract: A programmable digital modulator and methods of modulating digital data for transmission by a communication system according to operating parameters selected for various applications are provided. A two-chip system is utilized by a preferred embodiment of the invention. One chip comprises a PROM for storing impulse response data which would result from filtering the data to be transmitted. The second chip comprises a data interface for accepting input data, an address generator for generating an address of the PROM where the impulse response data is stored which corresponds to the data input to the chip and for causing the PROM to output the impulse response data stored at the address generated, and a data modulator for modulating a carrier signal with the impulse response data provided by the PROM.

Abstract: A digital DQPSK modulator according to the present: invention limits respective bands of symbol mapping data of I phase and Q phase obtained by applying differential encoding and mapping processings to a digital baseband signal, and multiplies the obtained data by the carrier signals by means of the digital filter. Such limiting of the bands and multiplication by the carrier signals are carried out by the digital filter in a time-divisionally multiplexed manner. The digital filter includes a circuit, for accumulating symbol mapping data for each of the I phase and the Q phase corresponding to a plurality of symbol sections, a plurality of ROMs corresponding to the plurality of symbol sections for storing a multiplication result of symbol data corresponding to a predetermined filter waveform and the carrier signal, and an adder for adding data output from these ROMs. The adder outputs a digital modulated signal which is, in turn, converted into an analog modulated signal by a D/A converter.

Abstract: A modulator capable of providing a fractional sample or symbol 995486 time employs a decimation counter (23) responsive to a clock having a frequency equal to M/N.times.(data symbol clock), where M is an interpolation factor and N is a decimation factor, for generating a data symbol clock to select FSK symbols from a sampled data array (21). A multiplier (26) receives the FSK symbols and multiplies the symbols by a weighting factor determined by the decimation counter. When the decimation counter wraps around due to a modulo M operation, a fractional weight is calculated for the current FSK symbol, then a new FSK symbol is selected, and then a fractional weight is calculated for the new FSK symbol. When the decimation counter has not wrapped, the full weighting, N, is output for the current FSK symbol.

Abstract: A .pi./4 shift QPSK modulator for receiving digital signals and for outputting a modulated signal therefrom in accordance with each of the inputted digital signals. The .pi./4 QPSK modulator is utilized in a communication apparatus and includes a counter for counting the number of the inputted digital signals, a phase information arithmetic unit for receiving a value of an output from the counter and a value of each of the inputted digital signals for outputting phase information of the signal to be modulated, an arithmetic unit for performing an arithmetic operation on values representing an impulse response of the output phase information from the phase information arithmetic unit and outputting impulse response values in accordance therewith, and an accumulating unit for accumulating impulse response values outputted from the arithmetic unit and for performing an arithmetic operation for enabling generation of a .pi./4 shift QPSK modulated signal.

Abstract: A method of generating a composite signal in the form of a QPSK signal on which an additional carrier signal is superposed, wherein a carrier signal is conducted through two series connected, switchable phase shifters. One of the phase shifters is controlled by one of two data signals. Both data signals are logically linked with one another by a logic circuit, and the resulting linkage signal used to control the other phase shifter. The phase states into which each phase shifter can be switched are selected and the linkage signal formed from the data signals such that, with the available values of the data signals, the carrier signal passing through the phase shifters is brought into the phase positions that should exist with the additional carrier signal superposed.

Abstract: A .pi./4 differential phase shift encoder that is implemented by simple digital logic circuits or a small number of digital signal processor instructions. The hardware logic circuit which implements .pi./4 differential phase shift encoding first converts a serial input binary data stream with a serial-to-parallel converter into two separate binary sequences. These sequences are then applied to a .pi./4 differential encoder which employs a table lookup to generate the final .pi./4 differential phase shift encoding. The software implementation of the .pi./4 differential phase shift encoding technique generates the phase shift encoded signal using tables of values based on sequences of the input serial binary data stream.

Abstract: In order to effectively reduce a memory size of each of two memories provided in an arrangement for converting a binary input data into the corresponding inphase and quadrature signals, a memory output controller and a sequential logic are provided. The memory output controller includes two polarity control circuits and two input data selectors. The two polarity control circuits are respectively coupled to the two memories, while the two input data selectors are preceded by and coupled to both of the two polarity control circuits. Each of the two polarity control circuits reverses the polarity of the output of the associated memory according to the output of the sequential logic. On the other hand, each of the two input data selectors is arranged to selectively acquire the outputs of the two polarity control circuits depending on the output of the sequential logic.

Abstract: A biphase shift keying modulation circuit includes: a clock pulse generator for generating system clock pulses; a random data generating unit for dividing the frequency of the system clock pulses to generate random digital data in synchronism with the divided clock pulses; a data conversion circuit for sequentially shifting the random digital data in synchronism with the system clock pulses and generating parallel shifted data which is multiplied by given resistive values and added to each other to provide an in-phase signal component, and for processing the shifted data and random digital data to provide a quadrature-phase signal component without a direct current component; a carrier wave oscillator for generating a carrier wave signal; and a modulating circuit for modulating the in-phase signal component and quadrature-phase signal component with the carrier wave signal and ninety degree phase-shifted carrier wave, respectively, in which the modulated signals are added to provide a phase modulated signal o

Abstract: A biphase shift keying (BPSK) modulation circuit for digital data transmission capable of preventing occurrence of signal distortion, even in phase shifting positions upon a power amplification of modulation signal, by providing a constant envelope characteristic to the modulation signal during the modulation. The BPSK modulation circuit has a clock input receiving a system clock, a data generation device connected to receive the system clock for providing random digital data in synchronization with the system clock, a data conversion device connected to receive the system clock and an output of the data generation device, for providing an in-phase signal component and a quadra-phase signal component in synchronization with the system clock, and a modulation device connected to receive both the in-phase and quadra-phase signal components from the data conversion device, for providing a phase modulation signal of constant envelope on a given carrier-wave signal for the digital data transmission.

Abstract: A CPFSK quadrature modulator (300) is disclosed utilizing an all-digital implementation. The serial data input signal (20 ) is formatted into parallel overlapping bits using a shift register (202), an up/down counter (206), and an interpolation counter (204) and applied as address lines to in-phase and quadrature-phase memories (208, 210). A multiple of the bit clock is used to address carrier generation ROMs (216, 218). The carrier signal is then modulated by the in-phase and quadrature-phase data signals (212, 214, 222), converted to an analog signal by a D/A converter (250), and low pass filtered (254) to generate the analog output signal (255). A single ROM (440) is utilized to implement all the look-up tables, multipliers, and adder. The all-digital implementation allows for precise control of the modulation index to h.dbd.0.5.+-.0.05 percent over time, temperature, power levels, etc.

Abstract: A direct digital synthesizer (DDS) includes a phase accumulator which generates phase words periodically and means for changing the phase of an RF signal. In a preferred embodiment, a DDS includes a pair of phase shifter channels having inputs and outputs coupled in parallel by make before break RF switches. The use of the dual phase shifter channels and make before break RF switches provides relatively smooth phase advance while eliminating fly-back transitions. This arrangement reduces excessive noise power in the output signal.

Abstract: A QPSK modulator has a signal generator which generates four carrier outputs having respective phases of 0.degree., 90.degree., 180.degree., and 270.degree.. A four input phase selector is connected to the four outputs of the generator, has four modulator signal inputs, and has four phase shifted carrier outputs connected to an OR gate which provides the QPSK output signal. The generator comprises a source of signals in opposite phase coupled to two frequency dividers, each divider having two outputs of opposite phase. It also has two pairs of flip-flops whose outputs form the four outputs of the generator. The signal inputs of one pair of flip-flops are connected to the outputs of the first divider. The signal inputs of the other pair of flip-flops are connected to the outputs of the second divider. Variable capacitors are provided between the clock inputs of the flip-flops and ground. A 2.sup.

Abstract: A phase modulator circuit for encoding successive serial binary digits at the zero crossing points of a sine wave carrier. A digital one is encoded as a brief phase deviation of the carrier and a digital zero as the normal wave form. The carrier frequency is one-half the clock frequency of the encoded data. A digital processing circuit operating at one-half the clock frequency of the data controls one shot multivibrators which control electronic switches to deviate the carrier.

Abstract: An improved circuit for generating phase and amplitude modulated signals in a modem. A first circuit (161) generates a first signal (163) using a 1200 Hz carrier (160) and an input data stream (162). This signal (163) is generated at the rate of 7200 samples per second. The first signal (163) is then sampled by a sampler (164) at a 3600 Hz rate (165). The sampled signal (166) contains both a 1200 Hz signal and a 2400 Hz signal. A bandpass filter (43) selects a 1200 Hz or a 2400 Hz center frequency. The resulting output (44) is a selectable 1200 Hz or 2400 Hz signal which is generated using only the data sampling points necessary to generate the first, 1200 Hz signal (163).

Abstract: A general purpose continuous phase modulator is shown which greatly reduces the amount of memory and associated hardware complexity traditionally found in continuous phase modulators. The continuous phase modulator includes a phase accumulator which calculates the phase state in an on-line real time fashion. As a result, a continuous phase modulator is provided which is adaptable to any transmitter or transceiver product requiring power and bandwidth efficiency such as those found in satellite communications equipment.