Abstract: The present invention provides a probability mass redistributor device comprising an input port and an output port. The device comprises a mapping block configured to perform a selected mapping function from a plurality of mapping functions on a random bitstream to generate an output signal having a desired probability mass function, at least one difference block, wherein the input to the at least one difference block comprises the output from the mapping block, and the output of the at least one difference block produces a modulation term, and wherein the output of each difference block is the difference between a previous value of the input signal to the block and a current value of the input signal to the block, and a summing block for summing a signal received by the input port and the modulation term to form an output signal.

Abstract: The present disclosure relates power control in wireless communications, to methods for open loop power control for setting the initial uplink transmission power for a wireless device capable of operating in multiple frequency bands. The disclosure includes methods for transmitting an uplink signal in an uplink channel of a first frequency band using an initial transmission power based on measurements of reference signals in the first frequency band when the received downlink channel is in a second frequency band not overlapping with the first frequency band. The disclosure also relates to corresponding devices and to a computer program for executing the proposed methods. Further, embodiments relating to a host computer and activities therein, are also provided.

Abstract: A fractional-N frequency synthesizer circuit is disclosed. It comprises a frequency divider circuit configured to receive a first oscillation signal having a first frequency, to receive a control word indicating a divisor, and to frequency divide the first oscillation signal with the divisor to generate a second oscillation signal having a second frequency, lower than the first frequency. It also comprises a modulator circuit configured to generate a sequence of control words to the frequency divider circuit. The modulator circuit comprises a set of memory elements configured to store an internal state of the modulator circuit in response to a first control signal and to restore the internal state of the modulator circuit in response to a second control signal, thereby enabling a time shift of the sequence of control words. A communication circuit, a communication apparatus, and a method are also disclosed.

Abstract: A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

Abstract: An injection locked phase locked loop includes an injection locked oscillator configured to generate an oscillation signal according to an injection signal and to generate a replica signal by replicating the oscillation signal when the injection signal is deactivated; a phase controller configured to generate a phase control signal according to a phase error signal; and an error detector configured to generate the phase error signal by comparing a phase of the oscillation signal and a phase of the replica signal, and to control a phase difference between the oscillation signal and the replica signal according to the phase control signal.

Abstract: A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.

Abstract: An audio FM transmitter is disclosed that may achieve high-precision frequency control as well as compact size and low cost by enabling FM modulation using a fractional-N type PLL circuit.

Abstract: A method and an apparatus provide a plurality of modulated signals by frequency shifting an output signal of a carrier signal generation circuit for obtaining a first carrier signal and a second carrier signal, and by modulating the first and second carrier signals.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Abstract: According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

Abstract: A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

Abstract: A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2), the phase information dynamic range is divided by a factor (e.g., by 2), and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator performs gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.

Abstract: Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

Abstract: A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Abstract: A radio transmitter includes a signal processing circuit splitting a basic modulating signal into first and second modulating signals and outputting the first and second modulating signals. A PLL decides a fundamental wave. A VCO forms a portion of the PLL and modulates the fundamental wave decided by the PLL in accordance with a voltage of the first modulating signal outputted from the signal processing circuit. A PLL circuit forms a portion of the PLL and varies a frequency division ratio to modulate the fundamental wave decided by the PLL in accordance with the second modulating signal outputted from the signal processing circuit.

Abstract: A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.

Abstract: A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Abstract: The present invention is a high power direct transmitter with frequency-shift keying (FSK) modulation. The transmitter implements a high power, high efficiency power voltage-controlled oscillator (VCO) which allows for production of a modulated RF signal at the final stage (ex.—right at the antenna), thereby eliminating all driving stage power amplification and frequency translation. The transmitter further provides a low SWAP-C alternative to currently available solutions.

Abstract: A method for applying a modulation signal to a phase locked loop comprises filtering the modulation signal to provide a low frequency component and a high frequency for application to respectively the feedback and feedforward paths of a phase locked loop. The high frequency component is scaled by a gain factor before being applied to the feedforward path. The low frequency component is also scaled by a gain factor and applied to the feedforward path. The energy in a common low frequency range of the modulation signal and of the loop error signal is estimated, and the gain factors are modified dependent on the measured energy.

Abstract: A phase-locked loop comprising; an oscillator configured to output an oscillating signal in dependence on the control signal at an input of the oscillator; a phase detector and loop filter configured to output a low frequency compensation signal in dependence on the output of the oscillator and a reference signal; a correlator configured to frequency correlate an interferer signal and the low frequency compensation signal, and in dependence on that correlation generate a correlation signal; and an adaptive filter configured to adapt the interferer signal in dependence on the correlation signal to output a high frequency compensation signal; and a summation unit configured to combine the low frequency compensation signal and the high frequency compensation signal to form a control signal to drive the input of the oscillator.

Abstract: A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.

Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.

Abstract: A modulator for modulating a radio frequency signal comprises a voltage controlled oscillator, a first feedback path, and a second feedback path. The first feedback path is coupled between a detector output and the voltage controlled oscillator. The second feedback path is coupled between the detector output and the voltage controlled oscillator. The detector is coupled to a divided down output of the voltage controlled oscillator and a reference clock.

Abstract: Apparatus and methods for improving the spectral performance of a polar modulator are described. A composite FM signal component of a composite polar transmit signal may be processed by monitoring the FM signal to detect a transient burst component, and, responsive to detection of a transient burst, generating a spectrally friendly replacement signal component that may be combined with the FM signal to improve spectral performance of the composite signal. In addition, an associated AM component of the composite transmit signal may be filtered to further improve spectral performance.

Abstract: In one embodiment, a cross zero best error selection system includes an error input interface, a most significant bit summation component and a multiplexer. The error input interface in coupled to a most significant bit summation component which in turn is coupled to a multiplexer. The error input interface receives a plurality of future error values. The most significant bit summation component sums most significant bits of said future error values. The multiplexer for selects error value based upon said summation of said most significant bits.

Abstract: With some embodiments, a VCO (voltage controlled oscillator) operates at an integer multiple (N) above a desired transmission frequency. In accordance with one embodiment, a chip is provided with a VCO to generate a signal and a frequency dividing circuit to provide a reduced frequency version of the signal to a transmit mixer. The transmit mixer is followed by a power amplifier that is on the same die as the VCO. The power amplifier is to generate an OFDM output transmission.

Abstract: Disclosed herein is synchronizing circuit including: a numerically controlled oscillating section; a phase rotating section; a phase error estimating section; a loop filter; and a gain controlling section; wherein the gain controlling section controls the gain so as to suppress an effect of a phase error in an immediate main signal section in a known start section from a start of the known section to a predetermined symbol.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: A phase noise correction device having a function for accurately detecting a phase noise component and capable of reducing a load on a reception device is provided. A phase noise correction device for correcting a phase noise generated in a local oscillator includes: a division section that divides a signal generated in the local oscillator; a reference signal generation section that generates a signal of the same frequency as that of the divided signal; a phase difference detection section that detects a phase difference between the divided signal and the generated reference signal; and a phase noise correction section that gives a phase rotation to a baseband signal in the direction that cancels the phase noise according to the detected phase difference as a phase noise component.

Abstract: The invention relates to a transmission module for transmitting data in the form of useful digital signals by modulation of a carrier, determined by the useful signals, by means of frequency shift keying. The transmission module contains a PLL circuit with a voltage-controlled oscillator and a controllable frequency divider with a frequency divider control input. The transmission module is designed to induce direct frequency shift keying (DFSK) of the carrier signal by appropriate triggering of the frequency divider with at least two different frequency divider control signals, and it has a modulation data preprocessing unit, which is connected to the frequency divider control input and is designed to weight samples of the same polarity of the useful signals to be transmitted and to fine tune the frequency divider control signal with regard to the frequency deviation to be induced.

Abstract: The invention relates to a method and apparatus for integrating the various circuit components controlling a voltage-controlled oscillator (“VCO”) on an integrated circuit formed on a semiconductor device. In one embodiment, the integrated circuit includes a first digital-to-analog converter (“DAC”) for receiving and converting a digital representation of the frequency modulation for the VCO to an analog form. A filter removes any conversion error from the first analog signal. A second DAC receives and converts a digital representation of the center frequency for the VCO to a second analog signal. The first and second analog signals are combined at an adder and the resulting signal is used by a bridge circuit which controls the VCO.

Abstract: A PLL circuit is disclosed that comprises a controlling unit that switches at a predetermined timing to enable/disable the phase difference signal supplied from the phase comparator to the low pass filter; and a resistor element that is disposed between a predetermined potential and a signal line for supplying the phase difference signal from the phase comparator to the low pass filter, when the phase difference signal is enabled, the oscillation circuit performing oscillation operation based on the voltage signal corresponding to the phase difference signal, when the phase difference signal is disabled, the low pass filter being supplied with the predetermined potential through the resistor element to allow the oscillation circuit to perform oscillation operation based on the voltage signal generated depending on the supplied predetermined potential.

Abstract: Apparatuses and methods for operating a modulation system using a flexible reference frequency signal are disclosed. A modulation system uses a phase-locked loop (PLL). An internal reference signal source is configured to provide an internal reference signal having an internal frequency that is substantially independent of the reference frequency. A frequency signal source is configured to provide a plurality of first samples of the frequency signal taken at a first sampling frequency according to the internal reference signal. A resampling device is configured to receive and resample the plurality of first samples to generate a plurality of second samples taken at a second sampling frequency according to the reference frequency. A loop gain compensation device is configured to receive the reference frequency and apply an offset gain to inversely offset a change in PLL loop gain responsive to a change in the reference frequency.

Abstract: Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band.

Abstract: A frequency modulator capable of performing frequency modulation without increasing quantization noise; and a method for adjusting the gain thereof are provided. An input signal is gain-adjusted by a gain adjustment section and outputted to a frequency modulation section. The frequency modulation section is gain-controlled based on a first signal. For setting a digital gain coefficient and an analog gain coefficient of the gain adjustment section, a test signal is inputted. In this state, in a generation section, first control information for setting the digital gain coefficient and second control information for setting the analog gain coefficient are generated based on information regarding a state of the frequency modulation section.

Abstract: A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

Abstract: A system and method for providing, among other things, wideband phase modulation is described. Several embodiments include a scaling network for scaling an input modulation signal in accordance with a scaling parameter and thereby generating a scaled modulation signal that is applied to a voltage-controlled oscillator of a phase-locked loop. A sensing network may also be included for detecting changes in one or more parameters characterizing the voltage-controlled oscillator. A calibration adjustment network may additionally be included for adjusting the scaling parameter in accordance with the changes in the one or more parameters.

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.

Abstract: Aspects of a method and system for direct and polar modulation using a two input PLL are presented. Aspects of the system may include generating digital signals Wn and Vn from an input data signal Un and a feedback signal Yn. The generated digital signals Wn and Vn combined may carry the information content of Un while they compensate the non-idealities of the two-input analog phase locked loop (PLL). The digital signal Wn, which may be scaled appropriately in frequency, and the digital signal Vn may be provided as inputs to the PLL. The feedback signal Yn may be a digital signal that may correspond to the analog feedback signal Pt that may be generated by the PLL. Accordingly, the PLL may be adaptively controlled via the digital signals Wn and Vn for properly transmitting the input data signal Un.

Abstract: Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a +90° or +re/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +re (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.