Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

Abstract: A transmitter including an analog front end configured to receive a serial signal; a control circuit configured to generate a first gain signal and a second gain signal based on a characteristic of a serial channel; a first amplifier is configured to amplify the serial signal to generate a first amplified signal based on the first gain signal; a first delay device configured to delay the serial signal to generate a first delayed signal; a second amplifier configured to amplify the first delayed signal to generate a second amplified signal based on the second gain signal; and at least one summer is configured to sum the first amplified signal and the second amplified signal to generate an output signal. The output signal is transmitted on the serial channel.

Abstract: The present invention refers to a signal concentrator comprising: a parallel to serial conversion device comprising a plurality of parallel inputs and a serial output, a control unit comprising detection means adapted for detecting the activity of said plurality of parallel inputs of said parallel to serial conversion device, indication means adapted for indicating the active parallel inputs to the parallel to serial conversion device and controlling means adapted for setting an operating bitrate of the serial output in function of said activity of said plurality of parallel inputs.

Abstract: In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N?1 operating mode (that serializes (N?1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.

Abstract: A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single adder. Values stored in the ROMs may produce one component of a sinusoid signal, and each of the ROMs may be of a different size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series expansion of a sinusoid function.

Abstract: Various techniques are provided for synchronizing serial data signals received by electronic systems or devices such as programmable logic devices (PLDs). In one example, a method of synchronizing data includes receiving a serial data signal at a device. The serial data signal operates independently of the device. The method also includes oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal. The method further includes filtering the samples to correct errors in the samples. In addition, the method includes extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal. Each data bit value is associated with one of the bit periods of the serial data signal.

Abstract: A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes.

Abstract: A method is provided for saving power in 1:N serializer and N:1 de-serializer by pre-loading the state of shift registers. Pre-loading the last stage of N shift registers with the last parallel data bit value in the multiplexor minimizes state changes in shift registers in the serializer. Pre-loading the 1st stage of N shift registers with the last bit data value in the previous N-bit serial data bit value in the de-multiplexor minimizes state changes in shift registers in the de-serializer. Power consumption can be significantly saved due to minimized number of state changes.

Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.

Abstract: A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter also includes a strobe generator and a number of latches. The strobe generator generates a plurality of enable signals based upon the serial clock signal. The frequency of a given enable signal corresponds to a fractional multiple of a frequency of the serial clock signal. In response to a particular respective enable signal, each of a first portion of the latches may latch and output a particular respective even data bit. Each of a second portion of the latches may latch and output a particular respective odd data bit. The serial-to-parallel converter further includes a number of output flip-flops to output the data bits in parallel in response to an output clock signal.

Abstract: A data output circuit is presented. The data output circuit includes: a data serializer and a driver. The data serializer is configured to generate serial data using first parallel data. The driver is configured to drive the serial data to generate output data. The data serializer is also configured to generate the serial data by multiplexing second parallel data generated by changing a power domain of the first parallel data.

Abstract: An apparatus for transferring serial data (e.g., a serial interface using a single wire) generally includes a detector configured to detect a first level time period and a second level time period of an input signal, and a computing unit configured to compute a duty or duty cycle of the input signal and generate an output signal based on the duty or duty cycle.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter also includes a strobe generator and a number of latches. The strobe generator generates a plurality of enable signals based upon the serial clock signal. The frequency of a given enable signal corresponds to a fractional multiple of a frequency of the serial clock signal. In response to a particular respective enable signal, each of a first portion of the latches may latch and output a particular respective even data bit. Each of a second portion of the latches may latch and output a particular respective odd data bit. The serial-to-parallel converter further includes a number of output flip-flops to output the data bits in parallel in response to an output clock signal.

Abstract: There is provided a parallel-serial converter including a selector to convert parallel data to serial data, a flip-flop to which the serial data are input so as to latch the serial data, a generator to generate replica data simulating the serial data, a detector to detect a first switching point of the replica data and a second switching point subsequent to the first switching point, and a controller to control relative timings of timing converted to the serial data in the selector and timing when the serial data is latched in the flip-flop, based on the first switching point and the second switching point.

Abstract: Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams.

Abstract: An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block.

Abstract: A parallel data output device includes a first latch circuit that latches and outputs one of at least two data signals input in parallel in accordance with a first clock signal; a second latch circuit that latches and outputs another of the at least two data signals in accordance with a second clock signal; and a phase set circuit that shifts at least one of a phase of the first clock signal and a phase of the second clock signal based on the phase of the first clock signal and the phase of the second clock signal.

Abstract: In a parallel-serial converter circuit of a multistage configuration, there is formed a clock propagation path so that when multistage connected data converters are operated according to the timing of a clock signal, a reference clock signal or a clock signal in which the reference clock signal has been frequency-converted, is given sequentially to the data converter of the first stage up to the data converter of the final stage. As a result, even in a case where variations occur in power supply voltage, timing deviation of data signals and clock signals input to the data converters of the second and subsequent stages can be suppressed, and parallel-serial conversion of high-speed data signals can be reliably executed.

Abstract: Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.

Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.

Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.

Abstract: In one embodiment, a semiconductor integrated device includes a plurality of semiconductor chips each having a first internal circuit and a second internal circuit and being stacked while displaced from each other. The first internal circuit processes a data signal in accordance with a predetermined process. The second internal circuit receives a request signal from a transmission source and determines whether the request signal is a request to itself or not. When the request signal is the request to the second internal circuit itself, the second internal circuit receives a data signal from a transmission source and outputs the data signal to the first internal circuit. When the request signal is not the request to the second internal circuit itself, the second internal circuit transfers the request signal to a transfer destination, receives the data signal from the transmission source and transfers the data signal to the transfer destination.

Abstract: A signal processing apparatus is provided, which generates a data signal having a signal waveform corresponding to a first bit value of a signal waveform transitioning from a high level to a low level or a signal waveform transitioning from a low level to a high level, a pre-transition signal level corresponding to a second bit value of one of a plurality of high levels and a plurality of low levels, and a post-transition signal level corresponding to a third bit value of the other.

Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.

Abstract: A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

Abstract: A parallel to serial conversion circuit makes output data normally swing even in a high-speed operation. The parallel to serial conversion circuit includes a main selection block configured to drive an output node sequentially in response to data on a first line and data on a second line, and a subsequent selection block configured to drive the output node sequentially in response to data on a subsequent first line and data on a subsequent second line, wherein the output node is driven by inverted data of the data on the subsequent first line and inverted data of the data on the subsequent second line.

Abstract: A data transmitting circuit that converts parallel data into serial data to output the serial data, includes a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data input port that receives second parallel data at a second data rate lower than the reference input clock, a data expansion unit that generates expanded data by expanding a bit number of the second parallel data to a bit number of the first parallel data, a serial data generation unit that performs a process for generating first serial data by performing a serial conversion on the first parallel data based on the reference input clock and a process for generating second serial data by performing a serial conversion on the expanded data, and a data output port that outputs the first serial data or the second serial data.

Abstract: The present invention relates to a serial-parallel conversion circuit of a display device. First latch circuits for sampling and latching a serial signal in accordance with sampling pulses outputted from a shift register (31) are provided in association with stages of the shift register (31). In addition, second latch circuits for latching signals outputted from the first latch circuits are provided in association with portions of the stages of the shift register (31). In this case, of all the stages of the shift register (31), the number of stages associated with the second latch circuits is less than the total number of stages of the shift register by two or more.

Abstract: Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each other, and selector circuits to receive data in parallel. In at least one embodiment, the selector circuits are responsive to the clock signals to transfer the data serially to the output line. Such apparatus and methods can also include a control unit to influence a portion of a signal that represents at least a portion of the data at the output line. Additional apparatus and methods are described.

Abstract: An all-optical combined serial-to-parallel and digital-to-analog convertor using standard WDM technology is realized. The system is based on bit interleaving and cross-gain modulation (XGM) in a semiconductor optical amplifier (SOA). The optical system can operate on multiple-bit digital words at a very high bit rate. The analog output forms series of pulses with the amplitude of each pulse taking one of the eight discrete values. A low pass filter may be used to turn this bit stream into a continuous waveform, and thus arbitrary waveforms are generated. Unlike many current digital-to-analog converter designs, which double in size with each additional bit, the design presented here allows a linear growth in components, thus making higher bit systems practical.

Abstract: A microprocessor control unit (MCU) is mounted on a printed circuit board. The MCU includes first and second clocked serial interface (CSI) circuits. The first CSI circuit is configured to serially transmit a first xCP packet to a first encoder circuit, which in turn is configured to generate an encoded first xCP packet as a function of the first xCP packet and a first clock signal. A first low voltage differential signal (LVDS) circuit is coupled to the first encoder circuit and configured to serially receive the encoded first xCP packet therefrom. The first LVDS circuit is configured to generate a first differential signal as a function of the encoded first xCP packet.

Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.

Abstract: A signal transmission system in which a serializer IC connected to first parallel signal wirings and a deserializer IC connected to second parallel signal wirings are connected by a transmission line. Among input terminals of the serializer IC, redundant input terminals which are not connected to the first parallel signal wirings are connected to one wiring obtained by branching off the first parallel signal wirings. When parallel signals are converted into a serial signal, their bit data is arranged into the serial signal which is temporally continuous. Thus, the number of transition times of the serial signal is reduced and radiation noises can be suppressed.

Abstract: A data communication network may include two or more master clocks, and a synchronization system connected to the master clocks. The synchronization system may determine a time-base for the master clocks. The synchronization system may control the master clocks according to the determined time-base. The data communication network may include one or more slave clocks. The slave clocks may be controlled by a slave clock time-base controller based on time information of a single selected master clock selected from the master clocks.

Abstract: A parallel-to-serial conversion circuit for converting pieces of parallel data into serial data, and a parallel-to-serial converting method thereof include: a shifter configured to sequentially shift an initiation signal to generate a plurality of transfer activation signals; a valid duration generator configured to define valid durations of the plurality of pieces of parallel data based on a clock and the plurality of transfer activation signals; and an output unit configured to receive the plurality of pieces of parallel data whose valid duration has been defined and to drive an output in response to a piece of data from among the received parallel data whose valid duration has begun.

Abstract: According to one embodiment, a high speed serializer for multiplexing 2N data inputs, N being a positive integer, comprises one less than 2N multiplexing cells arranged in N stages. The stages are numbered 1 through N, and the output of the Nth stage is a serial transmission and the inputs of the 1st stage are the 2N data inputs. Each stage comprises half as many multiplexing cells as the preceding stage. Additionally, each multiplexing cell comprises a multiplexer that comprises a pair of inputs and an output. 2N-2 of the multiplexing cells in the first stage further comprise a latch, and the output of the latch is coupled to an input of the multiplexer.

Abstract: A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flop of a next stage. A second D-type flip-flop receives one bit of enable control signal, and the output of each of the second D-type flip-flops connects to the input of a second D-type flip-flop of a next stage. A multiplexer contains two input terminals and an enable control signal receiving terminal, wherein one input terminal is used to receive the input data received by the first D-type flip-flop, and the enable control signal receiving terminal receives the enable control signal received by the second D-type flip-flop. A D-type latch outputs the data, and the output data is fed back to another input terminal of the multiplexer so as to be selected as a data output when a next set of data are input.

Abstract: In one embodiment, a method and apparatus for shifting the bits of a data word are disclosed. For example, a deserializer according to one embodiment includes an input register bank for capturing serial data comprising n bits, an intermediate register bank, and a strobe mux coupled to an input of the intermediate register bank. An input of the intermediate register bank is coupled to an output of the input register bank. The strobe mux comprises a single multiplexer configured to select a bitslip strobe signal that controls an order in which the n bits of the serial data are captured in the intermediate register bank.

Abstract: A physical layer (PHY) device including a first encoder, a second encoder, and a selector. The first encoder is configured to receive a first data stream at a first data rate, encode the first data stream using a first type of encoding, and output a first encoded data via a plurality of outputs. The second encoder is configured to receive a second data stream at a second data rate, encode the second data stream using a second type of encoding, and output a second encoded data via an output. The selector includes a first set of inputs and a second set of inputs. The first set of inputs is configured to receive the plurality of outputs of the first encoder, and each input of the second set of inputs is configured to receive the output of the second encoder.

Abstract: A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal.

Abstract: A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.

Abstract: Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.

Abstract: The present invention relates to a serial-parallel conversion circuit of a display device. First latch circuits for sampling and latching a serial signal in accordance with sampling pulses outputted from a shift register (31) are provided in association with stages of the shift register (31). In addition, second latch circuits for latching signals outputted from the first latch circuits are provided in association with portions of the stages of the shift register (31). In this case, of all the stages of the shift register (31), the number of stages associated with the second latch circuits is less than the total number of stages of the shift register by two or more.

Abstract: A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the multiple channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal. The serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the multiple channels.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.

Abstract: An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block.

Abstract: A method of encoding data structures using compressed object encodings during serialization. A compressed representation of the data is generated directly while encoding. Serialization means converting a data structure to a string of bytes for external storage or communication.

Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.