Abstract: Properties and the construction method of Orthogonal Differential Vector Signaling Codes are disclosed which are tolerant of order-reversal, as may occur when physical routing of communications channel wires causes the bus signal order to be reversed. Operation using the described codes with such bus-reversed signals can avoid complete logical or physical re-ordering of received signals or other significant duplication of receiver resources.

Abstract: Provided is a method of wireless communication which includes selecting a codebook from a plurality of codebooks in accordance with an antenna characteristic, and transmitting an indication of the selected codebook. Each of the plurality of codebooks is associated with one of a plurality of antenna characteristics. In some designs, channel state information is received from a user equipment. The channel state information may be used to determine downlink scheduling and/or precoding. In some designs, the channel state information may include feedback elements associated with different subband granularity. The feedback elements may also indicate a selection of a subset of precoder column vectors and/or a phase offset between two groups of transmit antennas.

Abstract: Properties and the construction method of Orthogonal Differential Vector Signaling Codes are disclosed which are tolerant of order-reversal, as may occur when physical routing of communications channel wires causes the bus signal order to be reversed. Operation using the described codes with such bus-reversed signals can avoid complete logical or physical re-ordering of received signals or other significant duplication of receiver resources.

Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.

Abstract: Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to serial conversion circuit that acquires M1 and M2 bits of the bit-swapped parallel data in a first and a second mode, respectively. The parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order in the second mode The bit-swapping circuit swaps the bits of the input parallel data such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in the same order.

Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.

Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.

Abstract: A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams (such as changing a first code to a predefined code); and combining at least two of the plurality of encoded serial data streams into a single data stream.

Abstract: A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

Abstract: ACARS systems and methods for compiling messages includes a processing device configured for mapping eight-bit characters in an eight-bit character stream into a six bit map to create a generally six-bit character stream. The processing device is further configured for encoding the generally six-bit character stream into an eight-bit character stream. Optionally, the processing device includes a look-up table configured to retrieve substituted six-bit characters in response to the presence of the eight-bit character received at a processor.

Abstract: A method for communication between a sender and a receiver, including receiving data in the form of an M-of-N code, where the M-of-N code includes a first component of length n1 and a second component of length n2; decoding data in which the first component is an m1-of-n1 code and the second component is an m2-of-n2 code; and decoding data in which the first component is an m3-of-n1 code where m1?m3 and the second component is an m4-of-n2 code where m2?m4.

Abstract: A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+? with bit count N is longitudinal-lateral converted into a data signal of time slot count N with bit count N+?. so as to create a null time ? and a control signal is inserted into the null time ?, thereby converting the parallel signal containing the data signal and the control signal into a serial signal for transmission.

Abstract: In a data arrangement of a CD-ROM format, data in which DSV control data cannot be placed due to a restriction on the format is followed by control data of two bytes. Main data in which any data cannot be placed is followed by a special control data sequence of two bytes. As a result, after a data sequence of which it is unknown whether the start bit is plus or minus, the sign of the start bit of a diverging control data sequence preceded by the special control data sequence can be kept constant. Consequently, DSV values can be deviated in one direction.

Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract: A method of encoding digital information in order to suppress dc includes the steps of receiving a sequence of m message bits of a message word, and mapping the sequence of m message bits of the message word to a codeword, of length n bits, generated from the m message bits using algebraic operations. Multiple codeword candidates are generated from the m message bits using the algebraic operations to combine the m message bits with different periodic scrambling sequences. One of the codeword candidates is selected for mapping based upon an optimizing criteria. Second order digital sum sequences, corresponding to each of the plurality of codeword candidates, can be used as the optimizing criteria to select the codeword.

Abstract: A method and a system for compensating for a permutation of L pairs of cable such that the compensation is localized in a trellis decoder of a receiver. The L pairs of cable correspond to L dimensions of a trellis code associated with the trellis decoder. The trellis code includes a plurality of code-subsets. The permutation of the L pairs of cable is determined. A plurality of sets of swap indicators based on the permutation of the L pairs of cable is generated. Each of the sets of swap indicators corresponds to one of the code-subsets. The code-subsets are remapped based on the corresponding sets of swap indicators.

Abstract: A method of coding data for communication within a network. The method includes receiving an 8b/10b source protocol data stream containing 10-bit code and translating the data stream into an 8-bit code by converting the 10-bit code into 8-bit data and an ordered set. The method further includes transmitting the 8-bit code.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A method for recovering a data required to have n consecutive and repetitive bits is disclosed. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having n−1 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the n−1 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits. In addition, a device for recovering a data to be decoded is also disclosed.

Abstract: An optical transmission system and optical transmission devices in the optical transmission system that can achieve a high quality transmission using considerably simple arrangements are disclosed. At a transmitting-end optical transmission device, encoding means having n outputs, forms k data by aligning phases of data on k channels with each other and for generating (n−k) error correction bits for said k data and adding said (n−k) error correction bits to said k data, and wavelength-multiplexing means connected to the encoding means, converts both said k data and said (n−k) error correction bits ton optical signals having different wavelengths and for wavelength-multiplexing said n optical signals so as to be delivered to the optical transmission line.

Abstract: An improved thermometer-to-binary coder in which the bits of the thermometer code are used to directly generate the binary code without using an intermediate one-hot code.

Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N−1 (from unclipped numbers in a range of −0.5N to (1.5N−1)), where N is 2m and m is the bit length of the desired clipped and quantized number. The most significant bit of the unclipped data value indicates whether an overflow of the permitted range has occurred and that clipping is required. The next most significant bit (m−1th) indicates which saturated value should be adopted. These properties of the unclipped data value may be exploited to generate the desired clipped and quantized numbers using logical left shifting and conditionally executed saturating instructions executing upon a general purpose processor 24. The shifting operations performed to achieve saturation operation may simultaneously yield quantization.

Abstract: A method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, a device for encoding, a signal, a record carrier, a method for decoding, and a device for decoding. The signal is constructed by repetitively or alternately using channel codes C1 and C2. Since two channel words with opposite parities are available in the channel code C2 for each information word, and the same state is established, predetermined properties of the constrained binary channel signal can be influenced. Since the method further comprises the step of substituting, in dependence upon a value of a predetermined property of the binary channel signal, a channel word for a substitute channel word, wherein the substituted channel word and the substitute channel word establish the same state, predetermined properties of the constrained binary channel signal can be further influenced.

Abstract: The present invention describes a system and method for encoding a sequence of 64 bit digital data words into a sequence of 65 bit codewords having constraints of (d=0, G=11/I=10) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64-bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword. A corresponding decoding method is also described. A byte shuffler may be used in the processing.

Abstract: Disclosed is transmission of a signal over a single interconnect between functional blocks of the IC. A scaled or encoded signal responsive to a first digital signal is generated by summing currents responsive to the first control signal. The summed currents, which may be the sum of one or more currents, is the scaled signal. The encoded signal is transmitted over a single interconnect. This transmission occurs in one clock period in contrast to the at least two clock periods required to serially transmit data. The encoded signal is then used to generate a second digital signal. The generation of the second digital signal preferably includes mirroring the current of the encoded signal. The mirrored current is can then generate one or more separate voltages which are used to generate the second digital signal.

Abstract: Satellite identification data generated when using the Reduced Order GPS (ROGPS) system are compressed, allowing for shorter data transmission times, reduced transmitter energy and reduced satellite channel occupancy. An indexed list of all possible constellations of a subset of all satellites is created. This list is then used at both the tracked object location and the central station to which the satellite identifications must be sent. At the tracked object location, the chosen satellite GPS indices are identified and the list index is found, encoded, and transmitted with only enough bits to uniquely identify it from all other indices in the list. At the central station, the received list index is used to find the satellite constellation corresponding to the chosen satellite GPS indices. The number of bits used to encode the index can be further reduced by reducing the indexed list size.

Abstract: A data conversion circuit and method are disclosed for converting an N-bit data stream to an M-bit data stream. A FIFO memory device having multiple N-bit memory locations receives as an input consecutive N-bit sets of data and stores each consecutively received N-bit set of data in consecutive memory locations. A write pointer identifies a next available memory location at which the next N-bit set of data is to be stored. A first read pointer identifies a first memory location containing a first portion of a first M-bit set of data. A second read pointer identifies a second memory location containing a last portion of the first M-bit set of data. Provided as the first M-bit set of data are each of the N-bit memory locations between and including the memory location identified by the first read pointer and the memory location identified by the second read pointer.

Abstract: A coding circuit forming a 1-from-N code from an X-from-N code includes partial circuits in which each position of the X-from-N code forms an input value of a partial circuit. Each partial circuit is formed of three emitter-coupled transistor pairs, a current source connected to reference potential, level shift circuits, signal outputs and a symmetrical signal input. Each partial circuit is connected to the partial circuit with the next higher position of the X-from-N code as an input value and to the partial circuit with the next lower position of the X-from-N code as an input value.

Abstract: An information-transmission system including an encoder for converting n-bit information words (D7, . . . , D0) into transmitted m-bit code words (C10, . . . , C0), and a decoder which reconverts the received code words (C'10, . . . , C'0) into information words (D*7, . . . , D*0) corresponding to the original information words. For a first group the encoder converts a first portion (D7, . . . , D3) into a first portion of a code word, such portion comprising q bits (C10, . . . , C5) thereof; and converts a second portion (D2, . . . , D0) of the information word into a second portion of the code word, such portion comprising s bits (C4, . . . , C0) thereof. For a second group the encoder converts a first portion (D7, . . . , D3) into a second portion comprising q bits (C'5, . . . , C'0) of a code word, and converts a second portion (D2, . . . , D0) of the information word into a first portion comprising s-bits of (C'10, . . . , C'6) such code word.

Abstract: A method and apparatus for generating signals representing a plurality (p) of n bit words corresponding to respective input signals. The apparatus comprises a basic word generator (7) for generating first signals representing m basic words (A-D) whereby the p words are the same as or are cyclic rearrangements of the n bits of the m basic words. Control means including combinatorial logic (33) determines the one of the p words corresponding to each input signal and generates corresponding control signals. Selection means including optical modulators (10-13, 20-25) are responsive to the control signals for selecting the appropriate first signal, if necessary after recycling by imposing selected delays, to constitute an output signal corresponding to the determined one of the p words.