Abstract: The invention relates to a method and an apparatus for automatic tuning of an impedance matrix, for instance the impedance matrix seen by the power amplifiers of a radio transmitter using a plurality of antennas simultaneously. The apparatus has 4 user ports and 4 target ports, and comprises: 4 sensing units; a signal processing unit which estimates real quantities depending on the impedance matrix presented by the user ports, using the sensing unit output signals obtained for 4 excitations applied to the user ports, two or more of the excitations being applied simultaneously, the signal processing unit delivering a tuning instruction; a multiple-input-port and multiple-output-port tuning unit comprising adjustable impedance devices; and a tuning control unit receiving the tuning instruction and delivering tuning control signals to the multiple-input-port and multiple-output-port tuning unit, the reactance of the adjustable impedance devices being mainly determined by the tuning control signals.

Abstract: A device for detecting the state of a switch. The device includes a detection circuit which delivers a signal of specified value (Vpullup) when the value of an electrical quantity (RSw) characterizing the state of the switch is less than a threshold called the lower threshold (Rclosed) and/or a signal of different value when the value of the electrical quantity is greater than a threshold different from the lower threshold, called the upper threshold (Ropen). The disclosed embodiments also concern flight control systems, in which the device is implemented, and the aircraft including the systems.

Abstract: An error reduction apparatus includes a combing absence detector to detect absence of combing from a luminance signal, a combing presence detector to detect presence of combing from a color-difference signal, a vertical low-pass filter to receive the color-difference signal, and a selector to select one of the color-difference signal and a color-difference signal to which the vertical low-pass filter is applied based on detection results of the combing absence detector and the combing presence detector, and if combing is absent in the luminance signal and combing is present in the color-difference signal, the error reduction apparatus applies the vertical low-pass filter to the color-difference signal and outputs the signal.

Abstract: A computer-implemented method to decode a digital signal includes following steps. A micro control unit (MCU) receives a digital signal. The MCU reads a low voltage period of the digital signal and stores a time duration of the low voltage period into a first register as a value TL. The MCU reads next high voltage period of the digital signal and stores a time duration of the high voltage period into a second register as a value TH. The MCU reads the value TL of the first register and the value TH of the second register, and computes a ratio TR=TH/TL. The MCU compares the ratio TR with two predetermined values M and N, if TR=M, the decoded result is a logical “1.” If TR=N, the decoded result is a logical “0.

Abstract: A system and method for efficiently performing a pattern matching procedure includes an enrollment manager that performs an image conversion procedure for converting an initial reference image into a reference template. The image conversion procedure may include at least one of a binarization procedure and a symmetrical reduction procedure to more efficiently utilize system resources such as processing requirements and memory requirements. A verification manager may then convert an initial test image into a transformed test image for combining with the foregoing reference template to produce a correlation image. The verification manager then analyzes matching characteristics of the correlation image to determine whether the initial test image matches the initial reference image.

Abstract: An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising steps consisting of decomposing the executable code into words; compressing each word of executable code, each compressed word of executable code comprising a part of predefined fixed length and a part of variable length whereof the length is defined by the part of fixed length; and combining all the parts of fixed length and all the parts of variable length of the words respectively into a block of parts of fixed length and in a block of parts of variable length, the respective positions of at least certain parts of variable length in the block of parts of variable length being saved in an addressing table.

Abstract: A fixed-size codeword table is generated for decompressing GIF encoded data. The fixed-size codeword table is defined to store a codeword string and a codeword length for each of a number of codewords. The codeword string is defined by a codeword previously represented in the codeword table and a character. The codeword length represents a total number of characters in the codeword string. A current codeword in the GIF encoded data is translated according to the codeword table to generate a series of characters represented by the current codeword. The generated series of characters is stored in a computer memory space.

Abstract: A method and system for decoding a biphase-mark input stream is disclosed. Aspects of the present invention include receiving an external biphase-mark input stream by a receiver module; recovering timing information from the input stream; decoding the input stream to generate decoded data and storing the decoded data in a data buffer; reading, by an audio out module, the decoded data from the data buffer at a rate determined by a programmable clock; using the timing information from the receiver module to calculate a sampling frequency of the input stream; and adjusting a frequency of the programmable clock to substantially match the sampling frequency so that the audio out module reads the decoded from the buffer at substantially the same rate that the receiver module inputs the decoded data into the data buffer.

Abstract: A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code a decimal digit is binary bits and 1 decimal digit is 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

Abstract: A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code 2 decimal digits to 7 binary bits, and 1 decimal digit to 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

Abstract: An apparatus for converting a multidigit decimal number into a binary number. In a preferred embodiment, the apparatus includes a register for holding the multidigit decimal number; first conversion logic, coupled to the register, for simultaneously converting a first pair of decimal digits in the multidigit decimal number, into a first binary representation and second conversion logic, coupled to said first conversion logic and the register, for simultaneously converting a second pair of decimal digits in the multidigit decimal number and the first binary representation into a second binary representation of a decimal number defined by the first and second pair of decimal digits.

Abstract: A numeric encoding method and apparatus for neural networks, encodes numeric input data into a form applicable to an input of a neural network by partitioning a binary input into N-bit input segments, each of which is replaced with a code having M adjacent logic ones and 2.sup.N -1 logic zeros, the bit position of the least significant of the M logic ones corresponding to the binary value of the input segment it replaces. The codes are concatenated to form an encoded input. A decoding method decodes an output from the neural network into a binary form by partitioning the output into output segments having 2.sup.N +M-1 bits each, each of which is replaced with an N-bit binary segment being a bracketed weighted average of the significances of logic ones present in the output segment. The binary segments are concatenated to form a decoded output.

Abstract: Dedicated convert hardware is disclosed for performing bidirectional conversions of numbers between binary and another base b (illustratively decimal) for use in a data processing system. The dedicated convert hardware comprises a special purpose multiply-and-add unit and a convert register. The output of the multiply-and-add unit is coupled to the input of the convert register, and the output of the convert register is recycled to the inputs of the multiply-and-add unit. The multiply-and-add unit is hardwired to multiply the input by b and concurrently add the value at a separate digit input. Means are also provided for initializing the convert register with zero or with any desired number.