Abstract: A digital background calibration circuit including a digital random number generator, an analog-to-digital converter (ADC) and a plurality of switches is provided. The digital random number generator is configured to generate a first digital sequence having a plurality of bits. The ADC includes a plurality of sampling capacitors. The switches receive the first digital sequence and are coupled to the sampling capacitors. During a calibration period, the digital random number generator controls the sampling capacitors via the switches to sample the first digital sequence.

Abstract: Examples disclosed herein relate to averaging modules. For example, a method may include obtaining, by an analog-to-digital converter (ADC), a plurality of samples of an input analog signal. The method may also include determining, by an averaging module, a sum value of the plurality of samples, such that a set of most significant bits of the sum value represent an average value of the plurality of samples. The method may further include determining the average value based at least on the set of most significant bits, and outputting the average value to a bus coupled to a memory module.

Abstract: The present disclosure relates to a method of self-calibration of a successive approximation register-analog-to-digital converter. The method includes measuring an error value for each thermometer element of a plurality of thermometer elements and determining a mean value of measured error values. The method also includes generating a thermometer scale where each level of the thermometer scale will be an incremental sum of each value of a first subset, and each further level of the thermometer scale will be a sum of all values of a second subset plus the incremental sum of the elements of the first subset in any order. In addition, the method includes generating the output code according to the thermometer scale.

Abstract: A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.

Abstract: A method for analyzing signals from an angle sensor including at least two sensing elements which span a plane and including a rotatable element for varying the plane, the element being spaced from same. The angle sensor also includes a brushless electromotor which is controlled according to the method. The method for analyzing signals from an angle sensor comprises at least two sensing elements, said method producing high-definition measured results using sensing elements that map a full circle. This is achieved in that the sensing elements capture at least one first and one second vector of the field lying on the plane, the vectors being linearly independent of each other. A further variable, which is dependent on the distance between the plane and the rotatable element, is additionally detected, and the amplitudes of the signals of the first and the second sensing elements are controlled with the value of the further variable.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: An image processor includes a readout arranged to read out an M-bit image data word from an image sensor pixel array and an adder arranged to add a noise contribution to the image data word to obtain a dithered M-bit word. A dither processor is arranged to derive correction data having a word size of M+1 bits from a combination of a plurality of M-bit reference words. The noise contribution are derived from said correction data, wherein different correction data are derived for different groups of pixels, each different group of pixels is associated with a specific pixel value DC shift.

Abstract: A motor control device determines a rotation angle and an angular speed of a motor, and has: a correcting unit including N number (N is an positive integer equal to or more than 2) of bit-shift circuits, which divide the angular speed by powers of 2 by bit shift, and a circuit, which subtracts output values of the second to Nth bit-shift circuits from an output value of the first bit-shift circuit to determine a correction amount for the rotation angle and correct the rotation angle by the correction amount; so as to determine two-phase direct voltages to obtain a target torque from the three-phase alternate currents passing through the motor according to the angular speed, and convert the two-phase direct voltages into the three-phase alternate voltages according to the sine, cosine of the corrected rotation angle.

Abstract: This resolver digital converter 10 includes a band pass processing unit that is disposed between a conversion unit and a multiplication unit and passes only a signal of a predetermined band through processing performed with a period that is shorter than the sampling period of an analog-to-digital converter and corrects the gains of digital signals before being input to the multiplication unit by using gain correction values that are set based on the maximum value and the minimum value of each one of digital signals passing through the band pass processing unit.

Abstract: An automatically calibrating time to digital conversion circuit. The circuit includes a first circuit node for switchably receiving a first calibration signal and a second circuit node coupled with the first circuit node via a first delay path. A third circuit node for switchably receiving a second calibration signal the same as the first calibration signal is coupled with a fourth circuit node via a second delay path. A calibration portion has a third delay path switchably connected with the fourth circuit node and a fourth delay path switchably connected with the second circuit node. The calibration portion generates a delay adjustment signal for adjusting a time delay of the first delay path such that the first time delay combined with the fourth time delay equals the second time delay combined with the third time delay. The calibration portion is disconnected when calibration is not desired for conserving power.

Abstract: First and second A/D converters perform analog/digital conversion of first and second signals of a Hall signal so as to generate third and fourth signals as digital signals. A differential conversion circuit generates a fifth signal as a single-ended signal that corresponds to the difference between the third and fourth signals. An offset correction circuit corrects offset of the fifth signal so as to generate a sixth signal. An amplitude control circuit stabilizes the amplitude of the sixth signal to a predetermined target value, and generates its absolute value, thus generating a seventh signal. A control signal generating unit generates a control signal based upon the seventh signal. A driver circuit drives a motor according to the control signal.

Abstract: A method is presented for converting the sine/cosine signals from an optical encoder into a high-resolution position signal for use by a position control system while eliminating common noise and error sources. The improved noise performance resulting from the alias-free demodulation of encoder signals improves precision and reduces power consumption in precision motion control applications. The adaptive compensation of harmonic distortion eliminates errors related to offset, gain and quadrature of the encoder channels. The interpolator is able to process encoder signals at extremely high resolution without the speed limitation of prior art encoder interpolators.

Abstract: A process inserts a random noise in a Time to Digital Converter (TDC) designed for calculating the phase error between a first high frequency signal FDCO with respect to a second reference signal, switching at a lower frequency.

Abstract: Methods and apparatus are disclosed for applying successive multi-rank beamforming strategies (e.g., successive precoding strategies) for the design of precoders over a set of parallel channels. Successive beamforming is applied to a narrow band channel model and is also applied for finer quantization of a single beamforming vector (e.g., recursive beamforming). A first embodiment provides the optimal approach with high complexity. An alternative embodiment provides successive beamforming for near optimal precoding selection with medium complexity. A low complexity method for precoder selection is also provided wherein a channel representative matrix for the set of parallel channels is determined and successive beamforming on the calculated channel representative is applied.

Abstract: An analog to digital converting device has a first converter nonlinearly converting an analog level into a first digital value every first sampling period, shorter than a second sampling period, with low precision, a second converter linearly converting the analog level into a second digital value every second sampling period with high precision, and a controller determining a correction equation by using the second digital value having a high precision in each second sampling period so as to renew the equation every second sampling period, and correcting the first digital values, obtained in each second sampling period, to corrected digital values according to the corresponding correction equation to output the corrected digital value as a digital value, obtained by substantially linearly converting the analog level, every first sampling period.

Abstract: An RD converter is disclosed that has a first multiplier multiplying a resolver signal S1 by an output of a SIN ROM; a second multiplier multiplying a resolver signal S2 by an output of a COS ROM; a subtractor subtracting an output of the first multiplier from an output of the second multiplier; a synchronous detecting circuit detecting synchronously an output of the subtractor with reference to an excitation signal; a controller controlling an output angle ?? to make an output of the synchronous detecting circuit equal to zero; a correction data part outputting a correction angle ?c for the output angle ??; an adder adding the output angle ?? and the correction angle ?c; the SIN ROM producing a sine value of a result from the adder; and the COS ROM producing a cosine value of the result.

Abstract: A data conversion system acquires samples of low frequency signal components of an applied analog signal at a first data conversion rate and samples of high frequency signal components of the applied analog signal at a second data conversion rate that is higher than the first data conversion rate. The data conversion system applies a first correction filter to the acquired samples of the low frequency signal components to provide a first filtered signal and applies a second correction filter to the acquired samples of the high frequency signal components to provide a second filtered signal. The data conversion system interpolates the first filtered signal to provide an interpolated signal, and sums the interpolated signal with the second filtered signal to provide an output signal.

Abstract: In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as ? ? ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.

Abstract: An aircraft cabin pressure control system and the method implement a technique that oversamples and filters a sensed cabin pressure signal, and then differentiates the oversampled and filtered pressure signal to generate cabin pressure rate-of-change. The oversampling and filtering technique removes circuit and sensor induced noise from the cabin pressure signal, and results in cabin pressure rate-of-change values with less noise than currently known systems and methods.

Abstract: The invention provides an angular position detector that can be configured at low cost and that accurately detects the angular position of a rotor in a rotary electric device and permits reliable control thereof even when the rotary electric device runs at a high speed. The angular position detector includes a resolver that outputs a signal indicating the rotational angle of the rotor and a signal processing circuit that calculates the rotational angle of the rotor based on the signal output from the resolver. The signal processing circuit samples output signals from the resolver at predetermined intervals and converts the signal into a digital signal. By calculating the angular speed according to the digital signal output from the resolver, the computation process is simpler, and can be performed using a microcomputer with less processing power, which reduces the component costs for the angular position detector.

Abstract: Two analog signals are substantially sinusoidal and out-of-phase by about 9020 relative to each other when an element moves in a temporally uniform manner in relation to a stationary element. The two analog signals make it possible to determine the actual position of the moving element relative to the stationary element. The analog signals have a corresponding maximum frequency when the moving element moves at a maximum speed. The signals are detected by sensor units and are fed to AD converters which digitize the signals at a scanning frequency and feed corresponding digital signals to an evaluation block that is configured as a hardware circuit, the scanning frequency of the AD converters being more than twice as large as the maximum frequency. The digital signals are fed to a computing block within the evaluation block, said computing block calculating an arc tangent that corresponds to the digital signals in real time.

Abstract: A position determining system for determining a position of a rotor of a rotating motor has sensors that are coupled to the rotor. The sensors generate, in response to a rotation of the rotor, a quadrature signal that has sine and cosine components. The position determining system calculates a sum (A2) of a squared value of the sine component (A2sin2x) and a squared value of the cosine component (A2cos2x). An amplitude correction factor (A) is calculated as the squared root of the sum (A2). An amplitude corrected sine component (sin(x)) is obtained by dividing the sine component (Asin(x)) by the amplitude correction factor (A). An amplitude corrected cosine component (cos(x)) is obtained by dividing the cosine component (Acos(x)) by the amplitude correction factor (A).

Abstract: To achieve miniaturization of a resolver apparatus as a system, to obtain the resolver apparatus at a low cost, and to improve failsafe by installing an abnormality detection unit and a self-diagnosis circuit within the R/D converter. According to the present invention, an abnormality detecting method for an R/D converter in a resolver apparatus includes detecting abnormalities of at least the resolver itself (1), a cable wiring (2) through which the resolver (1) and the R/D converter (3) are connected to each other, and the R/D converter (3) itself by an abnormality detection unit (4) provided in the R/D converter (3).

Abstract: Since an abnormality is judged by executing a square calculating process with respect to sin ? and cos ? for detecting an abnormality in an angular resolver, a processing time is elongated, and a burden to a CPU is great. Since the invention prepares a map which can judge whether the combination of sin ? and cos ? is normal or abnormal, and judges by mapping the combination of the detected sin ? and cos ?, a process can be easily executed, a processing speed is high, and a burden to the CPU can be reduced. Further, an assist can be maintained by controlling a motor by a rectangular wave current by detecting a rotation angle signal at low resolution level, such as Hall sensors arranged around the motor.

Abstract: An offset error, an amplitude error, a phase error and a third harmonic component contained in two-phase sinusoidal signals are removed using relatively simple digital computations. An offset error contained in two-phase sinusoidal signals with a phase difference output from an encoder is detected and corrected. Then, an amplitude error contained in the offset-corrected two-phase sinusoidal signals is detected and corrected. Subsequently, a phase error contained in the amplitude-corrected two-phase sinusoidal signals is detected and corrected. Further, a third harmonic distortion contained in the phase-corrected two-phase sinusoidal signals is detected and corrected. Each correction step includes detecting an error from an ideal Lissajous waveform contained in the corrected two-phase sinusoidal signals, and adding the detected error to an accumulatively added last value to yield a new correction coefficient, thereby dynamically updating the correction coefficient.

Abstract: A resolver can make accurate angle detection in an entire detection range. The resolver includes a resolver stator having an excitation winding of one phase adapted to be excited by a power supply and a first and a second output winding of two phases for outputting a change in the density of magnetic flux as a voltage, a resolver rotor arranged at a central portion of the resolver stator so as to cooperate with the resolver stator for changing a gap permeance between the resolver rotor and the resolver stator in accordance with the rotation of the resolver rotor, and a detection error correction part that corrects an angle detection error of the resolver by using the value of a Lissajous radius of a circular Lissajous waveform obtained from the amplitudes of an output signal Scos from the first output winding and an output signal Ssin from the second output winding.

Abstract: A third harmonic distortion corrector is equipped for correcting a third harmonic distortion contained in a two-phase sinusoidal signals with different phases output from an encoder. A third harmonic calculator/detector calculates the amplitude a3 and the phase ?3 of the third harmonic using Fourier analysis, based on change in radius r of the Lissajous waveform output from a r-? converter. The third harmonic distortion corrector corrects the third harmonic distortion of the two-phase sinusoidal signal A4, B4 based on the amplitude a3 and the phase ?3 of the third harmonic calculated.

Abstract: The present invention provides a device and a method for enhancing the resolution of the digital signal of a digital encoder. The device comprises a digital encoder which outputs a fundamental position signal. Beside, the device comprises a selected integral circuit which receives the fundamental position signal to produce an integral signal according to a predetermined way, a reset circuit which resets the select integral circuit according to the fundamental position signal, a level shift and gain circuit which transforms and amplifies the level of the integral signal to produce a processing signal, and an analog-digital converter which receives the processing signal to produce an expanding position signal. In the device, the resolution of the expanding position signal is higher than the resolution of the fundamental position signal, so that it enhances the resolution of the digital signal of the digital encoder.

Abstract: A rotary type encoder is provided with a signal generating portion 2 for generating a sine wave signal of N periods for each revolution in accordance with the rotation of the shaft 4 of a motor; a calculation means for obtaining the rotation angle of the shaft 4 based on the sine wave signal; an EEPROM 37 being arranged in a manner that the error value of the rotation angle for one revolution of the shaft 4 thus measured is divided in relation with the N periods to set a plurality of first angle regions i, the angle region almost at the center of the angle region i is divided into plural regions to set second angle regions j, and an error value corresponding to the angle at almost the center of each of the angle regions j is stored therein in correspondence with the rotation angle; and a correction means for reading the error value stored in the EEPROM 37 in correspondence with the rotation angle to correct the rotation angle.

Abstract: In a control apparatus, a “characteristic value calculation” block calculates a characteristic value (such as amplitude value, offset value, or waveform distortion for each phase of two-phase sinusoidal signals optically input from an encoder, or phase difference between the two phase signals) for each of the two-phase sinusoidal signals, and an “alarm detection” block checks the presence or absence of an excursion outside a predetermined allowable range and, if such an excursion is detected, produces an alarm indication or the like. Each time the “present characteristic value” is input, a “characteristic value comparison” block compares it with “previous characteristic values”, and analyzes the result of the comparison. That is, the difference between the present value and each previous data is calculated, and the largest amount of variation (with plus or minus sign) is obtained; if this amount is larger than a predetermined value, a signal indicating an “imminent failure” is output.

Abstract: A conversion device converts linear displacement signals from a displacement detector into non-linearly adjusted displacement signals for supply to a target such as a computer cursor controller. The displacement signals from the displacement detector are incremented, decremented, or left unchanged depending on displacement speeds detected by the conversion circuit.

Abstract: A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

Abstract: Systems and methods are provided for calibrating a sample delay time between a position request time from a host computer and a position encoder sample time. The position encoder includes a readhead with a transducer and transducer electronics, and encoder interface electronics which exchange data and commands with the readhead and with the host computer. The transducer electronics may lack a clock capable providing a sufficiently consistent sample delay time. To provide a consistent sample delay the interface electronics measures an inherent sample delay time based on signals from the readhead during a calibration mode. The difference between the inherent delay time and the desired delay time is saved and inserted by the interface electronics during position measurement such that the calibrated sample delay time is consistently the desired sample delay time.

Abstract: A method for the absolute determination of the position of two objects, which are movable in relation to each other over a defined measuring distance. The method includes scanning a first measuring graduation with a first graduation period so as to generate a first periodic scanning signal and scanning a second measuring graduation with a second graduation period so as to generate a second periodic scanning signal, wherein the second graduation period is finer than the first graduation period. Correcting the first scanning signal with respect to its ideal phase position, in that a phase correction value is applied to the first periodic scanning signal and determining the phase correction value for at least a partial section of the measuring distance, wherein the phase correction value is a mean value from a maximum and a minimum phase position deviation of an actual phase position from a setpoint phase position in the at least one partial section.

Abstract: A system and method are disclosed for improving resolution of an encoder or other position sensing device that provides one or more signals indicative of relative movement between two bodies. The signals are employed to determine an operating mode, which varies as a function of relative speed between the two bodies. In one operating mode, the system determines an indication of position by interpolating between position information of a table. Position also can be predicted in this operating mode, which can be used to update the position information. The table is populated with position information based on a sample of the signals from the position sensing device, such as to provide the position information for the table. In another operating mode, an indication of position is determined as a function of velocity and time.

Abstract: In a circuit arrangement for regenerating the black level of video signals during A/D conversion, in which a deviation of the black level of the digital video signals from a predetermined value influences the black level of the analog video signals, the scanning values obtained during the A/D conversion of the black level of the analog video signals are compared with the predetermined value. A ramp signal for tendency-compensating the deviations is superimposed on the analog video signals.

Abstract: A device for receiving first and second analog signals consisting of two sinusoidal signals shifted in phase from an encoder and outputting digital pulses corresponding to the approximate number of equal steps the system of which the encoder is a part has advanced or retreated comprising flash memory storing a table relating total value counts to the precise value as previously determined by calibration and that adds or subtracts counts to or from a difference register so that the count in the difference register corresponds to the calibrated value moved by the system

Abstract: In one embodiment of the present invention, a compensation driving circuit includes a code generator, an enable circuit, and a driver. The code generator generates a driver code from a compensation code according to a selector signal. The driver code corresponds to a buffer having an impedance. The enable circuit enables the driver code. The driver controls impedance of the buffer according to the driver code.

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: A reference signal generation portion generates a reference signal independently of a repetition cycle of a signal under test. A frequency measuring portion measures a repetition frequency of the signal under test by using a reference signal from the reference signal generation portion. A sampling frequency setting portion computes and sets a value of frequency of a sampling signal which can obtain a desired delay time with respect to a phase of the signal under test based on a value of a repetition frequency measured with the frequency measuring portion. The sampling signal generation portion uses a reference signal from the reference signal generation portion and the value of the frequency set by the sampling frequency setting portion to generate a sampling signal having a cycle corresponding to the frequency.

Abstract: An A/D converter has been described that compares the bounds of a voltage window with an analog input signal Vin. When Vin is not within the boundaries of the voltage window, the position of the voltage window is moved either upwards or downwards depending on the disposition of the analog input signal. The position of the voltage window is sequentially moved until either the analog signal Vin is within the bounds of the window or the absolute upper or lower position limits are reached.

Abstract: The constitution of mixed analog/digital integrated circuits and their testing methods are disclosed. These testing methods are aimed at verification and the linearity of D/A and A/D converters. The mixed analog/digital integrated circuit is given a constitution in which a D/A circuit and an A/D circuit are connected in series to verify the reveribility of the D/A circuit and the A/D circuit, and an attenuator is inserted after D/A conversion and a multiplier with multiplying factor equal to the reciprocal of the attenuation factor of the attenuator is inserted in the post-stge of the A/D converter.

Abstract: Spurious artifacts in intensity emulation caused by measurement non-linearities within a statistically created raster display are reduced or eliminated by first characterizing the non-linearities. Armed with this information the collection of code values in an aperture can be inspected to notice which code values are occurring. M-many out of every n-many instances of a fat code can be replaced by an adjacent code, with a frequency of replacement that is selected to counteract the fatness. In principle, the replacement mechanism could be sensitive to prior events and propagate or distribute corrections across a family of abnormal codes. The idea is to statistically adjust the collection of codes to be closer to what it would be if there were no non-linearities. Different non-linearities may benefit from different strategies for replacement. Certain safeguards may be desirable to prevent making the problem worse rather than better.

Abstract: An analog-to-digital (A/D) converter system converts an analog input signal into a digital output value by combining a plurality of digital sample values. For example, an A/D converter converts an RF analog signal into digital sample values. The A/D system comprises averaging circuitry which takes the average of N digital sample values from the A/D converter. The average is produced as the digital output value for digital processing circuitry. The signal to noise ratio (SNR) of the A/D system is thereby increased because in the averaging process noise components tend to cancel due to their random nature. The increase in the SNR provided by averaging the digital sample values enables the use of higher sampling rates because the processing gain achieved by averaging the digital signal samples counters the degradation caused by clock jitter. As such, a higher speed A/D converter can be used to directly convert an RF analog signal, thereby reducing the need for frequency conversion stages.

Abstract: In a printer, a paper positioning system is used to control feeding a printing medium, such as paper, through the printer. An optical encoder is used to generate analog current waveforms as the paper is fed through the printer. An integrated adjustable current to voltage converter and digital quadrature generator are used to convert waveforms received from the optical encoder into a digital form and then selectively converted to digital form for use by the paper positioning system.

Abstract: An offset correcting circuit for an encoder capable of detecting a correct offset value even when a sampling period is long as in the case of a low-speed A/D converter and restraining the influence of noise. The offset correcting circuit for an encoder adapted to output an angle signal based on digital signals obtained by performing A/D conversions of two signals having phases different by about 90 degrees in accordance with the same timing includes an offset detecting circuit for obtaining an offset value of one of the two signals, using an A/D converted value of that one signal which is obtained when an A/D converted value of the other of the two signals is zero or close to zero, and a compensating circuit for compensating an offset of that one signal using the offset value detected by the offset detecting circuit.

Abstract: A video DAC uses a charge pump to maintain a constant peak to peak amplitude within power supply variations over process and temperature, rather than an external reference signal or a band gap reference. The charge pump performs calibration at full scale output during horizontal sync levels or vertical sync pulses.

Abstract: The phase controlling circuit 1 controls the phase of the input sinusoidal signal S1 to generate first and second sinusoidal signal S1 and S2 which have different phases of 90.degree. shifted from each other. The signal generating circuits 2a and 2b square the first and second sinusoidal signal S1 and S2 to generate first and second squared sinusoidal signals S1.sup.2 and S2.sup.2, respectively. The squared sinusoidal signals S1.sup.2 and S2.sup.2 are added by the signal adding circuit 3, thereby generating the added output S3 which is an amplitude of the input sinusoidal signal S. The phase controlling circuit 1 comprises 90.degree. phase shift circuits 11 and 12 which have a common signal input terminal and the respective signal output terminals. The 90.degree. phase shift circuit is composed of an all-pass filter whose central frequency is set to be f0-.DELTA. f so as to generate the first sinusoidal signal. The second 90.degree.

Abstract: A resolver to digital converter wherein the data from the resolver is processed according to octants which provide the most significant three bits indicating shaft position. The sine and cosine values from the resolver are further processed according to the octant with the smaller value being divided by the larger value to derive a tangent value in the range of zero to one. A look up table can then be used to provide a linear position indication from the tangent values which are then added to the octant value to obtain the shaft position indication.

Abstract: A software-based resolver-to-digital converter (RDC) (80) for computing an angle of rotation &THgr; of gimbal-mounted instrumentation (16) in a gimbal system. The RDC (80) computes the angle of rotation of the instrumentation using parameter signals received from a resolver (32) in the system. The parameter signals, along with a resolver reference signal are input into a multiplexor (60) and are multiplexed. The signals are then fed to an analog to digital converter (38) and converted to digital form. The digital signals are then input into a processor (36) associated with the system. This processor, in addition to performing numerous system computations, is programmed through appropriate software to filter the digital signals received, compute the value for the angle of rotation &THgr; and output the computed value to system circuitry (31) for processing to enhance system operation.