Abstract: Latch systems and methods are configured to temporarily latch trim signals in experimental combinations of set and reset states and, subsequently, to permanently latch the trim signals in a preferred combination (i.e., a combination that optimizes the performance parameters of an electronic circuit). Latch systems of the invention include a latch, a reset driver, a temporary-set driver and a permanent-set driver and are particularly suited for determining a preferred combination of set and reset states prior to permanently latching this preferred combination.

Abstract: N-bit precision digital-to-analog converters are provided that facilitate realization of precision linearities (i.e., linearities that substantially exceed N-bit linearity). They include a binary-weighted current source, current switches and bidirectional-trim digital-to-analog converters. The binary-weighted current source generates binary-weighted currents that are each coupled to the output port by a respective one of the current switches in response to a respective bit of the digital input signal. The bidirectional-trim digital-to-analog converters generate respective bidirectional trim currents with respective amplitudes and directions. Each of the bidirectional-trim digital-to-analog converters is coupled to provide its bidirectional trim current to a respective one of the current switches for a linearizing adjustment of that switch's binary-weighted current. Preferably, the bidirectional-trim currents are slaved to the binary-weighted currents.

Abstract: Integrated-circuit structures and methods are provided for generating an error signal that represents temperature and process-induced signal changes in transistor parameters. In particular, a reference transistor and a sense transistor are biased to each generate a substantially temperature-insensitive minority-carrier current. The reference transistor is provided with a substantially constant voltage across its current terminals to convert its minority-carrier current into a substantially temperature-insensitive reference current IR. In contrast, the sense transistor is provided with a temperature-varying voltage across its current terminals to convert its minority-carrier current into a temperature-varying sense current IS. The reference current and the sense current are then differenced to realize an error signal IE that contains information that describes temperature and process-induced signal errors in integrated-circuit transistor stages.

Abstract: Digital self-calibration of digital-to-digital converters includes an approach to correct for the arbitrary errors in the analog section provided that there are sufficient redundancy in the architecture. The calibration procedure is performed off-line (upon power-up or user request). The digital correction technique avoids the need of a very accurate current mirror or an extra digital-to-analog converter as a standard transfer device.

Abstract: In a subranging ADC, the unary DAC is trimmed by walking through its transfer function while toggling an offset cell at the input to the coarse quantizer and a reference cell in the DAC such that the reference cell is substituted for the cell under test on alternating cycles to provide the last lsb of the reconstructed signal. A test circuit measures the voltage at the output of the summing amplifier for both conditions and generates an error voltage in which the common mode terms have been rejected. The cell under test is then laser trimmed to reduce the error voltage until the cell's DNL error is within an error bound of a tolerance. In one embodiment, the tolerance is dithered to improve spur free dynamic range.

Abstract: In the method for controlling output of a transmission amplifier of a radio, especially of a mobile telephone, by a digital/analog converter, calibration cycles for the digital/analog converter are performed during transmission pauses. Test signals are applied to the digital/analog converter and the signals delivered from the digital/analog converter are compared, after conversion into digital signals, with the test signals. The offset of the D/A converter is determined in a signal evaluation and control unit, and in the following transmission is superimposed on the input signal fed to the digital/analog converter.

Abstract: A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1 . . . 7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells.

Abstract: A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry such as a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. In order to make the measurements of the selected analog inputs more precise, the microcontroller uses a unique calibration procedure whereby selected parameters associated with the analog circuitry that are subject to variation are measured during test and corresponding calibration constants are calculated therefrom and stored in program memory. These stored calibration constants are subsequently used by the microprocessor in conjunction with the digital counts of the analog input signals for calculating a more precise measurement of the analog input signals.

Abstract: An analog-to-digital converter comprises the following elements. A reference voltage generation circuit is provided for dividing a reference voltage into a plurality of divided reference voltages having voltage levels different from each other. A plurality of comparators are provided, each of which has a first input terminal connected to an analog input line for fetching analog signals and a second input terminal connected to the reference voltage generation circuit for fetching a corresponding one of the divided reference voltages so as to compare the analog signals with the divided reference voltage. Each of the comparators has an output terminal through which an output digital signal is outputted.

Abstract: Disclosed is a method and a device for compensating the DC offset (dU) of a D/A converter (2), particularly in the base frequency modulator of a mobile phone. The method and the device use an error correction register (5), whose value is changed on the basis of the DC offset, and which is added to each signal sample to be converted for compensating the DC offset. The value of the error correction register (5) is changed in a testing mode so that a preset control value is fed into the D/A converter (2), corresponding to the zero voltage of the output of an ideal D/A converter; the voltage values of outputs of a differential output pair (2a, 2b) arranged in connection with the D/A converter (2) are compared to verify the polarity of the voltage difference (dU) of the outputs and the polarity, i.e.

Abstract: An analog-to-digital (A/D) converter is provided for converting an analog signal to a digital signal, wherein the digital signal is corrected such that it does not contain DC offset. The A/D converter preferably comprises a delta-sigma modulator and an offset compensation circuit. The offset compensation circuit is coupled to the output of the modulator or, according to another embodiment, to the output of a noise cancellation circuit. The offset compensation circuit can calibrate a single bit output from the modulator or a multi-bit output from the noise cancellation logic. In the former instance, the offset compensation circuit includes an up/down counter and register; in the latter instance, the calibration circuit includes an accumulator. The offset compensation circuit counts or accumulates a digital representation of DC offset.

Abstract: A method of self calibration for a segmented digital-to-analog converter is provided. The segmented digital-to-analog converter converts a digital input code to an analog output consisting of an analog output step and an analog calibration factor. The method comprises the step of determining a trim value for each segment of a segmented DAC. The method continues by storing the trim values in memory. Then, the trim values for a plurality of segments preselected to be enabled by a given digital input signal are summed, thereby producing a digital calibration factor associated with each given digital input signal. Last, storing each digital calibration factor in memory at an address corresponding to the associated digital input signal.

Abstract: A method of self calibration for a segmented digital-to-analog converter is provided. The segmented digital-to-analog converter converts a digital input code to an analog output consisting of an analog output step and an analog calibration factor. The method comprises the step of determining a trim value for each segment of a segmented DAC. The method continues by storing the trim values in memory. Then, the trim values for a plurality of segments preselected to be enabled by a given digital input signal are summed, thereby producing a digital calibration factor associated with each given digital input signal. Last, storing each digital calibration factor in memory at an address corresponding to the associated digital input signal.

Abstract: An electronic probe circuit having ac and dc amplifiers and an input compensation subcircuit is enclosed within a trim housing that replicates the electrical effect of the probe housing. The circuit is laser trimmed through ports in the trim housing. The difference between the voltage at 80 nsec and 1.4 .mu.sec points on a step voltage provides a first calibration factor while the difference between the 3 nsec voltage and the 80 nsec voltage provides a second calibration factor. A resistor in the DC amplifier is trimmed to an absolute voltage with a step scan laser cut. A resistor in the AC amplifier is trimmed with a laser L-cut until the difference between the 80 nsec and 1.4 .mu.sec points of the step voltage equals the first calibration factor. A capacitor in the input compensation subcircuit is trimmed until the voltage difference between the 3 nsec and 80 nsec points equals the second calibration factor.

Abstract: A segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential buffer amplifier. Also described are various alternative DAC embodiments and an operational amplifier input stage in which modulation of the offset voltage of a differential amplifier responsive to a digital signal is accomplished using interpolation techniques for eliminating errors in linearity and monotonicity arising from component inaccuracies.

Abstract: A method and apparatus for calibration of errors in the analog reference voltage input of an analog-to-digital converter. A monolithic reference voltage generator is provided to generate the analog reference which includes a bandgap voltage reference (50) that outputs an untrimmed voltage and a temperature voltage. The untrimmed voltage and temperature voltage are input to a delta-sigma A/D converter (52) which has the output thereof processed through a digital filter (54) to output data on a data bus (58) for storage in an EEPROM (60). The EEPROM (60) is operable in one mode to store temperature history data and, in another mode, to store temperature compensation data. In one mode, temperature compensation parameters are retrieved from the EEPROM (60) and utilized by a multiplier/accumulator circuit (74) to generate compensation factors which are output as a digital word to a DAC (76) for controlling a trim circuit (14).

Abstract: A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.

Abstract: An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. A memory array embedded in the ADC stores a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage. During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages. The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage. In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value.

Abstract: An improved digital-to-analog conversion circuit (10) comprises digital circuitry (12) for receiving digital input signals from a digital input signal source, conversion circuitry (42) receiving the digital input signals and producing analog output signals and analog output circuitry (44) for sending analog output signals to an analog output signal load. The conversion circuit (10) includes calibration circuitry (46) that samples analog output signals from analog output circuitry (44) and includes a reference signal source (52) for producing a plurality of reference signals. A comparator (50) compares a predetermined aspect of the analog output signals to the reference signals to produce therefrom a plurality of difference signals. Correction circuitry includes error detection circuit (95) that includes a successive approximation register (62) and a digital controller (66) for receiving the difference signals and a digital interpolator (26) for generating a plurality of correction signals.

Abstract: In one embodiment, a successive approximation analog-to-digital converter having a main CDAC and a trim CDAC includes resistors in the main CDAC connected in series with various bit switch FETs. The resistors are precisely matched to equivalent resistances of trimmable voltage divider circuits connected in series with various corresponding bit switch FETs in the trim DAC, to prevent non-linear parasitic capactiance and voltage-current properties of first and second clamping FETs from "unbalancing" the voltages on the charge summing conductors of the main DAC and the trim DAC during turn-off of the first and second clamping FETs after they have been turned on to equalize the voltages of the charge summing conductors. In another embodiment, separate trim and dummy DACs are provided to improve the accuracy to which the resistances in the main CDAC and trim CDAC can, as a practical matter, be matched.

Abstract: A voltage reference circuit is described which is capable of providing either an internally generated voltage having a trimming capability, or an externally generated voltage, with the use of only two pins. The internal voltage is connected through an interrupt circuit to an input/output terminal, which can also receive an externally generated voltage. A trimming terminal is used to apply trimming voltage signals to adjust the internally generated voltage. To convert from the internal to the external voltage source, an interrupt voltage is applied to the trimming terminal which is outside of the normal trimming voltage range. This interrupt voltage actuates an interrupt circuit to interrupt the connection between the internal voltage source and input/output terminal, leaving the output terminal available for the external voltage source.

Abstract: An analog to digital converter system is disclosed as comprising a conversion circuit operative for developing a digital output corresponding to the magnitude of an input analog signal, a calibration port arranged for receiving digital calibration data from an external source, adjustable calibration circuitry associated with the conversion circuit, and an adjustment mechanism for adjusting the calibration circuitry in response to data applied to the calibration port.

Abstract: A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.