Abstract: A method for processing continuous sensor signals of a sensor in which a sensor signal is sampled at a sampling frequency and a series of sampled values able to be classified in terms of time is generated in this way, the sampling frequency is dynamically adapted to the spectral signal properties of the sensor signal variable over time and an item of time information is allocated to the thereby generated sampled values, which allows an allocation of the sampled values in terms of time.

Abstract: A method includes obtaining electrical measurements of an input signal of a power system. The electrical measurements are obtained at a sampling frequency and the input signal is indicative of an operating frequency of the power system. The method includes generating an intermediate signal from the input signal. The intermediate signal has a direct current (DC) component indicative of a magnitude and a phase of the input signal. The method includes filtering the intermediate signal using an adjustable length filter to obtain the magnitude and the phase of the input signal. The length of the adjustable length filter varies based at least in part on a period measurement of the power system.

Abstract: Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

Abstract: An analog-digital conversion apparatus includes: an analog-digital converter (ADC) included in an integrated circuit (IC) and configured to operate based on a sampling clock constituting a portion of a plurality of clocks; and a driver included in the IC and configured to operate based on another portion of the plurality of clocks, and produce a driving signal based on a digital value output from the ADC. The ADC and the driver are synchronized with each other based on an interrupt request (Irq) of the IC.

Abstract: The present invention relates to a compressed sensing apparatus for compressed sensing of a set function consisting of a plurality of input sets containing a group of data. The apparatus includes: a plurality of sensing units acquiring a group of sampling data representing a plurality of sampling sets selected out of the plurality of input sets; a compression and computation unit enabling a compression to the group of data based on the group of sampling data in accordance with a Fourier basis set generated on the basis of the plurality of input sets and sampling sets, and a computation to compute a Fourier coefficient set based on a sparse regression technique which is in relation with the Fourier basis set; and a reconstruction unit predicting the group of data based on the Fourier coefficient set.

Abstract: Embodiments of the disclosure are drawn to apparatuses a hybrid switched capacitor array power amplifier (H-SCPA). The H-SCPA may have an array of storage elements divided into sub-arrays. A first sub-array may be configured to receive a delta sigma modulated (DSM) signal. A second sub-array may be configured to receive a Nyquist-rate signal. The H-SCPA may provide an output based on the received DSM and Nyquist-rate signals. The first sub-array and second sub-array may have different architectures. The DSM signal may represent the least significant bits of the signal and the Nyquist-rate signal may represent the most significant bits of the signal.

Abstract: An image sensor may include an analog-to-digital converter. The converter may have a input capacitor, one or more metal-oxide-semiconductor capacitors, a digital-to-analog converter, and a comparator. An input signal may be sampled onto the input capacitor while the metal-oxide-semiconductor capacitors are activated. A few conversion steps may be performed while the metal-oxide-semiconductor capacitors are activated. After the few conversion steps, the metal-oxide-semiconductor capacitors are deactivated to realize a voltage gain, which makes the converter less sensitive to comparator noise.

Abstract: The source light having a range of optical wavelengths is split into sample light and reference light. The sample light is delivered into a sample, such that the sample light is scattered by the sample, resulting in signal light that exits the sample. The signal light and the reference light are combined into an interference light pattern having optical modes having oscillation frequency components respectively corresponding to optical pathlengths extending through the sample. Different sets of the optical modes of the interference light pattern are respectively detected, and high-bandwidth analog signals representative of the optical modes of the interference light pattern are output. The high-bandwidth analog signals are parallel processed, and mid-bandwidth digital signals are output. The mid-bandwidth digital signals are processed over an i number of iterations, and a plurality of low-bandwidth digital signals are output on the ith iteration.

Abstract: An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes an analog-to-digital converter (ADC) to convert an analog input signal to a digital output signal in response to an ADC clock signal. The RF receiver further includes a frequency generator to selectively provide either a clock signal to be provided as the ADC clock signal or a signal to be used for in-phase-quadrature (IQ) calibration of the RF receiver.

Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

Abstract: In an intelligent electronic device, a first receiving circuit receives first time-series data at a first sample rate representing the electrical quantity of an electric power system from a merging unit. An up converter converts the first time-series data into second time-series data having a second sample rate higher than the first sample rate by interpolating the first time-series data. A down converter converts the second time-series data into third time-series data having a third sample rate lower than the first sample rate by periodically extracting a data point at any changeable sample time from the second time-series data. A relay computer performs protective relay computation using third time-series data.

Abstract: Electrochemical sensing of biomolecules eliminates the need for bulky optical instruments required in traditional fluorescence-based sensing assays. Integration of the sensor interface electrodes and active electrochemical detection circuitry on CMOS substrates miniaturizes the sensing platform, enhancing portability for point-of-care applications, while enabling high-throughput, highly-parallel analysis. One embodiment includes a four-by-four active sensor array for multiplexed electrochemical biomolecular detection in a standard 0.25-?m CMOS process. Integrated potentiostats, including control amplifiers and dual-slope ADCs, stimulate the electrochemical cell and detect the current flowing through on-chip gold electrodes at each sensor site resulting from biomolecular reactions occurring on the chip surface. Post-processing techniques for fabricating biologically-compatible surface-electrode arrays in CMOS that can withstand operation in harsh electrochemical environments are described.

Abstract: Provided are a device and a method for transmitting and receiving voice data in a wireless communication system. A method for operating a transmission terminal for transmitting a voice signal comprises the steps of: generating sampling and bitrate request information including sampling information for determining a sampling rate of the voice signal and bitrate information for determining a bitrate of the voice signal, and transmitting the generated sampling and bitrate request information to a reception terminal; receiving, from the reception terminal, combined determination information obtained by at least one combination of the sampling rate determined on the basis of the sampling information and the bitrate determined on the basis of the bitrate information; and compressing the voice signal according to the received combined determination information, and transmitting the compressed voice signal to the reception terminal.

Abstract: An embodiment electronic circuit includes an electronic switch comprising a load path, a first protection circuit configured to generate a first protection signal based on a current-time-characteristic of a load current through the load path of the electronic switch, and a drive circuit configured to drive the electronic switch based on the first protection signal. The first protection circuit includes an analog-to-digital converter (ADC) configured to receive an ADC input signal representing the load current, to sample the ADC input signal once in each of a plurality of successive sampling periods, and to output an ADC output signal that includes a sequence of values such that each of the values represents a respective sample of the ADC input signal. The ADC is configured to pseudo-randomly select a sample time in each sampling period.

Abstract: An electronic device and corresponding method are used for acquiring, storing, and transmitting radio frequency identification (RFID) credential data previously stored in another device. The electronic device includes a mechanical housing, electronic circuitry mounted within the mechanical housing, a power source coupled to the electronic circuitry to provide electrical power to the electronic circuitry, and an interface mechanism coupled to the electronic circuitry in a manner to allow a human user to effect operation of the electronic circuitry. The electronic circuitry is configured to (a) receive an initial response RF signal emitted by the other device in response to an initial interrogation RF signal, where the initial response RF signal carries the RFID credential data, (b) acquire the RFID credential data from the initial response RF signal, (c) store the RFID credential data, and (d) transmit to an interrogator device an outgoing RF signal that carries the RFID credential data.

Abstract: Systems and methods for biosignal acquisition, and in particular, electrocorticography signal acquisition, are disclosed for small area, low noise recording and digitization of brain signals from electrode arrays.

Abstract: Provided is a switching regulator in which a MOS transistor Q1 (first switch) and a MOS transistor Q2 (second switch) are complementarily turned on/off according to an output voltage VOUT, and in which a MOS transistor Q3 (third switch) and a MOS transistor Q4 (fourth switch) are complementarily turned on/off by fixing an on-duty D of the MOS transistor Q3 (third switch) in a step up/down mode. The switching regulator performs current mode control according to information of current flowing in the second switch.

Abstract: An Initial Profile Application Apparatus (IPAA) is operable to apply an initial profile to a modem pair connection system, the modem pair connection system comprising a first modem, a corresponding second modem and a metallic wire connection, wherein the first and second modems are operable to establish a data connection between themselves over the metallic wire connection. The IPAA comprises: a receiver; an evaluator; a line database; a comparator; a determiner; and an applicator.

Abstract: A system and method of locating a key fob with respect to a vehicle includes: detecting short-range wireless signals communicated between the key fob and a plurality of nodes at the vehicle using an IEEE 802.11 protocol; calculating the distance of the key fob relative to each of the nodes attached to the vehicle based on the detected short-range wireless signal; and determining the location of the key fob based on the distance of the key fob relative to each of the nodes.

Abstract: A hearing device comprises a receiver, an input buffer and a sample processor, the receiver being adapted to receive samples of a digital audio signal and feed received samples as a digital input signal to the input buffer, the sample processor being adapted to process the buffered samples to provide samples of a digital output signal such that the digital output signal is a sample-rate converted representation of the digital input signal with a predetermined target sample rate. The hearing device further comprises a latency controller adapted to estimate the quality of reception of the digital audio signal and to control the processing of the buffered samples in dependence on the estimated quality of reception.

Abstract: An electric vehicle charging station with a field upgradeable communications facility is provided. The invention includes a sealable housing including a first compartment and a second compartment, the second compartment including an access to an upgrade port; a partition within the housing that is adapted to insulate the first compartment from the second compartment, the partition including an opening providing access the upgrade port; and an EVSE charging station control circuit configured to recognize a communication module when coupled to the upgrade port and to use the communication module for communications if the communication module is connected. Numerous additional aspects are disclosed.

Abstract: A method of automatically adjusting a determination voltage used in an induction type power supply system includes detecting an output voltage of a signal analysis circuit; adding a first threshold value to the output voltage to generate a first determination voltage and subtracting a second threshold value from the output voltage to generate a second determination voltage; outputting the first determination voltage as a reference voltage; and comparing a trigger signal of the signal analysis circuit and the reference voltage, in order to generate a first data code; wherein when the step of comparing the trigger signal of the signal analysis circuit and the reference voltage in order to generate the first data code fails, the method further includes outputting the second determination voltage as the reference voltage and comparing the trigger signal of the signal analysis circuit and the reference voltage, in order to generate a second data code.

Abstract: A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC) using the sampling signal. The method also includes mapping the sampled received signal onto a frequency grid of sinusoids, where each sinusoid has a signal amplitude and a signal phase. The method further includes estimating the signal amplitude and the signal phase for each sinusoid in the frequency grid. In addition, the method includes computing an average background power level and detecting signals with power higher than the average background power level. The non-uniform sampling interval varies predictably.

Abstract: Methods, computer program products, and computer systems for recovering data of scene are provided. The techniques include: obtaining, by at least one processor, data of a scene; re-sampling, by the at least one processor, the data of the scene to obtain re-sampled sensing data of the scene and a corresponding sensing matrix; and constructing, by the at least one processor, recovered data of the scene using the re-sampled sensing data of the scene and the corresponding sensing matrix. In one embodiment, the method includes enhancing occluded data of the scene to construct the recovered data of the scene, where the recovered data of the scene facilitates identification of the scene. In another embodiment, the method includes compressing original data of a scene, the compressing including sampling the original data of the scene to select the data of the scene.

Abstract: There is provided herein a method of passive seismic acquisition that utilizes real time or near real time computation to reduce the volume of data that must be moved from the field to the processing center. Much of the computation that is traditionally applied to passive source data can be done in a streaming fashion. The raw data that passes through a field system can be processed in manageable pieces, after which the original data can be discarded and the intermediate results accumulated and periodically saved. These saved intermediate results are at least two, more likely three, orders of magnitude smaller than the raw data they are derived from. Such a volume of data is trivial to store, transport or transmit, allowing passive seismic acquisition to be practically used for continuous near-real-time seismic surveillance.

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract: A delta-sigma modulator capable of outputting an output signal including a plurality of signals having different frequencies. The delta-sigma modulator includes: a plurality of input ports to which a plurality of input signals having different frequencies are inputted, respectively; a plurality of loop filters provided corresponding to the plurality of input ports, respectively; an adder configured to add outputs of the plurality of loop filters; and a quantizer configured to quantize an output of the adder. The plurality of loop filters each receive the input signal inputted to the corresponding input port and a feedback signal of an output of the quantizer. The plurality of loop filters each have a characteristic of stopping noise in the vicinity of a frequency of the input signal inputted to the corresponding input port.

Abstract: A feedforward control method, which includes: determining, whether the input voltage rapidly changes or slowly changes; when the input voltage rapidly changes, determining, a first feedforward gain coefficient corresponding to the difference between a input voltage reference value and a first input voltage measurement value acquired by a high-speed low-precision analog-to-digital converter in a current sampling period; when the input voltage slowly changes, determining a second feedforward gain coefficient which is a ratio of the input voltage reference value to a second input voltage measurement value acquired by a low-speed high-precision analog-to-digital converter in the current sampling period; and using the first or the second feedforward gain coefficient as a feedforward gain coefficient of a current input voltage, multiplying the feedforward gain coefficient by an output value of a feedback loop of an output voltage, so as to control stable output of the output voltage.

Abstract: A device is configured to receive optimization information associated with a model, determine an amount of delay to be inserted into the model, and determine a sampling factor by which a first data rate associated with a signal is to be modified into a second data rate. The device is configured to determine a region of interest, insert an upsampling block that upsamples the signal entering the region of interest based on the sampling factor, and insert a downsampling block, associated with a unit of delay, which downsamples the signal exiting the region of interest based on the sampling factor. The device is configured to convert the unit of delay into a fast delay block, corresponding to the amount of delay, and insert the fast delay block in the region of interest. The device is configured to generate code associated with the model, and provide the code.

Abstract: Described is a system for foveated compressive sensing. The system is configured to receive an input image f of a scene and initialize a measurement matrix. Global measurements are then performed, with a lower resolution image of the scene thereafter reconstructed. Task salient regions are extracted from the low resolution image. Thereafter, the system estimates a task-specific operator and detects regions-of-interest (ROI) based on the task salient regions. An ROI-adapted and foveated measurement matrix is then generated. Local measurements are then performed on task-relevant ROIs. A higher resolution image can then be reconstructed of the scene to allow for identification of objects in the ROI.

Abstract: A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

Abstract: To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

Abstract: In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

Abstract: A sampling device for sampling an incoming signal in order to generate an output signal having a different frequency spectrum from the incoming signal. The device comprises a sampler configured to sample the incoming signal at a series of intervals in time, wherein the series of intervals includes a temporally repeating sequence of intervals, and wherein the duration of successive intervals varies throughout the series.

Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.

Abstract: A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.

Abstract: An asynchronous sampling frequency conversion device includes: a storage unit configured to store input digital signals; a data specifying unit configured to specify first data and second data based on a ratio of a sampling frequency of the input digital signal to a sampling frequency of an output digital signal, the first data being sampled at a sampling timing immediately before an ith (where i is a natural number) sampling timing of the output digital signal among the input digital signals stored in the storage unit, the second data being sampled at the sampling timing immediately after the ith sampling timing of the output digital signal; and an output data value calculator configured to calculate a value of ith data of the output digital signal based on the first data and the second data specified by the data specifying unit and the ratio.

Abstract: In one embodiment, a method comprising sampling by a first sampling unit a first signal received via a first antenna; and sampling by a second sampling unit a second signal received via a second antenna, the sampling of the second signal commencing in synchronization with the sampling of the first signal by the first sampling unit based on an accumulated value, the first and second signal sharing common information.

Abstract: A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise.

Abstract: Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency.

Abstract: A method and system for using Equivalent Time Sampling to improve the effective sampling rate of sensor data, and using the improved-resolution data for diagnosis and control. Data samples from existing sensors are provided, where the sampling rate of the existing sensors is not sufficient to accurately characterize the parameters being measured. High-resolution data sets are reconstructed using Equivalent Time Sampling. High-resolution input data sets are used in a system model to simulate the performance of the system being measured. Results from the system model, and high-resolution output data sets from Equivalent Time Sampling, are provided to an estimator, which provides accurate estimation of measured quantities and estimation of quantities not measured. Output from the estimator is used for fault diagnosis and control of the system being measured.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation.

Abstract: An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation.

Abstract: A sensing and recovery system includes a sensing unit and a recovery unit coupled together. The sensing unit includes a sensor to generate a bandlimited continuous time analog signal, and a modulator coupled to the sensor to generate a modulated analog signal based upon modulation of the bandlimited continuous time analog signal at a modulating rate at least equal to a Nyquist rate for the bandlimited continuous time analog signal. A compressive sensing circuit is coupled to the modulator to generate a compressed sensed signal based upon conversion of the modulated analog signal at a sampling rate less than the Nyquist rate. The recovery unit recovers the bandlimited continuous time analog signal from the compressed sensed signal.

Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.

Abstract: A particular method includes calibrating data capture by a data register, where the data register receives a data signal from an analog-to-digital converter (ADC). The data capture may be calibrated by determining a peak value of a set of output values of the data register, where the peak value is determined in response to the ADC receiving a known input signal, and increasing a delay interval applied to registering of a value by the data register when the peak value satisfies a threshold.

Abstract: Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.

Abstract: A data transfer system which can surely transfer data between two function circuits which operate synchronously with different clock frequencies. A data loading signal is generated just before timing when edges of two clocks of different frequencies coincide. Only information data received by the function circuit on a transfer data reception side within an existence period of the data loading signal is determined to be valid.

Abstract: A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data.