Abstract: A quantization apparatus comprises: a first quantization module for performing quantization without an inter-frame prediction; and a second quantization module for performing quantization with an inter-frame prediction, and the first quantization module comprises: a first quantization part for quantizing an input signal; and a third quantization part for quantizing a first quantization error signal, and the second quantization module comprises: a second quantization part for quantizing a prediction error; and a fourth quantization part for quantizing a second quantization error signal, and the first quantization part and the second quantization part comprise a trellis structured vector quantizer.

Abstract: A method of disarming and reconstructing an encoded video stream to nullify malicious agents potentially embedded in the encoded video stream comprising decoding a received encoded video stream to obtain a decoded video stream, extracting, from the encoded video stream, encoding information calculated by an originating encoder to create the encoded video stream, adjusting the encoding information by replacing one or more quantization parameters defined in the encoding information with respective adjusted quantization parameter(s) calculated based on a random selection of a value from a range of quantization parameter values, encoding the decoded video stream using the adjusted encoding information to produce a modified encoded video stream and transmitting the modified encoded video stream.

Abstract: Techniques for limiting the growth of errors in decoded data words that arise from bit errors incurred during transmission. The growth of 3+ bit errors in the decoded data word is limited at the expense of a higher number of two bit errors, which are correctable using practical error correcting codes.

Abstract: The present disclosure provides a data transmission method, includes: multiplying a frequency of a basic clock, so as to obtain a frequency-multiplied clock, in which a maximum number of high levels in the frequency-multiplied clock is greater than a maximum numerical value that the bit number can represent; removing an invalid bit width from the data to be transmitted, and determining a bit number of an effective bit width thereof and a numerical value represented by the effective bit width; determining a data period, according to the bit number of the effective bit width in the data to be transmitted; determining an actual number of high levels, according to a numerical value represented by the effective bit width in the data to be transmitted; and transmitting the data to be transmitted based on the frequency-multiplied clock, according to the data period and the actual number of the high levels.

Abstract: Methods for encoding data in synthetic DNA include, for an input data sequence, constructing a codebook of a number of unique codewords, of a nucleotide length, which are constructed such that, for each codeword, the codeword is formed from a selection of nucleotide pairs from a first predefined dictionary of nucleotide pairs, and, if the nucleotide length of the codeword is odd, an additional selection of a nucleotide from a second predefined dictionary of individual nucleotides. For each symbol from the input data sequence, at least one codeword is designated as associable therewith, and each symbol is coded as one codeword selected from the designated at least one codeword associable with that symbol. A code is formed from the codewords, arranged in corresponding order to that of their respective symbols in the input data sequence. A DNA sequence is synthetized with nucleotides ordered to match the code.

Abstract: A method for increasing the effective resolution of digital-to-analog conversion for the purpose of digital pre-distortion to compensate distortions of a communication channel, according to which a digital sequence of N samples x(n) to be transmitted over the communication channel are received and several quantization possibilities are generated by performing Soft Quantization (SQ) on each sample, using a soft quantizer, where low computational complexity is maintained by limiting the number of SQ possibilities. The Instantaneous costs for each possible SQ error is computed and converging paths in the Trellis diagram, which represents possible states and transitions between them, for each sample is eliminated. Then the averaged errors for each remaining path are computed and Hard-Quantization is performed to eliminate converging paths and to keep a constant number of states. These steps are repeated N times, one time for each sample and the optimal path with the lowest averaged error selecting.

Abstract: A tensor decomposition method, system, and computer program product include compressing multi-dimensional data by truncated tensor-tensor decompositions.

Abstract: A data compression method and a data decompression method are provided. The method includes pruning an original data including a plurality of weight parameters, identifying at least one first weight parameter of which at least one first value is not changed by the pruning, among multiple weight parameters included in the pruned original data, and obtaining a first index data including location information of the at least one first weight parameter of which the at least one first value is not changed, identifying at least one second weight parameter of which at least one second value is changed by the pruning, among the multiple weight parameters included in the pruned original data, and substituting the at least one second weight parameter of which the at least one second value is changed with a don't care parameter.

Abstract: An encoding for data in an audio data stream may be indicated in the data stream using a footer stored in low-order bits of data frames in the audio data stream. When the audio data stream may include either Pulse Code Modulation (PCM) or Direct Stream Digital (DSD) data, PCM data may be marked with a footer to indicate the encoding as PCM. The footer may be a fixed value, an alternating fixed value, a predetermined sequence of values, or a value computed based on the PCM data. Examples of computed values for the footer marker may include an error code, an error correction code (ECC), and a scrambled code.

Abstract: A mobile computing device is disclosed. In some aspects, the mobile computing device may execute a first application using one or more processors, and may receive, during execution of the first application, a user selection of a shift key. The mobile computing device may transition a state of the shift key from an unlocked non-shift state to a shift state based on the user selection. The mobile computing device may change the execution of the first application to an execution of a second application, and clear the state of the shift key in response to changing the execution from the first application to the second application.

Abstract: An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.

Abstract: Methods which uses interpolated primitive matrices to decode encoded audio to recover (losslessly) content of a multichannel audio program and/or to recover at least one downmix of such content, and encoding methods for generating such encoded audio. In some embodiments, a decoder performs interpolation on a set of seed primitive matrices to determine interpolated matrices for use in rendering channels of the program. Other aspects are a system or device configured to implement any embodiment of the method.

Abstract: The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.

Abstract: A solid state drive (SSD) apparatus including a plurality of solid state drives, a channel-interleaved interface operably coupled to the solid state drives, and a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface.

Abstract: A transceiver architecture can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data based on a product code of an E8 lattice based on binary and non binary codes that creates an extended Hamming code of a multi-level structure of E8 with four bit estimates. During decoding the multi-level E8 decoding is performed on the Hamming code and then row decoding and column decoding are performed. Then lattice decoding is performed on the output of the row and column decoding. This decoding process can be iteratively performed a predetermined number of times until the encoded bits are decoded.

Abstract: A method is provided for processing pre-echo attenuation in a digital audio signal generated from a transform coding, wherein, at the decoding point, the method includes: detection of a position of attack in the decoded signal; determination of a pre-echo region preceding the position of attack detected in the decoded signal; calculation of attenuation factors per sub-block of the pre-echo region, according to at least the frame wherein the attack has been detected and the preceding frame; and pre-echo attenuation in the sub-blocks of the pre-echo region by the corresponding damping factors. The method also includes application of a filter for the spectral shaping of the pre-echo region on the current frame up to the detected position of the attack. A device and a decoder including the device are also proved for implementing the method.

Abstract: In one embodiment, real-time adaptive binning may be performed through the modification of a set of partitions. More particularly, a set of partitions separating one or more bins from one another may be identified, each of the one or more bins having boundaries including a lower boundary and an upper boundary, wherein the boundaries of the one or more bins together define a contiguous range of data values capable of being stored in the one or more bins. A data value may be obtained and added to one of the one or more bins according to the boundaries of the one or more bins. It may be determined whether to modify the set of partitions. The set of partitions may be modified according to a result of the determining step.

Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

Abstract: Systems and methods for level-crossing sampling and reconstruction technique are disclosed. The derivative of the input signal is level-crossing-sampled, and the resulting samples are transmitted. At the receiver, these samples are fed to a zero-order hold followed by an integrator, which results in piecewise-linear reconstruction. The disclosed systems and methods are further refined to reduce the number of samples generated per unit of time, compared to methods based on zero-order-hold reconstruction, for a given signal-to-error ratio, without significant hardware overhead.

Abstract: One embodiment includes an adaptive sample quantization system. The adaptive sample quantization system includes an antenna to receive a radio frequency (RF) signal having data encoded therein, and analog antenna electronics configured to convert the RF signal to an analog electrical signal. The system also includes an analog-to-digital converter (ADC) directly coupled to the antenna and configured to generate a plurality of consecutive digital samples of the RF signal. The system further includes a quantizer to determine a mode based on the plurality of consecutive digital samples and to select at least one threshold based on the determined mode. The quantizer can further compare each digital sample with the at least one threshold to generate a corresponding one of a plurality of output samples having a reduced number of bits relative to the respective digital sample to substantially mitigate potential interference and facilitate extraction of the data.

Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.

Abstract: Representative implementations of devices and techniques provide a variable quantizer for a modulator. A compare value of the quantizer changes with each clock cycle of the modulator. The variable compare value results in a spread spectrum output of the modulator.

Abstract: A quantizer includes a voltage reference network and a set of comparators coupled with the voltage reference network. The voltage reference network generates a plurality of reference voltages. Each of the comparators receives an input signal and produces a sequence of digital samples. The set of comparators includes first, second, and third subsets of comparators. Each comparator of the first subset includes a switched capacitor stage, each comparator of the second subset includes a preamplifier stage, and each comparator of the third subset includes a switched capacitor stage. The first and third subsets of comparators compares the input signal with reference voltages corresponding to the upper and lower voltage ranges of the input signal, and the second subset of comparators compares the input signal with reference voltages corresponding to the middle voltage range of the input signal.

Abstract: An absolute rotary encoder comprises a scale having marks arranged at a first pitch; a first detector and a second detector including plural photoelectric conversion elements arranged at a second pitch smaller than the first pitch, and configured to detect a predetermined number of marks, the second detector disposed opposite to the first detector; and a computing device. The computing device is configured to generate a data string by quantizing a periodic signal output from the first detector, and obtains first angle data from the data string, to normalize amplitudes of the periodic signals output from the first and second detectors, to average the normalized periodic signal to obtain second angle data from a phase of the averaged periodic signal, and to combine the first and second angle data to generate data representing an absolute rotation angle.

Abstract: A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal.

Abstract: An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

Abstract: Provided is a wireless communication device which can improve the notification accuracy of the channel state information (CSI) without straining the feedback circuit. In this device, a channel estimator (105) uses a pilot signal input from a wireless receiver (102) to estimate the channel and obtain a plurality of path gains in each of a plurality of delay periods. Then, the channel estimator (105) outputs the plurality of path gains to a quantizer (107). The quantizer (107) quantizes the plurality of path gains in the number of notification bits corresponding to each of the plurality of delay periods based on the correspondence of the delay period and the number of notification bits input from a setting unit (106).

Abstract: Representative implementations of devices and techniques provide a variable quantizer for a modulator. A compare value of the quantizer changes with each clock cycle of the modulator. The variable compare value results in a spread spectrum output of the modulator.

Abstract: An embodiment is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. Another embodiment is a method and apparatus to decode a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.

Abstract: The present disclosure shows new mechanisms fir sampling an input signal. In particular, some embodiments of the present disclosure include a new type of a level-crossing sampling mechanism called a derivative level-crossing sampling (D-LCS). At a high level, D-LCS involves quantizing the derivative of an input signal when the derivative of the input signal crosses one of the quantization thresholds. For certain class of signals, the derivative of the input signal can vary at a slower speed compared to the amplitude of the input signal. Therefore, by sampling the derivative of the input signal, instead of the input signal itself, the number of samples per unit time can be reduced.

Abstract: The invention relates to the digital signal requantization, at a given quantization step size, of a first word received in a first period of time and encoded in a first number of bits, into a second word, with a quantization error equal to a third number. A sequence of third words is outputted, equal to the second word, with the sequence subdivided into a first group comprising a number of third words that is equal to the third number and a second group of third words. Before outputting them, the correction means adds a least significant bit to the third words of the first group and adds or subtracts least significant bits to or from the third words of the second group, such that the sum of the least significant bits added to and subtracted from the second group is zero.

Abstract: There is provided an audio coding device which appropriately sets the quantization bit number by a small calculation amount in each stage when coding an input audio signal by performing multi-stage normalization/quantization. A quantization information calculation section determines total quantization information idwl0, based on normalization information idsf, and allocates the total quantization information idwl0 for quantization information idwl1 and quantization information idwl2. At this time, the quantization information calculation section limits the quantization information idwl1 by a limiter lim1, and allocates the total quantization information idwl0 for quantization information idwl1. If the quantization information idwl1 exceeds the limiter lim1, the excess is allocated for the quantization information idwl2. A first normalization section and a first quantization section normalizes and quantizes a frequency spectrum mdspec1 in the first stage.

Abstract: A modulator that quantizes a first signal into a quantized signal having a plurality of bits includes an integrator performing sampling on the first signal in a first period, and to integrate a difference between the first signal and a reference signal in a second period; and a quantizer receiving a second signal which is an output of the integrator and operating in synchronization with a first clock having a cycle shorter than the first period, the quantizer generating the quantized signal on the basis of the second signal in the first period and outputting the reference signal on the basis of the quantized signal to the integrator.

Abstract: An LSP vector quantization device able to improve the precision of quantization in vector quantization where a codebook for first stage vector quantization is switched according to the type of a feature that has a correlation with the quantization target vector.

Abstract: Provided are a method and apparatus of a lossless encoding and decoding based on a context. According to an embodiment, by aligning and coding symbols of a MSB, a coding efficiency may be enhanced. According to an embodiment, by estimating initial scaling information using a symbol located proximate to a symbol of the MSB, the coding efficiency may be enhanced.

Abstract: An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (??) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ?? DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.

Abstract: A method for converting an analog signal to a digital signal is provided. Initially, a digital representation of a portion of an analog signal is generated. Residue of the analog signal is then sampled at a sampling instant so as to generate a residue sample. A signal having a frequency that is proportional to the voltage of the residue sample is generated, and the signal is measured to generate coarse and fine measurements of the frequency. A digital representation of the residue sample from the coarse and fine measurements is then generated.

Abstract: A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.

Abstract: A method and apparatus for an adder-embedded dynamic preamplifier system with dynamic comparator and current mode adder including differential switches for precharging, a switch for evaluation; and reference, feedfoward input sections. When differential switches are closed, OUTN and OUTP are precharged. During the evaluation, discharging currents are proportionately determined by input and reference values. A following latch amplifies the discharging differences of OUTN and OUTP.

Abstract: Disclosed are a context-based arithmetic encoding apparatus and method and a context-based arithmetic decoding apparatus and method. The context-based arithmetic decoding apparatus may determine a context of a current N-tuple to be decoded, determine a Most Significant Bit (MSB) context corresponding to an MSB symbol of the current N-tuple, and determine a probability model using the context of the N-tuple and the MSB context. Subsequently, the context-based arithmetic decoding apparatus may perform a decoding on an MSB based on the determined probability model, and perform a decoding on a Least Significant Bit (LSB) based on a bit depth of the LSB derived from a process of decoding on an escape code.

Abstract: An adaptive differential pulse-code modulation-demodulation system and method thereof is provided. The method includes steps of modulating an analog audio input signal into a data packet, including a plurality of digital data through adaptive differential pulse-code modulation, an initial value and a scale factor associated with the digital data, to be sent to the communication network, and demodulating the data packet according to the digital data, the initial value and the scale factor, thereby reconstructing the data packet to an analog audio output signal.

Abstract: A modulator is provided in operative engagement with a sensor element having a plurality of electrodes. The modulator has a single-bit quantizer electrically connected to a digital accumulator. The accumulator accumulates output information received from the single-bit quantizer. The accumulator converts the accumulated output information received from the single-bit quantizer to a multi-bit feedback signal and sends the multi-bit feedback signal in a primary feedback loop back to the sensor element. The quantizer sends a single-bit feedback signal in a secondary feedback loop back to a point before the quantizer.

Abstract: A method of collecting data from an optical channel monitor for monitoring the power of a wavelength-division multiplexed light signal at each wavelength is disclosed. The total light power is analog-to-digital converted by an A/D converter. The data of the total light power which has been analog-to-digital converted is compared with a reference light power by a comparator for each conversion, and when the difference between the total light power and the reference light power exceeds a predetermined threshold, a power fluctuation flag is turned ON. After the comparison, the above process of the analog-to-digital conversion and the comparison is iterated until the optical channel monitor completes the data collection for each wavelength. Thereafter, the processor determines whether the power fluctuation flag is ON or not. When the power fluctuation flag is ON, the processor discards the currently collected data and maintains the data which were collected immediately before.

Abstract: In a multi-rate algebraic vector quantizer and quantizing method for coding spectral coefficients of a plurality of frequency sub-bands, a quantizer portion is supplied with the spectral coefficients of the sub-bands. The quantizer portion has a plurality of codebooks each including a plurality of vectors, and first coders of quantizer parameters identifying the codebooks and vectors used for coding the spectral coefficients of the sub-bands. A second coder processes supplemental information usable to improve, at a dequantizer, decoded spectral coefficients of the sub-bands. Corresponding multi-rate algebraic vector dequantizer and dequantizing method are also provided.

Abstract: An apparatus and method for a fast quantizer comparator comprising three stages: a preamplifier stage, a regeneration latch stage, and a data latch stage. Time delay is reduced by changing the initial voltages of the regeneration latch outputs. The current source is provided at the tail of the comparator, enabling time delay optimization. When the PMOS equalization switch turns off, it makes the clock signal feedthrough and provides charge injection into the outputs. Because of these charges, the time delay of the comparator is variable. Only a very low current sets the output voltages because the resetting time is longer than the comparison time.

Abstract: A quantization circuit includes a quantizer and a compensation circuit. The quantizer includes a voltage-to-phase converter and a phase difference digitization block. The voltage-to-phase converter is arranged for generating a phase signal according to an input voltage. The phase difference digitization block is arranged for generating a quantization output according to a phase difference between a phase of the phase signal and a reference phase input. The compensation circuit is arranged for applying compensation to the phase difference digitization block according to the quantization output.

Abstract: A summing-tracking quantizer additively combines multiple feed-forward outputs of cascaded integrator stages of a sigma-delta analog-to-digital converter with a scaled sampled analog signal, and a delayed scaled analog input signal. The summing tracking quantizer compensates for loop delay within a sigma-delta analog-to-digital converter. A loop delay compensation digital-to-analog converter for a sigma-delta analog-to-digital converter is merged with the voltage reference generator within the summing-tracking quantizer. The summing tracking quantizer selects reference voltages from the voltage reference generator based on a previous digital output code. The summing-tracking quantizer has a matrix switch that receives the previous digital output code and selects the reference voltage for applying to comparators for determining a differential quantization code that is additively combined to the previous digital output code to determine the present digital output code.

Abstract: Provided are, among other things, systems, apparatuses methods and techniques for performing multi-bit quantization. One such apparatus includes an input signal line; a first comparator having a first input coupled to the input signal line, a second input coupled to a first reference signal, and an output; a rectifier having an input coupled to the input signal line and also having an output; and a second comparator having a first input coupled to the output of the rectifier, a second input coupled to a second reference signal, and an output, with the first comparator and the second comparator being clocked so as to produce sequences of quantized samples at substantially the same times.

Abstract: A method and apparatus for an adder-embedded dynamic preamplifier system with dynamic comparator and current mode adder including differential switches for precharging, a switch for evaluation; and reference, feedfoward input sections. When differential switches are closed, OUTN and OUTP are precharged. During the evaluation, discharging currents are proportionately determined by input and reference values. A following latch amplifies the discharging differences of OUTN and OUTP.