Abstract: A gate of the first p-type MOS transistor and the first and second control circuits are electrically coupled to a first node. The first control circuit lowers a voltage or the first node between a first time and a second time at which the first p-type MOS transistor is off. The second control circuit lowers the voltage of the first node between a third time and a fourth time at which the first p-type MOS transistor is on. The second time is later than the first time. The fourth time is later than the second and third times. The first p-type MOS transistor is turned on during a first period. A voltage decrease amount of the first node per unit time in the first control circuit is greater than that in the second control circuit.

Abstract: A method for executing a binary code including the execution of an indirect load instruction which provokes the reading of a data line associated with an address obtained from the content of a destination register, then the construction of an initialization vector from the content of this data line, then the loading of this constructed initialization vector in a microprocessor, then the execution of an indirect branch instruction which provokes a branch directly to a first encrypted instruction line of a following basic block whose address is obtained from the content of the same destination register, then the decryption of the cryptogram of each encrypted instruction line of the following basic block using the initialization vector loaded in the microprocessor.

Abstract: A method for executing a binary code includes for each item of data to be recorded: executing an algorithm for constructing a data line containing a cryptogram of this item of data constructed using an initialization vector ivj associated with an address @j of the main memory using a relationship ivj=Fiv(@j), where the function Fiv, is a pre-programmed function that associates a different initialization vector ivj with each different address @j of a main memory, and then recording this constructed data line in the main memory at the address @j, where each instruction line of a basic block is constructed by executing the same construction algorithm as the one executed to construct the data line and using the same function Fiv, the item of data for this purpose being taken to be equal to the instruction masked using a mask associated with this basic block.

Abstract: Embodiments of this disclosure provide an image coding method and apparatus and an image decoding method and apparatus. The image coding method includes: performing feature extraction on to-be-processed image data by using a convolutional neural network, to generate feature maps of the image data; quantizing the feature maps to generate discrete feature maps; preprocessing the discrete feature maps to generate preprocessed data, an amount of data of the preprocessed data being less than an amount of data of the discrete feature maps; calculating probabilities of to-be-coded data in the discrete feature maps according to the preprocessed data; and performing entropy coding on the to-be-coded data according to the probabilities of the to-be-coded data.

Abstract: Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

Abstract: An isolator includes a transmitter, a coupling module and a receiver. The transmitter drives an input of the coupling module in response to a digital signal, such that in response to a first type of digital data value in the digital signal, a signal of a first predetermined type is supplied to the input and in response to a second type of digital data value in the digital signal, a signal of a second predetermined type is supplied to the input, the signals of the first type and the second type each including an initiation signal that announces a time window during which another portion of the signals representing a digital data value of the first type or the second type will be valid. The receiver is coupled to an output of the coupling module to receive and to decode signals in correspondence to the signals provided to the input.

Abstract: A method for extracting scintillation pulse information includes followed steps: 1. obtaining a peak value of the scintillation pulse in a certain energy spectrum, and setting at least three threshold voltages according to the peak value; 2. determining the time when the scintillation pulse passes through the each threshold voltage, wherein each time value and its corresponding threshold voltage form a sampling point; 3. selecting multiple sampling points as sampling points for reconstructing and reconstructing pulse waveform; 4. obtaining the data of original scintillation pulse by using reconstructed pulse waveform. A device for extracting scintillation pulse information includes a threshold voltage setting module (100), a time sampling module (200), a pulse reconstruction module (300) and an information acquiring module (400).

Abstract: A data processing method and apparatus are provided. The data processing apparatus includes a converter module and a control module. The converter module receives a clock signal through a pin, and decides a bit value of the first data according to a length of a corresponding period of the clock signal. The control module determines whether to perform a bit writing operation for writing the bit value into a memory according to the clock signal and the first data.

Abstract: A video encoding method using inter-prediction, includes: encoding a first picture, wherein the first picture serves as a random access picture and is encoded without referring to a reference picture which has already encoded and then decoded; inter-prediction encoding a block included in a second picture, which is encoded after the first picture and displayed before the first picture, by using a plurality of reference pictures; generating reference picture information representing one or more past pictures which are encoded before the first picture and are used as reference pictures for encoding the second picture; and transmitting the encoded first picture and the encoded second pictures and the reference picture information, wherein, when the one or more past pictures are used as the reference pictures for encoding the second picture, the one or more past pictures are deleted from a memory after encoding at least the second picture.

Abstract: A compression device includes a processor configured to execute a process. The process includes: storing, in a storage, a first compressed code in association with a first element, the first compressed code corresponding to a combination of a first element and a first delimiter, the first element being one of a plurality of elements constituting input data, the first delimiter being one of delimiters delimiting the plurality of elements and succeeding the first element in the input data; acquiring, from the storage, the first compressed code in response to reading a sequence of the first element and the first delimiter from the input data; and writing the first compressed code into a storage area that stores therein compressed data of the input data.

Abstract: A video decoding method using inter-prediction, includes: identifying, based on information included in a bitstream, whether a first picture is a picture which allows a second picture preceding the first picture in a display order to refer to at least one picture decoded before the first picture, the first picture serving as a random access picture; decoding the first picture without referring to a reference picture which has already decoded; and when the first picture is a picture which allows the second picture to refer to the at least one picture decoded before the first picture, inter-prediction decoding, after decoding the first picture, the second picture by using at least one reference picture which is decoded before the first picture depending on reference picture information of the second picture.

Abstract: A video decoding method using inter-prediction, includes: decoding a first picture, wherein the first picture serves as a random access picture and is decoded without referring to a reference picture which has already decoded; and decoding a block, by using an inter-prediction, included in a second picture, which is decoded after the first picture and displayed before the first picture, by using a plurality of reference pictures, wherein the decoding of the block included in the second picture is performed based on reference picture information representing one or more past pictures which are decoded before the first picture and are used as reference pictures for decoding the second picture, and wherein when the one or more past pictures are used for decoding the second picture, the one or more past pictures are deleted from a memory after decoding at least the second picture.

Abstract: Methods for writing multiple codewords having multiple sizes to a solid-state device are provided. In one aspect, a method includes receiving a plurality of host data units for storage in a solid-state non-volatile memory. The method includes dividing the plurality of host data units among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit. The method includes encoding the first data payload into a first codeword having a first codeword size. The method includes encoding the second data payload into a second codeword having a second codeword size, the second codeword size being different from the first codeword size. The method includes writing the first codeword and the second codeword to a first page in the solid-state non-volatile memory. Systems and machine-readable media are also provided.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: An encoder encodes data to generate corresponding encoded data. The encoder includes a data processing arrangement for applying one or more encoding processes to the data to generate the encoded data. The data processing arrangement is operable to represent the data at least partially in a set of numerical value symbols, if the data is not already expressed in numerical value symbols. The data processing arrangement is operable to generate intermediate data in which the numerical value symbols are represented by original values and at least one symbol by a modified value with one or more continuum symbols generated by a continuum operator. The one or more continuum symbols modify preceding symbol values to accommodate an extended range of symbols.

Abstract: A decoder arrangement (10) includes a processor (12) programmed to decode multiple streams (111-11n), including multiple streams of different formats. In terms of functionality, the decoder arrangement includes a routing stage (13) routes each streams to different decoder stages (141-14n), each capable of decoding a stream of a particular format to yield an uncompressed stream at its output. Each of plurality of buffer stages (161-16n) stores a successive frame of an uncompressed stream output by an associated decoder stage. An output stage scales and the frames stored by the buffer stages to a common size for input to a display device (22).

Abstract: An encoder encodes data to generate corresponding encoded data. The encoder includes a data processing arrangement for applying one or more encoding processes to the data to generate the encoded data. The data processing arrangement is operable to represent the data at least partially in a set of numerical value symbols, if the data is not already expressed in numerical value symbols. The data processing arrangement is operable to generate intermediate data in which the numerical value symbols are represented by original values and at least one symbol by a modified value with one or more continuum symbols generated by a continuum operator. The one or more continuum symbols modify preceding symbol values to accommodate an extended range of symbols.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: A system and method of transmitting electronic voucher through short message. The method of transmitting an electronic voucher through a short message includes converting an electronic voucher to be transmitted into a bit stream; mapping each n-bits of the bit stream to any one text character of one of a plurality of text character groups, wherein text characters in each of the text character groups have at least one same or similar feature, and bit number n corresponding to each text character depends on the number m of the text character groups; arranging the text characters obtained through the mapping into a character sequence; and transmitting the character sequence through a short message. The present invention greatly reduces the cost for issuing an electronic voucher, significantly increases the convenience and apparently improves the safety and the stability.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of symbols and (ii) a plurality of decision values both in response to detecting an encoded codeword. The second circuit may be configured to (i) generate a plurality of probabilities to flip one or more of the symbols based on the decision values, (ii) generate a modified probability by merging two or more of the probabilities of an unreliable position in the symbols and (iii) generate a decoded codeword by decoding the symbols using a list decode technique in response to the modified probability.

Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.

Abstract: An encoding apparatus and method in a communication/broadcasting system are provided. When an encoding symbol is generated using at least one source symbol from among total source symbols to be encoded, encoding symbols are generated by using each of the total source symbols with a uniform probability before repeatedly using any of the total source symbols.

Abstract: Embodiments of the invention relate to a method, apparatus and computer readable storage medium wherein the method comprises; padding a data block of a data structure to enable encoding of the data block; encoding the data block; reducing the size of the encoded data block; and spreading the data block.

Abstract: A method of decoding an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time ?, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.

Abstract: An encoding method includes searching a search target symbol string within a specific range from the end of a symbol string, which has been utilized for encoding, for a match symbol string corresponding to a beginning symbol string of a symbol string to be encoded, encoding the beginning symbol string based on a distance between the match symbol string and the beginning symbol string, and a length of the match symbol string.

Abstract: A decoding device has a buffer configured in memory to store N code streams and N decoders connected in series. Each of N decoders decodes a corresponding code steam and sequentially generates partial symbols of M bit width each unit cycle. Among the N decoders, i (i>=2) stage decoders stores multiple probabilistic models in the memory. In each unit cycle, the decoder receives an input of i?1 partial symbols which contains partial symbols generated by the i?1 stage decoder in the former unit cycle, selects one probabilistic model among the multiple probabilistic models based on i?1 partial symbols which are entered previously, generates one partial symbol using previously selected probabilistic models, and outputs the previously generated one partial symbol along with previously entered i?1 partial symbols.

Abstract: A method codes information, wherein bits that are to be coded are divided into successive first blocks. Second blocks are determined, respectively, by applying a permutation to each of the first blocks. Third blocks are determined by interleaving each of the first blocks with a respective second block. The third blocks are convolution coded, and the bits are combined to form symbols according to the convolutional code. There is a related method for decoding and devices for carrying out the methods.

Abstract: Provided is a method for generating codewords. The method comprises the following steps: receiving an information bit; generating a generating matrix in which a size of a column is identical with a length of the information bit, a size of a row is 24 rows, and values of symbols that are elements of the matrix are 0 or 1; modifying the generating matrix by dividing the generated generating matrix into an upper group and a lower group having an identical size and replacing rows so that the number of symbols having a value of 1 in the upper group is identical with the number of symbols having a value of 1 in the lower group; and obtaining inner products from the information bit and each row of the modified generating matrix and generating codewords from remainders obtained by dividing the inner products by 2.

Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.

Abstract: A circuit arrangement includes a first light emitting diode and a second light emitting diode emitting light of different colors arranged adjacent to each other for additive color mixing. A first and second controllable current sources are connected to the first and second light emitting diode, respectively, such that the load currents of the light emitting diodes depend on respective control signals received by the current sources. First and second sigma-delta modulators are connected to the first and second light emitting diodes, respectively, and provide bit-streams as control signals to the current sources. The mean value of each bit-stream corresponds to the value of an input signal of the respective sigma-delta modulator.

Abstract: At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword.

Abstract: Encoding and/or decoding of messages. On the encoding end, a composite encoder encodes message from an internal format that is used by internal system components into an external format. However, the composite encoder may encode the outgoing messages into different external formats on a per-message basis. For incoming message, a composite decoder decodes incoming messages from any one of a plurality of external formats into the internal format also on a per-message basis. A per-message report mechanism permits internal system components and the encoding/decoding components to communicate information regarding the encoding or decoding on a per message basis. This permits a higher level of collaboration and complexity in the encoding and decoding process.

Abstract: An input bit stream is received and zone statistics such as zones count, zones center bit positions, and zones lengths are determined, where a zone is a set of non-transitioning bits in the input bit stream. Beginning and ending bit positions for each zone are determined simultaneously, and each beginning bit position is associated with an ending bit position. Zone statistics are calculated using the determined beginning and appropriate ending bit positions.

Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

Abstract: Methods and systems are described for combining sources in a data compression system. In a system in which a context model results in the production of multiple sources or symbols, each source being associated with a probability estimate, sources may be combined by defining another, reduced size, set of probabilities. The new set of probabilities may be a subset of the predefined set of probabilities provided by the context model. Minimizing relative entropy may be a basis upon which to define a mapping of predefined probabilities to the new set of probabilities. An input sequence that was modeled using the context model may then be entropy encoded and entropy decoded using the new set of probabilities based on a mapping between the new probabilities and the predefined probabilities.

Abstract: An encoding apparatus that converts m-bit data words into n-bit code words, where m and n are both integers and satisfy an expression 2n?2m×2, includes a first conversion table in which 2m m-bit data words are associated with 2m n-bit code words selected from 2n n-bit code words, a second conversion table in which the 2m m-bit data words are associated with 2m n-bit code words that have been selected from the 2n n-bit code words and that do not overlap with the 2m n-bit code words in the first conversion table, and an encoder configured to select and output an n-bit code word with which an m-bit data word that has been input is associated in the first conversion table or an n-bit code word with which the m-bit data word that has been input is associated in the second conversion table, the selected and output n-bit code word having a smaller number of symbols “1”.

Abstract: An encoding apparatus and method in a communication/broadcasting system are provided. When an encoding symbol is generated using at least one source symbol from among total source symbols to be encoded, encoding symbols are generated by using each of the total source symbols with a uniform probability before repeatedly using any of the total source symbols.

Abstract: A block-coded group modulation method includes generating a symbol by grouping at least one bit of a data bit stream into one group, classifying the symbol into an n number of sections, and generating an n number of initial information bits. Next, the method includes setting up the size of a pulse corresponding to signal energy transmitted through each of the n sections, generating an additional information bit on the basis of the number of cases according to the sequence of the energy sizes, and generating final information bits by inserting the additional information bit into the initial information bits.

Abstract: This disclosure relates to the transmission of binary data over a network between a transmission host and a receiving host. The transmission host receives packets of data including data in a first format which may be ASCII formatted and contain 6 bits-per-byte words, and including data which had an original binary format containing greater than 6 bits-per-byte words (such as 8 bits-per-byte) and which has been encoded (such as Uuencoded) to 6 bits-per-byte words. The transmission host searches the packets and identifies the encoded data and reverse codes the encoded data to its original binary format, before transmitting the data on a suitable network transmission media that can transmit both ASCII formatted data and data having greater than 6 bit-per-byte formats. The transmission host also includes an application packet demultiplexer for separating the incoming data according its application such as HTTP, NNTP, FTP, etc.

Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.

Abstract: A data redundancy elimination system. In particular implementations, a method includes accessing a data block; dividing the data block into a plurality of data chunks; computing chunk signatures for the plurality of data chunks; identifying a plurality of anchor chunks in the plurality of data chunks; accessing a second memory to identify one or more matching chunk signatures; reading one or more signature blocks corresponding to the matching chunk signatures from a first memory into the signature block search space of the second memory; and matching one or more computed chunk signatures to chunk signatures of the one or more signature blocks in the signature block search space.

Abstract: A binary conversion circuit includes: a latch circuit that latches phase information of at least one clock signal when the level of a signal is inverted, the level of the signal being inverted based on its state; at least one conversion circuit that converts the latched phase information of the latch circuit to a pulse train in response to a pulse signal; and a ripple counter section that converts phase information of a clock to a binary code by using the pulse obtained by the conversion of the conversion circuit as a count clock.

Abstract: Embodiments described herein may include example embodiments of a method, article and apparatus for compressing data utilizing combinatorial coding with specified occurrences which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communication between computing platforms via a network or other interconnection medium.

Abstract: The invention relates to a method for coding a data word having a prescribed quantity of arbitrary data symbols and a prescribed quantity of a reference data symbols, wherein a checksum with a prescribed quantity of cheek symbols is calculated for the data word and the quantity of arbitrary data symbols corresponds at least to the quantity of check symbols of the checksum.

Abstract: A bit coding method modifies the bit-steam information in such a way as to provide a very high compression during lossless symbol coding and may be used as a preprocessor for Huffman and arithmetic encodings or on its own. A bit rearrangement scheme (BRS) improves the run length within a data symbol set and achieves a more efficient data-to-symbol mapping. The BRS is implemented on the data symbol set in a column-by-column fashion. The BRS can be combined with any available lossless coding scheme, providing for a more efficient lossless bit coding scheme (ALBCS).

Abstract: A system for the context-based for the context-based encoding of an input signal includes a domain transform module and a context-based coding module. The domain transform module is operable to convert the input signal into a sequence of transform coefficients c[i]. The context-based coding module includes a bit-plane scanning module, and context modeling module, and a statistical encoding module. The bit-plane scanning module is operable to produce a bit-plane symbol bps [i,bp] for each transform coefficient c[i] and each bit-plane [bp]. The context modeling module is operable to assign one or more context values to each of the received bit plane symbols bps [i,bp]. The statistical coding module is operable to code each of the bit plane symbols bps [i,bp] as a function of one or more of the corresponding context values to produce a context-based encoded symbol stream.

Abstract: A system stores compressed literal symbols in a first data block and encoded literal symbols in a second data block. The compressed literal symbols correspond to a first group of literal symbols and the encoded literal symbols correspond to a second group of literal symbols. Each of the second group of literal symbols occurs subsequently in a symbol stream to a literal symbol with the same value in the first group of literal symbols.

Abstract: Digital video data is transmitted from a video source (61) to a video sink (62) as a group of three multilevel symbols (611, 612, and 613) per pixel color with each associated symbol being sent at a rate of three times the pixel clock (601). When eleven levels are used per symbol (611) and undesirable symbol groups having excess DC residual or minimal energy are eliminated, and a built-in-test symbol group is added for pixel alignment; there results a one-to-one correspondence between the remaining symbol groups available and the two-hundred and sixty possible states that are used in the TMDS physical layer that is in widespread commercial use.

Abstract: A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.

Abstract: A circuit for converting data of a signal line in the form of logical pulses of current to RS232 level voltages between an air-conditioner and a computer is described. The conversion circuit is able to troubleshoot the communication signals between the indoor unit and outdoor unit of an air-conditioner.