Abstract: A method for modulating a video input signal received into a modulation circuit is disclosed. A first step of the method generally comprises (A) during a first modulation pass, generating (i) a primary frame by inserting a plurality of primary synchronization codes into the video input signal, (ii) a secondary frame by inserting a plurality of secondary synchronization codes into the video input signal, (iii) a plurality of first values and a first digital sum value both for the primary frame and (iv) a plurality of second values and a second digital sum value both for the secondary frame. A second step of the method generally comprises (B) during a second modulation pass, generating a video output signal presented from the modulation circuit by modulating the video input signal using one set of (i) the first values and (ii) the second values as determined by the first digital sum value relative to the second digital sum value.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract: In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum.

Abstract: A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler 302. The second RLL coding unit generates a second coded sequence by subjecting the digital signal sequence, which is outputted from the first signal processing unit and on which the predetermined signal processing has been performed by the signal processing unit, to run-length limited coding.

Abstract: A seed generator for a scrambler comprises a seed set identifier that identifies a seed set based on received user data symbols, which include a plurality of M-bit symbols. A seed selector selects a scrambling seed for the scrambler from the seed set based on Hamming distances between at least two of the M-bit symbols in the seed set.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: Methods, algorithms, software, circuits, architectures, and systems for conditionally encoding information and processing conditionally encoded information. The present invention takes advantage of codes where most randomly selected data units fulfill the coding constraints. Thus, only those data units that need encoding (i.e., that do not fulfill coding constraints) are encoded, and those data units that do not need encoding (i.e., that fulfill coding constraints) are not encoded. By doing so, one may increase the density, bandwidth and/or gain of data communications, increase the error checking and/or correcting capabilities of a data communications system, and/or reduce interference in a multi-user system.

Abstract: Subversive DSV (SDSV) sequences of data symbols having a large absolute value of DSV are extremely valuable in the copy protection of optical discs as they can induce uncorrectable read errors. However, very few SDSV sequences of data symbols can be found in multimodal codes such as Eight-to-Sixteen Modulation (ESM) utilised in DVDs. It is required to select data symbols, for encoding using a multimodal code, which are capable of forcing an encoder to produce at least one subversive sequence of code words. A possible code word for a data symbol is selected if the code word has a large absolute value of DSV and there are no alternative code words, or all alternative code words are equivalent, or all alternatives except one are ruled out by RLL rules.

Abstract: Methods and apparatus are provided for partitioning a stream of binary input data into two binary output streams for supply to respective modulation encoders in a modulation coding system. A 4-ary enumerative encoding algorithm is applied to each of a succession of input words in the input bit-stream to produce a succession of 4-ary output symbols from the input word. The 4-ary algorithm simultaneously encodes respective j=? Fibonacci codes in the odd and even interleaves of the input word such that the two bit-sequences formed by respective corresponding bits of the succession of output symbols are range-limited codewords. The two binary output streams are then produced by separating the two range-limited codewords generated from each successive input word. The binary output streams can then be independently encoded by respective modulation encoders, and the encoder outputs interleaved to produce a modulation-constrained output stream. Corresponding decoding systems are also provided.

Abstract: According to the present disclosure, a transmitter for transmitting control characters to a display device over an interface includes a transmitter portion configured to transmit a control character having a plurality of bit values to the display device. The transmitter also includes logic configured to determine values of the bits in the control character and construct a corresponding plurality of rebalancing control characters based on the determination of the values of the plurality of bits in the control character to have bit values selected such that the combination of the control character and rebalancing control character is DC balanced. As such, the transmitter provides DC balance correction to non-DC balanced control characters in such a way as to allow DVI and HDMI to operate properly on an AC-coupled connection.

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract: It is an object of the present invention to provide coding techniques which allow for higher efficiency and easier synchronization with coded data. In order to attain the object, a coding device according to the present invention converts 2-bit informational data into 4-bit coded data according to a predetermined coding rule. According to the coding rule employed in the coding device, one of four possible kinds of bit strings of informational data is converted into alternately a bit string of four bits in which each of values of two successive bits is “1” and a bit string of four bits in which each of values of all bits is “0”. Then, the other kinds of bit strings are converted into bit strings of four bits which differ from one another, in each of which a value of only one bit is “1”.

Abstract: A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit (“RLL”) constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.

Abstract: Methods and apparatus are provided for modulation coding of input data. In a first scheme, a modulation encoder applies a modulation code to input data to produce an (L,K)-constrained encoded bit-sequence, where K is maximum run-length of 0's, and L is the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence. Then, a precoder effects 1/(1?D4) preceding of the encoded bit-sequence. In a second scheme, a modulation encoder applies a modulation code to the input data to produce a K-constrained encoded bit-sequence. In this scheme, a precoder then effects 1/(1?D?D2?D3) preceding of the encoded bit-sequence. In both schemes, the effect of the precoder is to produce a precoded sequence in which, in addition to other constraints, the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value CVFO.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients which are obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table that is selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table that is selected according to the number of already-processed run values.

Abstract: The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N?2k?2+k?1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k?1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.

Abstract: A computerized system for representing a digital media using both a bit stream and an associated metadata includes a codec configured to encode the digital media to the bit stream. The codec is further configured to generate a metadata representation stream of the bit stream that encapsulates information embedded in the bit stream and at least one type of media-related information. The system also includes a manager configured to assure synchronization between the bit stream and the metadata representation stream during streaming of the bit stream and the metadata representation stream.

Abstract: In accordance with one or more embodiments data may be encoded into a code word that meets run length constraints and has a reduced running digital sum by encoding (N?y)?1 data bits and y flag bits into m first n-bit patterns that form a first N-bit code word, producing a second N-bit code word by encoding the (N?y)?1 data bits and the y flag bits into m second n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold, and selecting the code word that satisfies selection criteria. The selection criteria may, for example, be the word with the fewest transitions, the word with the smallest running digital sum, and so forth.

Abstract: An unencoded m-bit data input sequence is divided into a block of n bits and a block of m?n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m?n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

Abstract: An apparatus and method for sampling a plurality of digital video signals to generate an interleaved digital video signal is disclosed. The apparatus includes: a first analog-to-digital converter (ADC), coupled to an analog input signal, for converting the analog input signal to a first digital output signal according to a sampling clock signal; a second ADC, coupled to the analog input signal, for converting the analog input signal to a second digital output signal according to the sampling clock signal; a reference clock generator, for generating a reference clock; a random signal generator, for outputting control values in a random sequence; and a clock controller, coupled to the reference clock generator and the random signal generator, for modifying the reference clock signal according to the control values to generate the sampling clock signal to the first ADC and the second ADC.

Abstract: An encoder includes a mapping module that receives input words including first input words and second input words. The mapping module maps the first input words to first output words that are run-length limited and have a digital sum that is equal to zero. The mapping module maps the second input words to second output words that are run-length limited and have one of a positive and a negative digital sum. An inverter module selectively inverts the second output words based on a cumulative digital sum of the second output words.

Abstract: Systems and methods are provided for encoding and decoding constrained codes using an enumerative coding graph. The constrained code may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has two branches that lead to other states. Each state in the enumerative coding graph is assigned a cardinality. Configuring the structure of the graph and the cardinalities associated with each state allow the encoder to generate a code that conforms to defined constraints.

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form.

Abstract: An encoding method is disclosed for use with an encoding apparatus for carrying out variable-length conversion encoding involving a look-ahead operation of at least either one information word or one code word upon encoding. The encoding method includes the step of performing conversion encoding in such a manner as to permit decoding of encoded words in units of a code word.

Abstract: An encoder comprises a DC tracking device that generates a metric based on portions of a communication signal and an invert signal as a function of the metric, wherein the invert signal has a flip state and a nonflip state. An inverter that selectively inverts the portions based on said invert signal to reduce an average DC value of the communication signal.

Abstract: A technique for determining an optimal transition-limiting code for use in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for determining an optimal transition-limiting code for use in a multi-level signaling system. Such a method comprises determining a coding gain for each of a plurality of transition-limiting codes, and selecting one of the plurality of transition-limiting codes having a largest coding gain for use in the multi-level signaling system.

Abstract: Systems and methods for encoding/decoding are provided. The systems and methods include encoding a stream of K-bit input sequences into a stream of (G, I, M)-constrained 2N-bit output sequences by transforming each K-bit input bit sequence into two separate data paths including even and odd bits. Enumerative maximum-transition-run (eMTR) encoding of the even bits generates constrained even bits, and enumerative maximum-transition-run (MTR) encoding of the odd bits generates constrained odd bits. The constrained even and constrained odd bits are interleaved to form a stream of (G, I, M)-constrained 2N-bit output sequences where G is a global constraint, I is an interleave constraint, and M is a variable frequency oscillator constraint of a partial-response maximum-likelihood (PRML) codeword. Decoding systems and methods are also provided.

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A run-length limited (RLL) encoder includes a block detection module that receives a data block that includes N portions and generates N?1 coding bits indicating whether corresponding ones of N?1 of the N portions of the data block include one of all ones and all zeros, where N is an integer greater than two. A mapping module generates an RLL codeword including N portions comprising bits that are determined by a first mapping table, a second mapping table, bits of the data block and the N?1 coding bits.

Abstract: A method and apparatus for improved efficiency in protocols using character coding have been disclosed.

Abstract: A circuit to reduce noise spikes on the power and ground rails of a chip when switching over an input-output bus, the circuit comprising an encoder to encode a word before transmission over the input-output bus so that the difference in the number of 1 bits and the number of 0 bits in the encoded word is upper bounded, where the upper bound is less than the length of the original word before encoding. An embodiment circuit to implement this encoding comprises partitioning the word into a plurality of smaller words. An embodiment circuit further comprises a number of stages, where in the first stage, there are a plurality of encoders to encode in pair-wise fashion the smaller words. Additional stages also comprise a plurality of encoders, each encoder performing a pair-wise encoding of words outputted by a previous stage. Other embodiments are described and claimed.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: Method of converting information words, which includes receiving m-bit information words, where m is an integer, and converting the m-bit information words into n-bit code words based on a code conversion table including a plurality of coding states, where n is an integer greater than m. The plurality of coding states are categorized into a first kind or a second kind and a number of coding states of the first kind is greater than a number of coding states of the second kind. Each coding state includes at least two code words of a same value representing information words of a different value, and a minimum number of zeros between consecutive ones in the n-bit code words is 1.

Abstract: In a perpendicular magnetic recording system, the data that is being written by the write channel is fed back into the read channel. The read channel processes the data and decides if the written sequence is likely to have very poor DC characteristics. If that is the case, the write channel changes a scrambler seed and rewrites the data using the new scrambler seed. The data may also be inspected for patterns that might cause large baseline wander before being written to disk, i.e., in the write channel. A data sequence may be repeatedly scrambled and encoded until an acceptable level of estimated DC-wander has been achieved. The data sequence may then be written to disk.

Abstract: A system and method for increasing transmission distance and/or transmission data rates using tedons and an encoding scheme to reduce the number of ones in a data signal is described. For example, the method for increasing transmission distance and transmission data rate of a fiber optical communications link using tedons includes the steps of encoding a data signal to be transmitted using an encoding scheme that reduces a number of ones in the data signal, transmitting the encoded data signal over the fiber optical communications link, receiving the encoded data signal and decoding the encoded data signal.

Abstract: A data encoding and decoding method capable of lowering signal power spectral density for a binary data transmission system is disclosed. The data encoding method includes receiving binary data, performing adaptive mode tracking encoding for the binary data to generate a first encoding result, performing bit stuffing encoding for the first encoding result to generate a second encoding result, performing bit stationary state resuming encoding for the second encoding result to generate a third encoding result, and outputting the third encoding result.

Abstract: An encoding system for a high density optical storage medium includes a conversion module that receives a data pattern and generates a code pattern based on the data pattern. A code connector module receives the code pattern, determines whether the code pattern includes a first predetermined code pattern, and outputs a substitution code pattern when the code pattern includes the first predetermined code pattern. The first predetermined code pattern includes first and second consecutive code words that include first and second bit sequences “01010*” and “??????,” respectively, “?” corresponds to an in consequential bit, and “*” corresponds to an undetermined bit.

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract: A modulation apparatus and method employs first and second conversion means for translating input data into an alternate form for recording. The first conversion means converts a portion of input data matching a first data pattern into a first code pattern in accordance with a first table which maintains an even/odd-characteristic and a second conversion means converts a portion of input data matching a second data pattern into a second code pattern in accordance with a second table which does not maintain an even/odd-characteristic.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: There is provided an apparatus which obtains a circumstance where LDPC codes are interleaved without damaging modulation rules and thereby a correction ability of LDPC encoding and decoding method is fully exhibited. The apparatus includes an RLL rule applying section which modulates user data by applying an RLL rule to the user data and thereby obtains RLL encoded sequence data, an interleave section which interleaves the RLL encoded sequence data and thereby obtains interleaved sequence data, an LDPC parity generating section which subjects the interleaved sequence data to LDPC encoding processing and thereby obtains LDPC parity sequence data, an inserting section which inserts parity of the LDPC parity sequence data in the RLL encoded sequence data in a distribution manner and thereby obtains output data, and an output section which records or transmits the output data.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: Embodiments of the invention generally provide methods, systems, and articles of manufacture for selecting a data bus inversion (DBI) mode of operation. A comparison circuit of a device may receive multiple packets of data to be transmitted to another device over a bus connecting the devices. The comparison circuit may compare the multiple packets of data and select a DBI mode of operation that conserves power and reduces noise on the bus.

Abstract: A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler 302. The second RLL coding unit generates a second coded sequence by subjecting the digital signal sequence, which is outputted from the first signal processing unit and on which the predetermined signal processing has been performed by the signal processing unit, to run-length limited coding.

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.