Abstract: A method for data processing is disclosed. A blank state is determined for several data bits based on a majority decision. Each data bit is represented by a group of at least two memory cells. The at least two memory cells of this group are complementary cells of a differential read memory.

Abstract: A device that provides for the non-invasive data monitoring of analog IO of a Programmable Logic Controller (PLC) system is described. The output is ultimately presented to a user audibly and/or visually on an interface in real-time and is measured directly from the IO channel. This type of device allows the accurate reading and analysis of errors and erroneous data within a device and transmission of said data to disparate secondary devices for use.

Abstract: A system for compressing digital data by representing a portion of it predictionally and transformationally as a block of transform coefficients, then quantizing that block selectively into a set of encoding symbols based on an indication whether the transform coefficients represent the portion as having a particular characteristic, and then by encoding the set of encoding symbols into a data bit stream. In particular, frequency may be used as the characteristic of the digital data in many applications.

Abstract: A blasting device includes a flow passage (14) for a carrier gas, the flow passage (14) forming a blasting nozzle (12) at its downstream end, and a supply line (22) for liquid CO2, the supply line opening out into an expansion chamber (26) that is coaxially accommodated in the flow passage (14), the expansion chamber (26) being formed by a pipe (20) that is held at its upstream end by a holder' (18) which is passed by the flow of carrier gas in the flow passage, and in that the supply line (22) extends through the holder (18) in transverse direction of the flow passage and opens into an expansion valve (24) that extends in parallel with the axis of the flow passage (14).

Abstract: The invention relates to a method for the compression of data comprising values to be coded, in particular grey values or prediction errors using a run-length coding. A bit sequence of a bit plane which represents at least one item of partial information of at least one value to be coded is thereby coded coherently. This method is particularly used in connection with medical image data.

Abstract: A character-information conversion apparatus is configured to process character information including attribute information indicating a coding system and character codes conforming to the coding system and for converting the character codes into characters. The apparatus includes a key operation unit, an EEPROM, and a controlling unit. The key operation unit specifies a coding system to be applied to decode character codes conforming to a coding system other than a normally applied coding system. The EEPROM stores information indicating the coding system corresponding to the received input. The controlling unit refers to the attribute information and determines which coding system the character codes conforms to, converts the character codes into characters based on the information stored in the EEPROM when it is incapable of determining the coding system or when it is determined that the coding system differs from the normally applied coding system.

Abstract: Methods, systems and data structures select prioritized robust data values from a plurality of available data values formed by a plurality of data bits, each capable of exhibiting a bit value. Available data values are arranged into a gray code format, and alternate values of gray code format are selected to form a value map. An optional complementary value map may also be formed from the remaining data values. The value map is then prioritized according to bit adjacencies, wherein bit adjacencies are defined by contiguous bits within one of the data values that exhibit a common bit value. Priority may be given to data values having shortest and/or fewest bit adjacencies.

Abstract: An input/output controller for an extension unit of a programmable logic controller (PLC). The input/output controller has a first port connected to the PLC and a second port connected to a terminal device of the extension unit. A memory is provided to save data received from the first port and the second port. A mode-selecting circuit of the input/output controller includes a plurality of preset operation modes, which determine the input or output type of the first and second port, data-transmitting format used by the first and second port, and data-saving format used in the memory. Thus, the PLC can receive data from the terminal device, or can transfer predetermined data to the terminal device through the input/output controller of the present invention.

Abstract: An input/output controller for an extension unit of a programmable logic controller (PLC). The input/output controller has a first port connected to the PLC and a second port connected to a terminal device of the extension unit. A memory is provided to save data received from the first port and the second port. A mode-selecting circuit of the input/output controller includes a plurality of preset operation modes, which determine the input or output type of the first and second port, data-transmitting format used by the first and second port, and data-saving format used in the memory. Thus, the PLC can receive data from the terminal device, or can transfer predetermined data to the terminal device through the input/output controller of the present invention.

Abstract: In a method for transmitting digital data of images, etc., under the condition of n>m and k<n-m, when the synchronous data are not transmitted, the image data of "m" bits for the respective pixels are translated into the n-bit codes, of which identical logical bits do not continue more than or equal to "k" even if they are sequentially time-division multiplexed and transmitted with any combination, and then time-division multiplexed and transmitted. On the other hand, when the synchronous data are transmitted, the m-bit image data of the pixel is directly time-division multiplexed, and to this data, a serial code which is composed of "n-m" bits and including the specific bit string which is the continuous "k" bits of the identical logic is added. Thereby, making it possible to perform transmission and reception of the digital data and the synchronous data through one transmission line without a break of transmission or reception of the image data.

Abstract: A system for compressing bilevel data includes a first cache memory having a plurality of assigned levels of usage, a first usage level assigned to a most recently used data segments and a second level assigned to a plurality of less recently used data segments. A processor determines if a received data segment is found in the cache memory and, if not, it assigns the received data segment to the cache memory's first level in place of a previous data segment stored therein. The previous data segment is assigned to a position in the second level in place of a less recently used data segment. The less recently used data segment that is displaced is chosen by a pseudo-random method. A not-found indication is then transmitted to a receiving station along with the identity of the received data segment. The receiving station contains identical cache structures and updates its caches in response to received code words and data segments.

Abstract: A high-speed universal scaler operates in real time, accepting as an input an N-bit binary data word which is to be scaled (multiplied) by a scale factor specified in units per bit. The input data word is divided into M-bit sections which are provided (together with a count value indicating the position of the M-bit section within the input data word and a scale indicator value specifying which of a plurality of programmed scale factors values is to be used) sequentially as scaling addresses specifying binary coded decimal scale data in a scale memory. The sequential outputs of the scale memory in response to the scaling addresses are summed. When the sequence of addresses has been completed and all of the sequential memory outputs have been summed, the resulting sum will be a scaled binary coded decimal value equivalent to the input data word.

Abstract: A bit pattern conversion system for converting a sequence of a bit pattern between a central processing unit and a peripheral circuit, including a data bus line connected between the central processing unit and the peripheral circuit, and a conversion circuit provided in the peripheral circuit for converting the sequence of the bit pattern from a most significant bit to a least significant bit, and vice versa, in accordance with a conversion signal.