Abstract: An object of the present invention is to provide an image processing apparatus in which a delay from start of image data input to start of coding is small, the capacity of a temporary storage device used for temporarily storing the image data to be coded is small, and the possibility of discarding the image data is low even when coding is delayed and, therefore, the image quality is hardly degraded. Since this apparatus is provided with a flag generator for generating control information according to the processing status, input/output of the image data in/from the temporary storage device is performed for each unit amount, and storage and coding of the image data are executed according to the control information.

Abstract: A graphics system in which the dedicated graphics memory is doubly virtualized: it can be paged into host physical memory, and also, beyond that, into host bulk storage. Portions of host physical memory which are needed to support the graphics memory management process can be locked down.

Abstract: The monitor system comprises the display device which has a screen having a display area virtually divided into a plurality of sub-screens. Provided are graphics adapters, each of which has two frame buffers, so as to correspond to the sub-screens of the display device.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A reconfigurable graphics pipeline has a hidden surface removal stage that may be placed at different locations within the pipeline depending on pipeline rendering mode. When the pipeline operates in certain rendering modes, the hidden surface removal operation can be performed early in the pipeline—allowing the pipeline to avoid wasting its time imaging obstructed surfaces. For other (e.g., alpha based) rendering modes, the hidden surface removal operation is performed near the end of the pipeline—when the pipeline has developed sufficient additional information required by the particular rendering mode to resolve depth comparisons.

Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.

Abstract: A 3D graphics controller configurable to simultaneously copy portions of a pixel region between a back buffer and a front buffer. The 3D graphics controller includes four memory controllers, each controlling a bank of frame buffer memory. A sequence of addresses defining a pixel region is generated. The addresses are distributed to the four memory controllers according to the memory banks (addresses) coupled thereto. Each memory controller is configured to read pixels according to the addresses and a first offset; and write the pixels according to the addresses and a second offset. The offsets are chosen so as not to shift pixels within the banks. Therefore, each memory controller simultaneously and independently copies a portion of the pixel region without accessing any other memory banks resulting in a copy of the entire pixel region.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

Abstract: A data processing apparatus generates original waveform data based upon which musical tone data are to be generated, and sounding control data containing kind information indicative of kinds of the original waveform data and pitch information indicative of pitches of the musical tone data, and generates original image data based upon which image data are to be generated, and picture control data containing kind information indicative of kinds of the original image data and coordinate information indicative of coordinates of the image data on a display screen.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: A multi-function controller in a computer graphics system performs the functions of a graphics processor, a video processor, a system memory controller, a cache controller, and a PCI bridge. The multi-function controller is connected to the host bus of the computer graphics display system to maximize performance. A graphics frame buffer and a system memory are combined into a unified system memory, which is controlled by and coupled to the multi-function controller.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A computer system having a highly parallel system architecture with multiple central processing units, multiple core logic chipsets and pooled system memory is provided with one or more AGP ports capable of connection to AGP devices. A memory manager is provided within the operating system for allocating pooled memory resources without regard to the location of that memory. A method is presented for dynamically allocating memory for the AGP device that is located on the same core logic chipset to which the AGP device is connected. By allocating local memory instead of allocating memory on remote core logic units, the AGP device can access the needed memory quickly without memory transmissions along the host bus, thereby increasing overall performance of the computer system.

Abstract: A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: The present invention provides a low-cost computer system which includes a single sharable block of memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the “appetite” for main system memory (unlike that of a display memory) is difficult to satisfy, the memory can be addressed by reallocating an unused portion of a display memory for system memory use. Reallocation of the unused display memory alleviates any need to oversize the display memory, yet realizes the cost effectiveness of using readily available memory sizes. Further, reallocation of the graphics memory avoids any need to separately consider both the system memory and the display memory in accommodating worst case operational requirements. In accordance with additional embodiments, improved efficiency of operation can be achieved to enhance concurrency between plural banks of memory when expansion memory is included.

Abstract: A display controller has a display data RAM, and generates a frame frequency in an internal oscillating circuit. A memory area of the display data RAM corresponds to a moving image display area of a liquid crystal panel. The liquid crystal panel is driven by moving image data read from the display data RAM at the frame frequency. In the display controller, display data generated at a frame frequency lower than the frame frequency from a display data generation circuit is written to the display data RAM. In this case, a control operation is performed such that the display data is read at the frame frequency after a write operation is performed precedently by at least one scanning line.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: An MPEG decoder and an MPEG decoding method with two memory controllers is capable of separately controlling compressed data and decoded data. An MPEG decoder decodes a compressed input data formatted in an MPEG type. The MPEG decoder comprises a compressed data memory controller and a decoded data memory controller. The compressed data memory controller is coupled to a compressed data memory and controls the compressed data. The decoded data memory controller is coupled to a decoded data memory, and controls the decoded data. Since the compressed data flow and the decoded data flow are divided, the memory transfer rate is increased, and also the memory control is simple. In addition, the compressed data are able to be stored within the MPEG decoder. Therefore, the high-performance of the MPEG decoder and the high quality of the image are possible.

Abstract: A computer system having a highly parallel system architecture with multiple central processing units, multiple core logic chipsets and pooled system memory is provided with one or more AGP ports capable of connection to AGP devices. A memory manager is provided within the operating system for allocating pooled memory resources without regard to the location of that memory. A method is presented for dynamically allocating memory for the AGP device that is located on the same core logic chipset to which the AGP device is connected. By allocating local memory instead of allocating memory on remote core logic units, the AGP device can access the needed memory quickly without memory transmissions along the host bus, thereby increasing overall performance of the computer system.

Abstract: The present invention provides a graphics memory system of a computer graphics display system which utilizes a batching architecture in conjunction with detached Z buffering for minimizing paging overhead. The graphics memory system comprises a memory controller which receives a batch of pixels from a host CPU of the computer graphics display system when a 3D rendering mode is in effect. Each pixel has a pixel color and corresponding Z coordinate associated with it. The memory controller then performs a Z comparison test wherein Z coordinates of the batch are compared with existing Z coordinates read out of a frame buffer memory to determine whether or not each new color of the batch associated with the Z coordinate being compared should be written into the frame buffer memory. If the results of a Z comparison test pass, the new pixel color and Z coordinate are queued for writing into the frame buffer memory.

Abstract: An apparatus and method for processing ultrasound data is provided. The apparatus includes an interface operatively connected to a memory, a programmable single instruction multiple data processor (or two symmetric processors), a source of acoustic data (such as a data bus) and a system bus. The memory stores data from the processor, ultrasound data from the source, and data from the system bus. The processor has direct access to the memory. Alternatively, the system bus has direct access to the memory. The interface device translates logically addressed ultrasound data to physically addressed ultrasound data for storage in a memory. The translation is the same for data from both the processor and the source for at least a portion of a range of addresses. The memory stores both ultrasound data and various of: beamformer control data, instruction data for the processor, display text plane information, control plane data, and a table of memory addresses. One peripheral connects to the ultrasound apparatus.

Abstract: The monitor system comprises the display device which has a screen having a display area virtually divided into a plurality of sub-screens. Provided are graphics adapters, each of which has two frame buffers, so as to correspond to the sub-screens of the display device.

Abstract: The present invention provides a graphics memory system of a computer graphics display system which utilizes a batching architecture in conjunction with detached Z buffering for minimizing paging overhead. The graphics memory system comprises a memory controller which receives a batch of pixels from a host CPU of the computer graphics display system when a 3D rendering mode is in effect. Each pixel has a pixel color and corresponding Z coordinate associated with it. The memory controller then performs a Z comparison test wherein Z coordinates of the batch are compared with existing Z coordinates read out of a frame buffer memory to determine whether or not each new color of the batch associated with the Z coordinate being compared should be written into the frame buffer memory. If the results of a Z comparison test pass, the new pixel color and Z coordinate are queued for writing into the frame buffer memory.

Abstract: A multi-function controller in a computer graphics system performs the functions of a graphics processor, a video processor, a system memory controller, a cache controller, and a PCI bridge. The multi-function controller is connected to the host bus of the computer graphics display system to maximize performance. A graphics frame buffer and a system memory are combined into a unified system memory, which is controlled by and coupled to the multi-function controller.

Abstract: Two-dimensional addresses of lateral lines of a rectangular area are produced in a prescribed scanning order in a sender-memory control unit as readout addresses of a sender's memory, pieces of pixel data corresponding to the readout addresses are read out from the sender's memory, the pieces of pixel data read out are sub-sampled at a sample ratio of n:1 in a direction of each lateral line according to a quincunx method in a data transforming unit, two-dimensional write addresses of a receiver's memory are produced in a receiver-memory control unit, and pieces of sub-sampled pixel data are written in the receiver's memory. Accordingly, the pieces of pixel data can be sub-sampled and transferred at a high speed in a DMA transfer apparatus.