Data Transfer Between System Memory Display Memory Patents (Class 345/538)
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Patent number: 8629879Abstract: Data pixels defining first and second images are stored in first and second image buffers, respectively. A second image coordinate location within a display matrix of a display device having display pixels that have multiple stable states is stored in a memory. Data pixels of the first image are read from the first image buffer. If a data pixel read from the first image buffer is within the second image coordinate location, a data pixel from the second image buffer corresponding with the data pixel read from the first image buffer is read, and the data pixel read from the second image buffer is combined with the corresponding data pixel read from the first image buffer to generate a derived data pixel. Synthesized pixels corresponding with at least each of the data pixels of the second image are generated. The synthesized pixels respectively include the derived data pixels.Type: GrantFiled: April 24, 2009Date of Patent: January 14, 2014Assignee: Seiko Epson CorporationInventors: Yun Shon Low, Eric Jeffrey
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Patent number: 8624916Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.Type: GrantFiled: April 1, 2013Date of Patent: January 7, 2014Assignee: Nvidia CorporationInventors: Narayan Kulshrestha, Adam Paul Dreyer, Chad D. Walker, Rui M. Bastos
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Patent number: 8593472Abstract: One embodiment of the invention sets forth a mechanism for retrieving and storing data from/to a frame buffer via a storage driver included in a GPU driver. The storage driver includes three separate routines, the registration engine, the page-fault routine and the write-back routine, that facilitate the transfer of data between the frame buffer and the system memory. The registration engine registers a file system, corresponding to the frame buffer, the page-fault routine and the write-back routine with the VMM. The page-fault routine causes a portion of data stored in a specific memory location in the frame buffer to be transmitted to a corresponding memory location in the application memory. The write-back routine causes data stored in a particular memory location in the application memory to be transmitted to a corresponding memory location in the frame buffer.Type: GrantFiled: July 31, 2009Date of Patent: November 26, 2013Assignee: Nvidia CorporationInventor: Franck Diard
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Patent number: 8581919Abstract: A display controller is provided. The display controller includes an external memory and a timing controller which compresses current frame data to generate front first in-first out (FIFO) input data, temporarily stores the front FIFO input data and writes the front FIFO input data to the external memory in a burst mode, and reads data from the external memory in the burst mode, temporarily stores the read data as back FIFO output data, and decodes the back FIFO output data to output previous frame data.Type: GrantFiled: March 19, 2010Date of Patent: November 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Yun Park, Won-Gab Jung, Jong-Seon Kim, Sang-Woo Kim, Hae-Yong Ahn
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Patent number: 8520009Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 29, 2009Date of Patent: August 27, 2013Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Publication number: 20130201195Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Inventors: Krishnan SREENIVAS, Koen Bennebroek, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
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Patent number: 8497867Abstract: An information processing system stores a plurality of content data having different display qualities for each content in a storage unit, and detects a user operation to instruct switching of a content displayed on a display screen, and determines a switching speed of content display on the display screen based on the detected user operation, and decides a distribution for content data of each display quality to be read out to a temporary memory unit based on the determined switching speed, and reads out the content data from the storage unit to the temporary memory unit in accordance with the decided distribution.Type: GrantFiled: November 11, 2009Date of Patent: July 30, 2013Assignee: Canon Kabushiki KaishaInventors: Masato Fujiwara, Toru Kikuchi, Daiki Kondo
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Patent number: 8456480Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.Type: GrantFiled: January 13, 2010Date of Patent: June 4, 2013Assignee: Calos Fund Limited Liability CompanyInventors: Donald James Curry, Ujval J. Kapasi
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Patent number: 8427497Abstract: Methods, software, and apparatuses for graphics processing, including caching pixel data of one or more tiles of a graphics surface. Methods generally include setting a caching bit corresponding to the surface, setting tile pattern bits corresponding to tiles in the surface, and when the caching bit is active, storing one or more pixel values in a cache memory. When at least one tile contains pixels having the same value for at least one predetermined parameter, the caching bit and the corresponding tile pattern bits may be active. Apparatuses generally include a pixel memory, a cache memory, and a controller including logic configured to reserve the caching bit, tile pattern bits, and same pixel values in cache memory when the caching bit is active.Type: GrantFiled: July 30, 2009Date of Patent: April 23, 2013Assignee: Marvell International Ltd.Inventors: Yunsen Chin, Haohong Wang
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Patent number: 8421809Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.Type: GrantFiled: May 26, 2010Date of Patent: April 16, 2013Assignee: Chimei Innolux CorporationInventor: Naoki Sumi
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Patent number: 8411103Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.Type: GrantFiled: September 29, 2009Date of Patent: April 2, 2013Assignee: Nvidia CorporationInventors: Narayan Kulshrestha, Adam Paul Dreyer, Chad D. Walker, Rui M. Bastos
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Patent number: 8405851Abstract: An image reading apparatus configured to read a document at a second resolution based on a result of reading the document at a first resolution generates image data with low data amount having small data amount from image data-for-save that has been read at the second resolution and transfers the image data with low data amount taking priority over the image data-for-save to an image processing apparatus. The image processing apparatus is configured to notify a user that next reading processing is acceptable when receiving of the image data with low data amount is completed. The image processing apparatus is configured to receive and store the image data-for-save according to the next reading processing instructed by the user.Type: GrantFiled: January 28, 2009Date of Patent: March 26, 2013Assignee: Canon Kabushiki KaishaInventor: Hiroaki Sugiura
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Patent number: 8390635Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.Type: GrantFiled: October 15, 2010Date of Patent: March 5, 2013Assignee: Broadcom CorporationInventors: Alexander G. MacInnis, Chengfuh Jeffrey Tang, Xiaodong Xie, James T. Patterson, Greg A. Kranawetter
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Patent number: 8373714Abstract: Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.Type: GrantFiled: July 30, 2010Date of Patent: February 12, 2013Assignee: Apple Inc.Inventors: John Stauffer, Bob Beretta
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Patent number: 8368707Abstract: A window surface associated with a first application is automatically detected as an exclusive window surface for a display. In response, the system automatically transitions to a full-screen mode in which a graphics processor flushes content to the display. The full-screen mode includes flipping between a front surface buffer and a back surface buffer associated with the first application. It is subsequently detected that the window surface associated with the first application is not an exclusive window surface for the display. In response, the system automatically transitions to a windowed mode in which the graphics processor flushes content to the display. In windowed mode, the system frame buffer is flushed to the display. The transition to windowed mode includes a minimum number of buffer content copy operations between the front surface buffer, the back surface buffer and the system frame buffer.Type: GrantFiled: May 18, 2009Date of Patent: February 5, 2013Assignee: Apple Inc.Inventors: Changan Lao, Kenneth C. Dyke, John Stauffer
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Patent number: 8341548Abstract: A method of configuring an image for data storage on a storage device in an overlapping-tiled format and a method of displaying a desired image selected for viewing on a display are disclosed. The method of configuring an image for data storage includes formatting an image to include a plurality of image tiles, each image tile in the plurality of image tiles having at least a portion that is substantially identical to at least a portion of an adjacent image tile in the plurality of image tiles. The method further includes converting data of the image from data in a first color space into data in a second color space so as to reduce a size of the data of the image, and storing the image data in the second color space.Type: GrantFiled: September 28, 2009Date of Patent: December 25, 2012Assignee: Pixia Corp.Inventors: Rudolf O. Ernst, Rahul C. Thakkar
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Patent number: 8295612Abstract: Change image detecting devices and methods are disclosed. In one example, a determination unit partially compares a first image and a reference image and determines whether there is a change therebetween. If the determination unit determines no change between the first image and the reference image, the change image detecting unit selects a second image, which is temporally later than the first image and stored in a first storing unit, as a new image to be processed and the determination unit partially compares the second image and the reference image at a different position than previously compared and determines whether there is a change between the second image and the reference image. If the determination unit determines change between the first image and the reference image, a change image detecting unit detects the first image stored in the first storing unit as the change image, and stores the first image in the second storing unit.Type: GrantFiled: August 31, 2011Date of Patent: October 23, 2012Assignee: Seiko Epson CorporationInventor: Issei Yokoyama
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Patent number: 8228262Abstract: Multimedia from a source can be wirelessly transmitted in a 60 GHz system to a display. To support rapid reads of encryption, EDID, and other data written into a slave at the display by a master at the source in accordance with I2C protocol, a master simulator on the display side continually polls the slave for changes, and maintains a shadow memory in a slave simulator at the source side current, so that reads from the master may be immediately executed from the shadow memory in the slave simulator without transmitting the wireless link.Type: GrantFiled: November 23, 2009Date of Patent: July 24, 2012Assignees: Sony Corporation, Sony Electronics Inc.Inventor: Robert Allan Unger
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Patent number: 8154555Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.Type: GrantFiled: October 26, 2010Date of Patent: April 10, 2012Assignee: Intel CorporationInventors: Balaji Vembu, Aditya Navale, Wishwesh Gandhi
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Patent number: 8144160Abstract: Modification to frame buffer memory information associated with a first display may be used to update information displayed on a second display. The first display may be mapped to a matrix of display areas. The modification to the frame buffer memory information may be detected be detecting write memory address. One or more display areas affected by the modification to the frame buffer memory information may be identified based on display parameters associated with the first display. Frame buffer memory information associated with the one or more affected display areas may be retrieved and compressed before being transmitted over a communication link to be displayed on the second display.Type: GrantFiled: February 14, 2008Date of Patent: March 27, 2012Assignee: Emulex CorporationInventors: Dwarka Partani, Sujith Arramreddy, Balakrishna Jayadev
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Patent number: 8144159Abstract: Techniques to generate partial display updates in a buffered window system in which arbitrary visual effects are permitted to any one or more windows (e.g., application-specific window buffers) are described. Once a display output region is identified for updating, the buffered window system is interrogated to determine which regions within each window, if any, may effect the identified output region. Such determination considers the consequences any filters associated with a window impose on the region needed to make the output update.Type: GrantFiled: May 19, 2011Date of Patent: March 27, 2012Assignee: Apple Inc.Inventors: Ralph Brunner, John Harper
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Patent number: 8140781Abstract: The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.Type: GrantFiled: December 31, 2007Date of Patent: March 20, 2012Assignee: Intel CorporationInventors: Chee Hak Teh, Arthur D Hunter
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Patent number: 8134562Abstract: A method for assisting in data calculation by using a display card: In the present method, input data stored in a system memory is transformed into texture data, which is then stored in a display memory of the display card. Then, a Graphic processing unit (GPU) of the display card is used for executing a texture calculation to the texture data, and a result of the texture calculation is stored in a display target of the display memory. Finally, the display target is outputted to the system memory as the output data. Accordingly, a part of calculation tasks of a central processing unit (CPU) can be given to the GPU of the display card when the CPU is in a high usage rate, so as to reduce a calculation burden of the CPU.Type: GrantFiled: December 31, 2008Date of Patent: March 13, 2012Assignee: ASUSTek Computer Inc.Inventors: Chih-Hao Liang, Li-Hsiang Liao
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Patent number: 8134577Abstract: A method for displaying an image in a display device initially includes storing a plurality masks in a memory. A mask of the plurality of masks is selected randomly from the plurality of masks, when control information is received for a source image and used to change the orientation of the source image. Each mask controls the transfer of image lines in a different non-sequential order based on the control information.Type: GrantFiled: August 21, 2008Date of Patent: March 13, 2012Assignee: LG Electronics Inc.Inventors: Guruprasad Nagaraj, Krishna Koteshwara Sridhar Murthy
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Patent number: 8131270Abstract: A system for mobile devices that facilitates the creation and dissemination of interactive media to a plurality of mobile devices. A computer or PC comprising an interactive media generator is used to generate interactive media and communicate it to a distribution server. Mobile devices have an interactive media client component to receive and present interactive media to a user.Type: GrantFiled: July 30, 2007Date of Patent: March 6, 2012Inventor: Bindu Rama Rao
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Patent number: 8120614Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.Type: GrantFiled: March 17, 2011Date of Patent: February 21, 2012Assignee: NVIDIA CorporationInventors: Krishnan Sreenivas, Koen Bennebroek, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
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Patent number: 8112481Abstract: A state management sub-system that assists in transmitting and processing documents and messages between two applications in a sequentially correct order through an integration server is disclosed. The state management subsystem analyzes the message and enters state information about the message into a state management table. Once the message is transformed the state management subsystem check the status of the message in the state management table, and checks all waiting parameters. Depending on the status of the check, the state management subsystem changes the state of message in the table. Only when all messages have passed the waiting parameters check is a message posted to the destination system.Type: GrantFiled: March 28, 2003Date of Patent: February 7, 2012Assignee: Microsoft CorporationInventors: Kevin Whittenberger, Sonja Jackson, Jason Ladwig
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Patent number: 8106916Abstract: One embodiment of the invention sets forth a computing system for performing cryptographic computations. The computing system comprises a central processing unit, a graphics processing unit, and a driver. The central processing requests a cryptographic computation. In response, the driver downloads microcode to perform the cryptographic computation to the graphics processing unit and the graphics processing unit executes microcode. This offloads cryptographic computations from the CPU. As a result, cryptographic computations are performed faster and more efficiently on the GPU, freeing resources on the CPU for other tasks.Type: GrantFiled: December 29, 2009Date of Patent: January 31, 2012Assignee: NVIDIA CorporationInventor: Radoslav Danilak
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Patent number: 8107775Abstract: An image processing apparatus obtains color image data by performing an interpolation processing for an image signal output from a color image pickup element having color filters arranged like a mosaic, by using a filter. The apparatus includes an interpolation processing unit which selectively modifies an interpolation processing according to a kind of layout pattern of a spatial center position of gravity of each color component signal included the image signal in an image area to be interpolated, so that the spatial center position of gravity of each color component signal after the interpolation processing becomes identical in any layout pattern, if there are a plurality of kinds of layout pattern of a spatial center position of gravity of each color component signal included the image signal in an image area to be interpolated.Type: GrantFiled: February 7, 2008Date of Patent: January 31, 2012Assignee: Olympus Imaging CorpInventor: Kenichi Onomura
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Patent number: 8098254Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.Type: GrantFiled: January 14, 2011Date of Patent: January 17, 2012Assignee: NVIDIA CorporationInventors: Krishnan Sreenivas, Koen Bennebroek, Sanford S. Lum, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
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Patent number: 8081826Abstract: Change image detecting devices and methods are disclosed. In one example, a change image detecting device includes a change image detecting unit that selects a reference image and an image to be processed and a determination unit that compares an Na-th (‘Na’ is a natural number equal to or smaller than N) partial region of N (‘N’ is an integer equal to or larger than 2) partial regions. If the determination unit determines that there is a change, the change image detecting unit selects the image to be processed or an image, which is temporally later than the image to be processed, as a new reference image and detects the image to be processed or the image, which is temporally later than the image to be processed, as the change image.Type: GrantFiled: January 31, 2008Date of Patent: December 20, 2011Assignee: Seiko Epson CorporationInventor: Issei Yokoyama
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Patent number: 8035649Abstract: There is provided a screen update method and system including: a first step of identifying image resource data associated with a first image update event from a predetermined basic recording space in case that the first image update event occurs; a second step of loading the identified image resource data in a buffer space including a plurality of buffers, in which the image resource data are loaded in rotation on the buffer by a frame, respectively; a third step of sequentially determining the image resource data loaded on the buffer for each the buffer, rendering the determined image resource data, and generating a first image at a first frame rate; a fourth step of generating a second image associated with a second image update event at a second frame rate in case that the second image update event occurs; a fifth step of compositing the first image with the second image to generate an entire image; and a sixth step of displaying the entire image on a predetermined display means.Type: GrantFiled: June 28, 2005Date of Patent: October 11, 2011Assignee: NHN CorporationInventor: Dae Il Kim
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Patent number: 7999819Abstract: Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.Type: GrantFiled: November 20, 2007Date of Patent: August 16, 2011Assignee: Via Technologies, Inc.Inventors: Fred Liao, Yijung Su, Yiping Chen, Mark Zheng
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Patent number: 7978198Abstract: An image data transfer method including the steps of: (a) reading pixel data of a two-dimensional image stored in a first image storage and having a plurality of pixels, the position of each of the pixels being represented by coordinates of first and second directions, the pixel data being read by scanning data transfer units of the pixel data in the second direction where each of the data transfer units is formed by data of a predetermined number of pixels consecutive in the first direction; (b) writing the data transfer units read at step (a) in a temporary data storage where data is stored at a position designated by a combination of first and second addresses, the data transfer units being written in burst mode in a region of the temporary data storage in which the first addresses are consecutive while the second address is fixed; and (c) reading the data transfer units written in the temporary data storage from the region in which the first addresses are consecutive while the second address is fixed in bType: GrantFiled: April 17, 2007Date of Patent: July 12, 2011Assignee: Panasonic CorporationInventors: Yasuharu Tanaka, Shinji Kitamura, Taichi Nagata, Yoshihisa Shimazu
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Patent number: 7944451Abstract: A method comprises storing pixel data in a frame buffer, retrieving the pixel data from the frame buffer and processing at least one pixel value of the pixel data to generate an output pixel bit stream. The method further comprises storing pixel values in a first update buffer. The pixel values are derived from the output pixel bit stream. The method also comprises providing the pixel values from the first update buffer across a network to a remote graphics system.Type: GrantFiled: July 31, 2007Date of Patent: May 17, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Roland M. Hochmuth, Robert P. Martin, Andrew D. Thomas
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Publication number: 20110109639Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Inventors: Krishnan Sreenivas, Koen Bennebroek, Sanford S. Lum, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
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Patent number: 7911474Abstract: A memory manager interfaces between a rendering application and the driver controlling one or more memories. A multi-level brick cache system caches bricks in a memory hierarchy to accelerate the rendering. One example memory hierarchy may include system memory, AGP memory, and graphics memory. The memory manager allows control of brick overwriting based on current or past rendering. Since different memories are typically available, one or more memory managers may control storage of bricks into different memories to optimize rendering. Management of different memory levels, overwriting based on current or previous rendering, and an interfacing memory manager may each be used alone or in any possible combination.Type: GrantFiled: February 28, 2007Date of Patent: March 22, 2011Assignee: Siemens Medical Solutions USA, Inc.Inventors: Wei Li, Gianluca Paladini
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Patent number: 7880742Abstract: An information processing device in which a data bus for establishing interconnection between a plurality of control operating units formed in a main processor is connected at one end to a graphic processor and at the other end to a main memory. Image frame data generated by the graphic processor is sequentially transferred through the data bus and stored into the main memory. The data bus satisfies R1?R2?R4 and R1?R3?R4, where R1 is the data transmission rate from the main processor to the graphic processor, R2 is the data transmission rate from the graphic processor to the main processor, R3 is the data transmission rate between the main processor and the main memory, and R4 is the rate to transmit a single image frame of data within a vertical blanking interval.Type: GrantFiled: January 9, 2006Date of Patent: February 1, 2011Assignee: Sony Computer Entertainment Inc.Inventor: Katsu Saito
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Patent number: 7876327Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.Type: GrantFiled: December 21, 2006Date of Patent: January 25, 2011Assignee: NVIDIA CorporationInventors: Krishnan Sreenivas, Koen Bennebroek, Sanford S. Lum, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
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Patent number: 7868897Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.Type: GrantFiled: June 30, 2006Date of Patent: January 11, 2011Assignee: Intel CorporationInventors: Balaji Vembu, Aditya Navale, Wishwesh A. Gandhi
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High resolution display of large electronically stored or communicated images with real time roaming
Patent number: 7840908Abstract: A video display system, which enables users to navigate (by panning and zooming) throughout very large digital images. The digital images are stored on a disk drive in a proprietary file format (which is optimized for speed) and then viewed via a VGA connection. The system enables a user's ability to navigate throughout the entire image seamlessly. Instead of requiring a large amount of memory to display these images, the images are essentially transferred directly from the disk drive to video memory.Type: GrantFiled: September 13, 2002Date of Patent: November 23, 2010Assignee: Pixia Corp.Inventors: Rudolf O. Ernst, Pun Sing Lui -
Patent number: 7817156Abstract: A hook processing module 400 hooks and preempts a specific drawing command issued by an application program 122, and draws an image in an image data storage area 106b within the RAM 106 according to the acquired drawing command. VNC server 130 acquires the image from the image data storage area 106b, and transfers the acquired image to a projector via a network.Type: GrantFiled: May 25, 2005Date of Patent: October 19, 2010Assignee: Seiko Epson CorporationInventor: Hiroyuki Ichieda
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Patent number: 7817157Abstract: A remote management controller may include a capture engine and a processor. The capture engine may be configured to obtain a slice of video data output from a video graphics controller, store the slice of video data, and calculate at least one value correlative to the slice of video data. The processor may be configured to retrieve the slice of video data stored by the capture engine and process any changed portion of the slice of video data for transmission to a remote system.Type: GrantFiled: August 23, 2005Date of Patent: October 19, 2010Assignee: Hewlett-Packard Company, L.P.Inventors: Theodore F. Emerson, Robert L. Noonan, David F. Heinrich, Don Dykes
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Patent number: 7809904Abstract: Circuits, methods, and apparatus that pre-load data that may be needed by a graphics processor to render upcoming scenes. One example determines one or more possible upcoming scenes or views. To save computing resources, the possible upcoming scenes are not fully rendered, but the addresses, and corresponding pages, of data that would be needed to render the scenes are determined. Page usage information is also gathered. Pages that would be needed to render the upcoming scenes, but which are not resident in memory, are read in from a disk drive and stored in memory before they are needed. Pages that are infrequently used are removed from physical memory. In this way, when the scene changes, a large number of page faults do not occur in one frame, rather, they are distributed among several frames.Type: GrantFiled: December 15, 2006Date of Patent: October 5, 2010Assignee: NVIDIA CorporationInventor: Nicholas P. Wilt
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Patent number: 7800635Abstract: A method for displaying an image in a wireless terminal including at least two screen modes is provided, in which a display buffer existing in one Device Context (DC) is formed, capable of recording a corresponding image to be displayed according to screen sizes in the at least two screen modes, and recording the corresponding image to be displayed according to a screen size of a corresponding screen mode in the at least two screen modes through the display buffer existing in the DC, and outputting the corresponding image to a screen in the corresponding screen mode.Type: GrantFiled: May 26, 2006Date of Patent: September 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-Hyoun Kim
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Patent number: 7800625Abstract: A method of automatically adjusting parameters of a display device is provided. The method includes: measuring a current distance between a user and the display device; determining a particular distance range which the current distance falls in; determining corresponding parameter values of the particular distance range according to a parameter management table which lists a series of distance ranges and corresponding parameter values of the display device; transmitting the parameter values to the display device; adjusting parameters of the display device according to the parameter values.Type: GrantFiled: July 24, 2007Date of Patent: September 21, 2010Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Fang-Hua Liu, Shih-Fang Wong
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Patent number: 7800622Abstract: A method and apparatus for selective control of display data sequencing in a mobile computing device is disclosed. The method may include storing a plurality of display data sequencing instruction sets in a memory of the mobile computing device, each of the display data sequencing instruction sets being usable for transferring data in accordance with a different sequencing of display data than other ones of the display data sequencing instruction sets, receiving an indication of a particular type of display data sequencing to be used, selecting one of the display data sequencing instruction sets based on the received indication of the particular type of display data sequencing to be used, transferring data for display based on the selected one of the display data sequencing instruction sets, and controlling the transfer of data to the display device in order to synchronize the data transfer with the data and timing requirements of the display device.Type: GrantFiled: March 21, 2007Date of Patent: September 21, 2010Assignee: Motorola, Inc.Inventors: Jon Schindler, Irfan Nasir
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Patent number: 7791609Abstract: An apparatus and a method providing an automatic display control in a multimedia system. The apparatus includes a memory that stores predetermined display information; a controller that includes a communication module to perform data communication with an external device, set to be in a master mode to write the display information to the memory in an initialize mode and set to be in a slave mode to analyze display control data for a predetermined automatic display control function which is transmitted by the external device, in other modes, and generates a display control signal used to perform a function that corresponds to the result of analyzing the display control data; and a video signal processor that receives video signals from the external device, converts the format of the video signals to another format suitable for the display characteristics of a display means, and processes the converted video signals according to the control signal.Type: GrantFiled: July 23, 2004Date of Patent: September 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Yong-jai Lee
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Patent number: 7782330Abstract: In response to a requirement of transferring a file from a personal computer PC to a projector 10 that is output by dragging and dropping a corresponding file icon onto a projector icon, a CPU 50 requires setting of a password. The CPU 50 maps the preset password to a file and transfers the file with the password to an external storage device of the projector 10. The projector 10 requires input of a password, which is expected to be assigned to the file, and allows reproduction of the file when the input password is coincident with the preset password.Type: GrantFiled: February 5, 2008Date of Patent: August 24, 2010Assignee: Seiko Epson CorporationInventors: Shoichi Akaiwa, Tomohiro Nomizo
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Patent number: 7768522Abstract: Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.Type: GrantFiled: April 22, 2005Date of Patent: August 3, 2010Assignee: Apple Inc.Inventors: John Stauffer, Bob Beretta