Abstract: A method including accessing an electronic document from a source of electronic documents; determining if the electronic document is redaction protected; and when the electronic document is redaction protected, allowing the electronic document to be opened only if a redaction application is available to allow opening of the electronic document with a redaction.

Abstract: A method and apparatus for displaying digital photos on a digital display with a network connection module. The method includes identifying two different photos in a digital photo collection that include a matching photo content, and displaying the two different photos simultaneously in a split screen on the digital display. The two different photos can be matched from related photo clusters. An integrated camera can be used to automatically determine an identity of a frame viewer to determine photos to display, and can capture gesture-based feedback. The photos can be filtered and cropped at the receiver side.

Abstract: An image forming apparatus includes a controller, a storage, and a display, and upon output of an image for printing based on print data, the controller stores the print data in the storage and selectively outputs an image for printing, and if the print data includes identification information for identifying the image for printing, the controller outputs the identification information together with the image for printing. In the image forming apparatus, when an image for printing based on print data selected by a user is displayed on the display, the controller restricts an output process so that the image for printing is displayed only if the identification information is not included in the print data.

Abstract: A redaction system including a system for receiving an electronic version of a first document; a system for generating an electronic version of a second document which is a redacted version of the first document, wherein the system for generating includes a computer having a redaction engine coupled to a source of redaction rules; and a system for transmitting the second document from the redaction system.

Abstract: A method including scanning a document by a scanner to form a scanned document; determining a form of the document; and redacting a cell of the scanned document based upon the determined form of the document to thereby form a scanned redacted document.

Abstract: Disclosed herein is a redaction system, method and computer program product. Embodiments of the invention implement an automated redaction system for redacting electronic documents. A redaction system of the invention has a source of electronic documents to be redacted; a source of redaction rules; and a redaction engine coupled to the source of electronic documents and the source of redaction rules. The redaction system is configured to perform operations of the method of the invention by accessing electronic documents to be redacted; accessing redaction rules to be applied when redacting the electronic documents; and redacting the electronic documents in accordance with the redaction rules. In other embodiments of the invention, the electronic documents to be redacted are converted to a common electronic format prior to redaction, and redacted when in the common electronic format.

Abstract: A method of operating a data processing system is disclosed for a data processing system that comprises a display and a display controller. The method comprises the display controller providing to the display data for an output surface to be displayed, storing the data in a memory of the display, and the display reading the data from the memory and displaying the output surface. The method further comprises the display controller indicating to the display a particular memory address of the memory, and the display using the indication to control the reading of data from the memory. The display controller may provide to the display image data for one or more sub-regions of the output surface that were not present in a previous version of the output surface.

Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.

Abstract: Systems, devices and methods operative for identifying a reference within a figure and an identifier in a text associated with the figure, the reference referring to an element depicted in the figure, the reference corresponding to the identifier, the identifier identifying the element in the text, placing the identifier on the figure at a distance from the reference, the identifier visually associated with the reference upon the placing, the placing of the identifier on the figure is irrespective of the distance between the identifier and the reference.

Abstract: Systems, devices and methods operative for identifying a reference within a figure and an identifier in a text associated with the figure, the reference referring to an element depicted in the figure, the reference corresponding to the identifier, the identifier identifying the element in the text, placing the identifier on the figure at a distance from the reference, the identifier visually associated with the reference upon the placing, the placing of the identifier on the figure is irrespective of the distance between the identifier and the reference.

Abstract: Techniques related to video coding with low bitrates are discussed. Such techniques may include skipping coding of a picture of a group of pictures when an estimated coding bit cost of the picture is greater than an available coding bit limit for the picture and, when the estimated coding bit cost is not greater than the available coding bit limit, determining the coding skip indicator based on a picture type of the individual picture and a picture structure of the group of pictures.

Abstract: An apparatus for processing visual information includes a controller to control display of information in an application window based on first visual information stored in a buffer and second visual information received from one or more sources. The controller outputs the first visual information for display in a first area of the application window and outputs the second visual information for simultaneous display in a second area of the application window. The first visual information is visual information that does not change between a first time and a second time, and the second visual information is visual information that changes between the first time and the second time. The controller may be different from a central processing unit of a host device.

Abstract: Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

Abstract: A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be executed before the first thread's execution. Thread execution may be freely reordered, subject only to the rule that a second thread, whose execution is dependent on execution of a first thread, can only be executed after the first thread.

Abstract: For certain medical images, it is important and/or required that a user view all of a medical image at full resolution so that minute, but important, indicia in the medical image are not missed. A computing systems monitor the portions of the medical image that are displayed on the display device, notates those portions that have been displayed at full resolution (or other user-defined display parameters), and provides the user with information indicating portions that have not been viewed at full resolution and/or provides information indicating for which images of a multiple image examination full pixel display has been accomplished. The process reduces the possibility of missing an abnormality in a medical image due to the viewer not viewing a portion of the image at full resolution or using other user-defined display parameters.

Abstract: Concurrent display of graphic content on multiple displays is described. A frame of graphic content to be displayed on multiple displays can be written to a single memory location. Previously written graphic content can be read to multiple displays having misaligned synchronization signals and new graphic content can be written to a different memory location concurrently.

Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Abstract: To make it possible to display an application that is suitable for specific circumstances of a specific user, from among a large number of applications, without complicating a rule file and without increasing its capacity. An application execution terminal acquires context information from received sensor information, acquires an arrangement display rule file that matches the acquired context information from among arrangement display rule files in which a category indicating a type of an application and a display position of the application are defined, analyzes a category defined by the acquired arrangement display rule file, acquires a list of applications that match the category, links the applications indicated by the list of the applications to the acquired arrangement display rule file, and arranges and displays the applications in accordance with a description of the arrangement display rule file.

Abstract: A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.

Abstract: A flag memory is provided which stores a flag indicating whether or not a corresponding pixel is in the initial state. When writing has been performed on an image memory by a drawing unit, a value of the flag of a corresponding pixel is changed from a first value indicating that the pixel is in the initial state to a second value indicating that the pixel is not in the initial state. When a display unit reads a pixel value from the image memory, a flag corresponding to the pixel is read from the flag memory, and if the flag still has the first value, an initial pixel value is supplied to the display unit, and otherwise, a pixel value read from the image memory is supplied to the display unit.

Abstract: An interfacing circuit comprising a First In First Out (FIFO) memory for exchanging data between a “data producer device” and a “data consumer device”. The FIFO memory is controlled by first write control signals (WR, CLK_WR) and second read control signals (ENABLE, Clk_Rd). The interfacing circuit further includes: a redundancy filter (230) for receiving a sequence of N data (Y0, Y1, Y2 . . . Yn?1 ) to be stored within said FIFO, and for generating a redundancy control word representative of the presence of consecutive identical data within said sequence; means (250) for controlling said first and said second control signals of said FIFO for the purpose of preventing the storage into said FIFO of multiple consecutive identical data and more important to make possible to accelerate the average speed of the data flux going to the “data consumer device” without need to accelerate the clocking of the memory feeding the said FIFO thanks to increase of efficiency of transfers due to redundancy filtering.

Abstract: To realize effective load distribution and improve the performance in image formation processing, an image processing apparatus includes a first image processing unit configured to perform image processing on a drawing area, a second image processing unit configured to be differentiated from the first image processing unit, a load analysis unit configured to analyze a composition processing load of an object in the drawing area, a rotational angle analysis unit configured to analyze a rotational angle of the object in the drawing area, and a load distribution determination unit configured to determine whether to distribute a part of image formation processing to be applied on the drawing area from the first image processing unit to the second image processing unit based on the analyzed composition processing load of the object and the analyzed rotational angle of the object.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: A device includes a memory storing a persistence bit for each of a plurality of pixels of a display device, the persistence bit having a first value when a corresponding pixel should be illuminated for displaying a persistent image, and having a second value when the corresponding pixel should not be illuminated for the persistent image; a pseudorandom pixel value generator which during each video frame receives a seed value and generates pseudorandom pixel values for the plurality of pixels, each pseudorandom pixel value being not greater than a specified variable persistence value; a frame value generator outputting a frame value for each video frame; and a match detector which, during each video frame, compares the frame value to the pseudorandom pixel values for the plurality of pixels, and for each pixel where the comparison indicates a match, makes the persistence bit for the corresponding pixel have the second value.

Abstract: A method and apparatus for processing data in a system comprising a central processing unit (CPU), a system memory, and a graphics processing unit (GPU) includes determining whether the GPU is an integrated graphics processor (IGP). Based upon a determination that the GPU is an IGP, data stored in the system memory is accessed by the GPU without copying the data to a memory on the GPU. Processing is performed on the data in the GPU.

Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.

Abstract: There is provided an information processing apparatus including a storage unit for storing a transition frequency database storing transition frequency information representing a frequency of a state transition of a display content displayed on a display screen from a display state displaying the display content to another display state, and a cache control unit for predicting the another display state to which a transition may occur based on the transition frequency database and the display content displayed on the display screen, and preparing a resource needed by the another predicted display state before the transition occurs.

Abstract: Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.

Abstract: The present invention provides a method for sharing a graphics card among multiple Operation Systems (OSs) and a computer system. The method comprises: detecting a first GOS to be displayed, the first GOS being one of at least two GOSs; calling a correspondence table to determine a first display control register bank corresponding to the first GOS, the first display control register bank including display mode parameters therein; controlling the first display control register bank to connect to a display output port; and displaying the first GOS based on the display mode parameters. According to the inventive method and computer system, it is possible to achieve sharing of the graphics card among the multiple OSs and quick display of the GOS to be displayed, without simulating registers of the graphics card.

Abstract: A system, method, and computer program product are provided for optimizing use of a vertex cache. In use, information is identified, where such information is associated with vertex data stored in a vertex cache. To this end, use of the vertex cache may be optimized utilizing the information. In one embodiment, the information may include new information derived from the vertex data, and optionally index data, prior to processing of the vertex data. Further, the vertex cache may optionally utilize the information to optimize performance of the vertex cache by minimizing a number of cache misses.

Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.

Abstract: An image processing apparatus for managing a memory device having a plurality of storage areas including a storage area storing out-of-use information and a free area storing no information, the image processing apparatus comprises memory control unit adapted to determine whether or not there is a storage area storing the out-of-use information based on a request for storing information and determining the storage area storing the out-of-use information as an area for storing the information, in a case where the storage area exists; and information writing unit adapted to overwrite generated information to the storage area determined by the memory control unit.

Abstract: A display device changes the gradation of pixels by a write operation of applying a voltage to the pixels a plurality of times. When newly changing the display state of pixels, the display device judges as to whether or not the pixels whose display state are to be changed are in a write operation. The display device starts the writing operation for those of the pixels that are not in a writing operation, and starts a new writing operation for those of the pixels that are in a writing operation, after the ongoing writing operation is completed. If a writing operation for pixels in progress of being updated and pixels with which a writing operation is to be newly started would lead to substantially large power consumption, the start of the writing operation for the pixels with which a writing operation is to be newly started is postponed.

Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.

Abstract: An image processing apparatus and graphics memory unit which reduces useless memory access to a graphics memory unit. When an image data read section reads image data from frame buffers or windows, a mask area inside/outside determination section determines by reference to mask information stored in a mask information storage section whether image data which is being scanned is in a memory access mask area. If the image data which is being scanned is in the memory access mask area, then a superposition process section performs a superposition process according to a transmission attribute assigned to the memory access mask area regardless of transmission attributes assigned to the frame buffers or the windows.

Abstract: A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.

Abstract: The invention relates to a device and a method for detecting broken glass in a continuous furnace provided for sterilizing or depyrogenating glass containers, comprising a transport device for the glass containers, wherein the detection device comprises at least one transmission and receiving unit. The receiving unit is designed to detect electromagnetic radiation that can be emitted by the transmission unit. The transport device and the transmission unit and receiving unit are positioned and aligned in relation to each other such that the glass particles or pieces of broken glass resulting from glass breakage cross the radiation path between transmission and receiving unit during or after leaving a substantially horizontal transport plane predetermined by the transport device.

Abstract: A display device that comprises a flag memory containing state flags of pixel areas of the image is provided. The display device comprises a display screen and a graphical generation unit implementing at least three functions for displaying an image, i.e. a first data erasure function, a second function for generating an image comprised of pixels in a first memory, and a third function for displaying the image by reading the pixels in said memory and controlling the screen, in which an image is divided into a plurality of separate pixel areas and in that each area is addressed by a flag, wherein the display device further includes a memory that stores the flag states so that the graphical generation unit can execute the display function on the basis of the flag states. The generation of images having a predominantly uniform background can, in particular, be used for application in aeronautics.

Abstract: Provided is a display data channel (DDC) communication module reading and storing extended display identification data (EDID) of a display device and providing the stored EDID to a host device. The DDC communication module includes: a serial electrically erasable and programmable read only memory (EEPFROM) in which the EDID is stored; a comparator outputting logic data indicating that the comparator is connected to the display device or the host device; and a controller reading and storing EDID, or providing EDID stored in the serial EEPROM to the host device, according to the logic data output from the comparator.

Abstract: A distance information generating unit 4 for rasterizing minute line segments divided by a curved line dividing unit 2 through a combination of straight line cells and corner cells to generate distance information corresponding to a pixel 12 of a display and an edge rasterizing unit 7 for rasterizing edge information about the minute line segments divided by the curved line dividing unit 2 are disposed, and a mapping unit 10 determines whether the pixel 12 is located inside or outside by using the edge information rasterized by the edge rasterizing unit 7, and maps the distance information generated by the distance information generating unit 4 onto the antialiasing intensity 11 of a component 13 included in the pixel 12 according to the results of the inside or outside determination.

Abstract: A display apparatus includes a storage unit which stores a display identification data and a comparative check data obtained from the display identification data by a preset data processing method; and a controller which calculates an inspective check data from the display identification data stored in the storage unit via the data processing method, compares the inspective check data with the comparative check data, and performs an identification data checking process to determine whether there is an error in the display identification data.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: An image display system includes: a frame buffer having a plurality of lines, each of which stores image data and repetition information of the image data; a memory controller in signal communication with the frame buffer for reading the image data and the repetition information from the frame buffer; a display controller in signal communication with the memory controller for regenerating the image data, which is provided from the memory controller, in accordance with the repetition information provided from the memory controller; and a display device in signal communication with the display controller for displaying the regenerated image data, which is provided from the display controller, under regulation by the display controller.

Abstract: Systems and methods for determining a compression tag state prior to memory client arbitration may reduce the latency for memory accesses. A compression tag is associated with each portion of a surface stored in memory and indicates whether or not the data stored in each portion is compressed or not. A client uses the compression tags to construct memory access requests and the size of each request is based on whether or not the portion of the surface to be accessed is compressed or not. When multiple clients access the same surface the compression tag reads are interlocked with the pending memory access requests to ensure that the compression tags provided to each client are accurate. This mechanism allows for memory bandwidth optimizations including reordering memory access requests for efficient access.

Abstract: Determining a schedule of instructions for an integrated circuit graphics pipeline. The method includes accessing a state of a host system. The state comprises operations to be performed on fragments to be processed by the graphics pipeline. The method further includes determining a vector based on the state and indexing a table based on the vector to obtain a predetermined listing and ordering of macro-operations to be executed. The method still further includes determining instructions for programming the graphics pipeline based the executing of the macro-operations in the scheduled order.

Abstract: When a processor, which transits from a first mode that causes a guest operating system to operate to a second mode that causes a virtual machine monitor managing the guest operating system to operate, when previously set transition condition is satisfied, transits to the second mode, a determining unit determines a cause or the transition. When it is determined that an execution of a process related to a completion of writing the image information in an image storage unit on the guest operating system is the cause, a detecting unit detects an updated portion representing an unmatched portion of the image information between before and after writing.

Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.

Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.

Abstract: A video display device including an integrated atypical/typical defect compensation circuit is disclosed. The video display device includes a display panel, a memory storing atypical/typical defect information used to compensate atypical/typical defect regions of the display panel, and an integrated atypical/typical compensation circuit including a first compensator for compensating input data to be displayed on the atypical/typical defect regions, using the atypical/typical defect information from the memory, and a second compensator for finely compensating the data compensated by the first compensator, using first and second dithering patterns. The compensation circuit supplies data to be displayed on normal regions, without compensation.

Abstract: A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each portion of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.