Abstract: A method and apparatus for accessing a cache memory of a computer graphics system, the apparatus including a frame buffer memory having a graphics memory for storing pixel data for ultimate supply to a video display device, a read cache memory for storing data received from the graphics memory, and a write cache memory for storing data received externally of the frame buffer and data that is to be written into the graphics memory. Also included is a frame buffer controller for controlling access to the graphics memory and read and write cache memories. The frame buffer controller includes a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memories.

Abstract: A dual-cache pixel processing circuit that allows one cache to be flushed while the other receives subsequent pixel fragments is presented. The system includes a first fragment cache and a first set of state registers where the first set of state registers stores state variables for drawing operations corresponding to fragments stored in the first fragment cache. The system also includes a second fragment cache and a second set of state registers where the second set of state registers stores state variables for drawing operations corresponding to fragments stored in the second fragment cache. The system further includes a render backend block that is operably coupled to the first and second fragment caches and to a frame buffer that stores current pixel information for a plurality of pixels in a display frame.

Abstract: A memory architecture for a video graphics controller includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and a bus. The DRAM includes a data port, an address decoder that can receive an address to select a memory location in the DRAM and a command instruction bus that can receive instructions for data transfer. The SRAM includes a first data port to transfer data with the DRAM, a second data port to transfer data with other than the DRAM, a first address decoder that can receive an address to select a memory location in the SRAM for data transfer with the DRAM, a first read/write input that can receive a signal for data transfer with the DRAM, a second address decoder that can receive an address to select a memory location in a page of the SRAM to transfer data with other than the DRAM and a second read/write input that can receive a signal for data transfer from other than the DRAM.

Abstract: A method for rendering a three-dimensional terrain, the method including providing at least one previous display pixel having a previous ray from a point of view through the at least one previous display pixel to a previous terrain unit intersecting an axis of the previous ray, the previous ray having a length, and computing a subsequent ray from the point of view through a subsequent display pixel, whereby the subsequent ray has a length equal to the length of the previous ray.

Abstract: Methods and apparatus for constructing objects within a cache system thereby allowing the cache system to respond to requested objects that are not initially available within the cache system. One embodiment of the invention caches image files, where the images are divided into components and stored in a format that allows identification and access to the components. The cache system determines that an object, such as an image file, is missing from the cache memory, locates sufficient components from the cache memory and/or external storage, and constructs the object from the located components.

Abstract: A method, apparatus, and computer implemented instructions for managing a set of memory resources used to store texture objects in a data processing system. A texture manager allocates memory to a current texture object in a set of memory resources. A stored texture object, handled by the texture manager, is selectively removed in response to an inability to allocate sufficient memory to the current texture object. The allocating and selectively removing steps are repeated until the current texture object is allocated sufficient memory. The repeating step is halted in response to an absence of any stored texture objects, handled by a texture manager, being present in the first memory resource. Stored texture objects, handled by another texture manager, are selectively removed in response to an inability to allocate sufficient memory to the current texture object. Memory is allocated in the set of memory resources to the current texture object in response to selectively removing stored texture objects.

Abstract: A cache memory for high latency and out-of-order return of texture data. The present invention includes a texture cache memory that prefetches texture data before it is needed. Further, the texture cache memory counts the number of times a cache line is requested and a number of times the cache line is read, and determines whether the cache line is free by keeping track of the different between the two numbers. The texture cache memory of the present invention is capable of working efficiently in computer systems where there is a long latency from the time the texture data is requested and the time the texture data is available for use. In addition, the present invention is capable of handling texture data which enters into the texture cache memory in a different order from which it was requested. The present invention significantly improves performance of the texture data retrieval subsystem within network based or memory hierarchy based computer systems.

Abstract: Apparatus and methods for storing and retrieving images for transmission to an output device are disclosed. A cache comprising one or more bitmaps is examined to determine whether the image to be transmitted generates a match with a bitmap already stored on the cache. If a match is found, the bitmap matching the image to be transmitted is retrieved from the cache. If no match is found, a bitmap representing the image is stored in the cache.

Abstract: A method of indexing a high-dimensional vector space, along with a method of quickly retrieving a feature vector having features similar to a query vector from the vector space indexed by the indexing method, are provided. The method of indexing a feature vector space includes the steps of (a) partitioning the feature vector space into a plurality of approximation regions; (b) selecting an arbitrary approximation region to determine whether the selected approximation region is heavily or sparsely distributed; and (c) if the approximation region is determined to be sparsely distributed, indexing the corresponding approximation region as one special node belonging to a child node of the tree data structure, together with any other sparsely distributed approximation region spaced apart by a distance less than a predetermined distance.

Abstract: A method and apparatus for managing compressed Z information in a video graphics system that supports anti-aliasing is described. Each pixel in the display frame is represented with a primary Z value, a secondary Z value, a first and second color, and a pixel mask that indicates how the Z values and colors apply to the samples of the pixel. The primary Z values for the pixels in a pixel block are then compressed using a compression algorithm and stored in a Z buffer in a compressed format. A secondary mask that indicates which pixels in the pixel block have valid secondary Z values is also stored in the Z buffer, along with the secondary Z values and the pixel masks in an uncompressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates the level of compression of the Z information the corresponding pixel block.

Abstract: A system and method using inductive image generation with cached, state-specific image tiles for editing digital images. A computer system contains an archival digital image to be edited and viewed, a transformation state list, describing editing operations to be applied to the archival image in order to produce the current edited image rendition, and a viewing data set, describing the resolution, offset and extent of the current view of the current edited image rendition. The current view is constructed from a set of image tiles kept in a tile cache. In response to an instruction to generate the current view, the system identifies the requisite tiles, and then generates each tile by an inductive image generation process.

Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory.

Abstract: The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.

Abstract: The invention provides for cache organization of texture information and a method and apparatus for accessing cached texture information and an index for cached information. Texels are represented in two dimensions and stored in groups referred to as tiles. Cache is configured to contain multiple tiles of texture image data, each tile being stored as a line in the cache. A cache line can be multidimensional (e.g., two or three or more dimensions) and may be viewed as an identifiable storage element in the cache. Memory may consist of a plurality of cache lines. Direct mapped cache may be utilized wherein each DRAM location maps to a single cache line. A tag table contains the tag information for all tiles currently stored in cache. A portion of the texel information may be utilized as an index assigned to a specific cache line. Another portion of the tag information identifies the tile currently stored in cache.

Abstract: Color caching method used in color matching processing has advantages and disadvantages, and the processing efficiency depends upon an image to be processed. In view of this, color matching calculation and caching for uniquely determining an output color corresponding to an input color are employed to calculate a hit rate per unit block at a checkpoint block when performing color matching processing in block unit having a predetermined pixel size. Based on the calculated hit rate, a caching method to be applied to a block subsequent to the checkpoint block is determined.

Abstract: The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.

Abstract: A multi-function controller in a computer graphics system performs the functions of a graphics processor, a video processor, a system memory controller, a cache controller, and a PCI bridge. The multi-function controller is connected to the host bus of the computer graphics display system to maximize performance. A graphics frame buffer and a system memory are combined into a unified system memory, which is controlled by and coupled to the multi-function controller.

Abstract: An image processing system is described in which a data buffer memory 4 is provided between an image processor 2 and an image frame memory 8. The data buffer memory 4 stores a sub-set of the raster lines stored within the image frame memory 8. This data can be read in either an intra-raster-line mode from adjacent memory cells within a bank or in an inter-raster-line mode from memory cell locations at corresponding positions within different banks. The data may be 8-bit pixel data or 16-bit pixel data. In the case of 8-bit pixel data a single bank contains a full raster line whereas in the case of 16-bit pixel data a single raster line extends over two banks.