Abstract: A drawing control method, a drawing control apparatus, and a drawing control system for embedded system are provided. The present invention adopts an independent drawing control apparatus to control a drawing unit to draw a frame, and move the drawn frame to an external frame buffer in advance, and therefore the number of lines that can be drawn is not restricted by the capacity of the memory of the drawing unit. Further, the present invention employs a counter to accumulate a counting number upon each time completion of drawing frame or moving frame. Whenever the counting number is accumulated, the drawing unit is controlled to perform a next stage of frame drawing or frame moving. In this concern, the present invention eliminates the time for external accessing, and thus achieving parallel processing, and instant displaying.

Abstract: Disclosed herein is a display device in which input data is written to a RAM as current frame data and read from the RAM as preceding frame data. Then, the current frame data and the preceding frame data are added up in a correction circuit and the result is subjected to an overdriving processing. After this, the processed (over-driven) data is assumed as current frame corrected data, which is then written to the RAM. The written corrected data is read from the RAM and subjected to a double-speed driving processing.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: An image generation apparatus provides interpolation and distortion correction. The interpolation and distortion correction may be provided in one or two dimensions. Nonlinear image scan trajectories, such as sinusoidal and bi-sinusoidal trajectories are accommodated. Horizontal and vertical scan positions are determined using a linear pixel clock, and displayed pixel intensities are determined using interpolation techniques.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: A method for synchronization of data over multiple panels is provided. A communications apparatus that synchronizes data across multiple displays is provided. A computer program product, comprising a computer-readable medium that synchronizes video data across multiple displays is provided. At least one processor configured to synchronize data across multiple panels is provided. The video data can be sent between the multiple panels or displays at different rates to facilitate synchronization of the data. Double buffering at each panel can allow data to be written to a first buffer and at substantially the same time data is extracted from a second buffer and written to a display.

Abstract: A source driver comprising a frame memory, a first line buffer, and a second line buffer. The frame memory stores bits of pixel values of an image. The first line buffer then sequentially latches the bits of the pixel values from the frame memory with a first address index. The second line buffer then sequentially latch the bits of the pixel values from the first line buffer with a second address index, which is different from the first address index, and writes the bits of the pixel values back to the frame memory, such that the image is scrolled. The present invention also provides a method of refreshing the frame memory in a source driver.

Abstract: A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: In a video processor unit, a method of providing a video data stream at a clock rate that is independent of a pixel clock rate. Receiving native video data from a video source at a native clock rate, storing the video data in a memory unit, reading selected portions of the video data at a memory clock rate, rasterizing the selected video data, packetizing the rasterized video data, sending the packetized video data to a display unit by way of a link at a link rate, wherein the link rate is directly related to the memory clock rate.

Abstract: An apparatus and method of processing image data sub-samples image data by generating a data patch by dividing the image data into a plurality of blocks and sequentially accessing pixel data values in each of the blocks through a plurality of line memories. The image data is divided into the plurality of blocks, the blocks are stored in each of the line memories, and the pixel data values stored in each of the line memories are sequentially accessed, so as to generate the data patch for sub-sampling the image data.

Abstract: An image display device includes a timing controller capable of overdriving. The timing controller has three line buffers, an image reverse processing unit, and an overdrive unit. The first line buffer buffers first line data of a second frame, wherein the second frame is generated later than a first frame. The second line buffer buffers first compressed data. The image reverse processing unit estimates first and second line data of the first frame according to the first compressed data. According to the first and second line data of the first and second frames, the overdrive unit outputs first and second lines of interleaving data for an interleaving frame. The interleaving frame is inserted between the first and second frames. With the third line buffer, the timing controller outputs the first and second lines of interleaving data at different time point.

Abstract: A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.

Abstract: A graphics processor for processing graphics data originating in a host device into rendered graphics data employable in a remote display device. The graphics processor includes a video processor with a reduced instruction-set computer coupled to a configuration register for producing rendered graphics data from the graphics data in a memory storage structure. A first line buffer affords the video processor read-only access to the graphics data in the memory storage structure, and a second line buffer affords the video processor write access to the memory storage structure for rendered graphics data. A method of processing graphics data includes the steps of moving graphics data from the host device into a memory storage structure, transferring the graphics data from the memory storage structure to the video processor, processing the graphics data in the video processor, and writing the rendered graphics data into the memory storage structure.

Abstract: An object is to provide an image processing circuit adaptable to displays having a variety of pixel numbers. The image processing circuit includes a data adjustment circuit, a first line memory and a second line memory capable of storing K pieces of data, an output timing control circuit, and an arithmetic circuit. To the data adjustment circuit, (X×Y) pieces of pixel data are input. Y pieces of pixel data are transmitted to the first line memory. When Y is less than K, (K?Y) pieces of dummy data are added to fill the first line memory. Then, the K pieces of data are output from the first line memory to the second line memory and a new set of K data is input to the first line memory. The arithmetic circuit stores the data input from the line memories and performs filtering.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: An image scaling circuit and a method for scaling an image into images with different ratios are provided. The image scaling circuit includes a line buffer memory apparatus, a line buffer control apparatus, a first and a second scaling circuit. The first scaling circuit is coupled to the line buffer memory apparatus, and performs a first image scaling interpolation operation on the data output by the line buffer memory apparatus. The second scaling circuit is coupled to the line buffer memory apparatus, and performs a second image scaling interpolation operation on the data output by the line buffer memory apparatus. The line buffer control apparatus is coupled to the line buffer memory apparatus, the first scaling circuit and the second scaling circuit, for controlling the line buffer memory apparatus to receive or output a scan line data according to the operation status of the first and second scaling circuits.

Abstract: An image processing circuit comprising a plurality of line buffers is provided. Each line buffer stores pixel data of a plurality of pixels as line data, the plurality of pixels configuring a single image line of an image. A first image processing part performs a first image processing task on original image data provided from the exterior by using the line data stored in at least one of the line buffers, and provides processed image data. A second image processing part performs a second image processing task on the processed image data provided from the first image processing part by using the line data stored in at least one of the line buffers, and provides processed image data. A line buffer selector selectively connects the first image processing part and the second image processing part to any number of line buffers. An output path selector selects one of an output path that skips the second image processing task and an output path that performs the second image processing task.

Abstract: A display system comprises line buffer memory that stores input image data in a first color space, and a plurality of gamut mapping modules that accept the input image data from the line buffer memory and performs a gamut mapping operation to produce mapped image data specified in a second color space. The system also includes a subpixel rendering module that renders the image data specified in the second color space for display on a display panel substantially comprised of a particular subpixel repeating group. The system architecture utilizes a plurality of gamut mapping modules which in turn allows for a reduction in the size of line buffer memory needed for the subpixel rendering operation.

Abstract: A display system comprises line buffer memory that stores input image data in a first color space, and a plurality of gamut mapping modules that accept the input image data from the line buffer memory and performs a gamut mapping operation to produce mapped image data specified in a second color space. The system also includes a subpixel rendering module that renders the image data specified in the second color space for display on a display panel substantially comprised of a particular subpixel repeating group. The system architecture utilizes a plurality of gamut mapping modules which in turn allows for a reduction in the size of line buffer memory needed for the subpixel rendering operation.

Abstract: A device and a method for controlling a display make use of a virtual display buffer that acts as an intermediary between data input and display output. The data stored in the virtual display buffer is in a generic, readable first format. A display software driver translates the data stored in the virtual display buffer to a second format usable by a hardware display driver to control a specific display device.

Abstract: When writing data into a single port memory, a plurality of data corresponding to predetermined number of pixels that are packed by a data packing section is written together into the single port memory. When reading data from the single port memory, data corresponding to predetermined number of pixels are read out together from the single port memory. After writing the data corresponding to predetermined number of pixels into the single port memory and before next data corresponding to predetermined number of pixels that are to be written into the single port memory are inputted to the line buffer circuit, data are read from the single port memory. This allows providing a line buffer circuit capable reading and writing data at high speed, without requiring a larger circuit configuration.

Abstract: The disclosure describes image processing techniques useful for devices that support image processing of different sized images. The techniques can be used in many contexts, and may be particularly useful for front-end image processing of small viewfinder images and large still images captured by the device. In one embodiment, this disclosure provides a method comprising capturing a first image with a device, processing the first image using line buffers sized to accommodate an image width of the first image, and capturing a second image with the device, wherein the second image has an image width larger than the image width first image. The method also includes processing the vertical stripes of the second image using the line buffers, wherein the vertical stripes of the second image define widths that fit into the line buffers.

Abstract: An object of the present invention is to provide a memory device and a memory application device which can reduce memories and reduce burden on processings by reading out predetermined bit data stored in plural memory addresses as data output from the memory device. The memory device of the present invention is provided with multiplexers (301, . . . , 3n?1n-2) which can selectively output data in memory cells (000, . . . , n?1m-1n-1) outputted by buffer circuits (200, . . . , 2n?1n-1) one-bit by one-bit from each of memory cell arrays (10 to 1n-1) or n bits from one memory cell array.

Abstract: A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.

Abstract: Systems, methods and apparatus provided for driving the memory of a liquid crystal display device that is capable of reducing the number of frame memories include the steps of storing a current frame data in an input line memory at a first speed; storing the data stored in the input line memory in a frame memory at a second speed faster than the first speed; storing a previous frame data stored in the frame memory in an output line memory at the second speed; and comparing the current frame data with the previous frame data, the previous frame data being outputted from the output line memory at the first speed and selecting a predetermined modulation data in accordance with the result of the comparison.

Abstract: A method for reducing memory consumption when carrying out edge enhancement in a multiple beam pixel apparatus is provided, wherein Static Random Access Memories and first in first out buffers are employed. When the first to the nth input units read the next bit data, the first rows of the bit data in the first to the nth buffers are removed, and each row of bit data behind the first rows is moved towards left by one bit. The first rows of bit data in the (n+1)th to the (n+4)th buffers are stored in one end of the first to the fourth memories respectively, and a bit data is taken out from the other end of each of the memories, to be sequentially stored in the end of the first to the fourth buffers, and the read next bit data is stored in the fifth to the (n+4)th buffers.

Abstract: Provided are a video display control apparatus and a video display control method. A video display control apparatus, including a data storage storing graphic/control integrated data including control information used to display graphic data to be combined with video data and the video data; and a controller combining the video data and the graphic data referring to the graphic/control integrated data and transmitting the combined data to more than one display device. As described above, the transmission capacity of video data, OSD data, and graphic data for a variety of display devices is reduced, thereby lowering the bus proportion. As a whole, the power consumption required by a system is reduced, thereby realizing to be suitable for a mobile device.

Abstract: In forward scanning, a timing control unit outputs the display data in the same sequence as the input display data. In backward scanning, on the other hand, the timing control unit inverts the output sequence of the display data for one line (for one horizontal cycle). Upon input of a scan direction control signal indicating backward scanning, the timing control unit executes sequence change processing by using line memory. The display data in which the sequence of the pixel data is reversed is outputted together with the control signals. It is able to select whether to output data in an inverted sequence or in a normal sequence according to the scan direction control signal.

Abstract: A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a transpose buffer with a crossbar to reorganize incoming data, several memory banks to store the reorganized data over a period of several clock cycles, and a second crossbar for reorganizing the stored data after it is read from the bank of memories in one clock cycle. The method for converting between data in hexadecimal form and data in quads includes providing data in hexadecimal form, reorganizing the data provided in hexadecimal form, storing the reorganized data in several memories, and reading several of the memory locations, which contain all of the elements of the quad, in one clock cycle.

Abstract: Progressive scan encoded JPEGS are decoded sequentially on a Minimum Coded Unit (MCU) basis and then the JPEG image is output one row at a time to a frame buffer. Since the entire image does not need to be decoded at once, a huge JPEG buffer is generally not required. The present invention reconstructs each MCU one scan at a time to produce complete lines of image data and thus provides an output using the image data on a line-by-line basis. This technique may require that each MCU be reconstructed scan-by-scan. This technique provides a modified entropy (Huffman) decoder in which data for different scans of an MCU of the progressively scanned JPEG image may be stored in a buffer, and a parsing and scan table element creates pointers to the memory buffer corresponding to the start of each scan level. Scan tables are also extracted for each level of scan or points to the same tables if some scan levels use the same table.

Abstract: A pixel data transfer controller reads color pixel data including pixel data pertaining to “m” color elements from a memory through a first bus having an “n”-byte width, and transfers the color pixel data to an image processing circuit through second buses which are associated with the respective color elements. The pixel data transfer controller includes: a buffer row, including buffers equivalent in number to a common multiple of “m” and “n”, each of the buffers having storage capacity for storing the pixel data pertaining to one of the color elements; a first selector, configured to sequentially store the pixel data of the color pixel data transferred through the first bus into the respective buffers of the buffer row for each color element; and a second selector, configured to output, to the second buses associated with respective color elements, the pixel data from groups of the buffers, each of the groups storing the pixel data pertaining to one of the color elements.

Abstract: A liquid crystal display apparatus and a method of driving the same capable of lowering a power consumption as well as a production cost. A liquid crystal display apparatus according to the present invention comprises: pixels including red, green and blue color pixels arranged in a direction along a data line; gate line groups, each gate line group having a set of two gate lines electrically connected each other, and each gate line crossing the data line; a data driver that drives the data line; a gate driver that drives the gate line groups; and a timing controller that controls the data driver and the gate driver, the timing controller having at least one line memory that temporarily stores data supplied to the data driver.

Abstract: A system and method for effectively storing compressed information in an electronic device includes a memory device coupled to the electronic device for storing the compressed information. A compression module sequentially performs a forward write procedure to store first components of the compressed information. The forward write procedure begins at a top location of the memory device. The compression module concurrently performs a reverse write procedure to store second components and third components of the compressed information sequentially in an interlaced configuration. The reverse write procedure begins at a bottom location of the memory device.

Abstract: In an active matrix type display device including two source line side drivers for driving a plurality of pixel TFTs, one gate line side driver, two line memories respectively including at least first and second memories, and a controller for controlling the first and second line memories, storing and transmitting of picture data of the two line memories are switched to transmit the data to the two source line side drivers at the same time.

Abstract: A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Abstract: A method for transforming an original image to a new image is provided. The original image includes M rows of original data; the new image includes Q rows of new data. The method first generates a (2i?1)th row and a (2i)th row of intermediate data respectively based on the (2i?1)th row and the (2i)th row of original data. Then, the method generates a (2i+1)th row and a (2i+2)th row of intermediate data respectively based on the (2i+1)th row and the (2i+2)th row of original data. During the process of generating the (2i+1)th row of intermediate data, the (2j?1)th row of new data is simultaneously generated based on the (2i?1)th row and the (2i+1)th row of intermediate data. During the process of generating the (2i+2)th row of intermediate data, the (2j)th row of new data is simultaneously generated based on the (2i)th row and the (2i+2)th row of intermediate data.

Abstract: A display system for adjusting video parameters of a user-selected area is disclosed. The display system includes a level detector detecting a line pattern included in one of a plurality of image lines representative of a complete image being displayed, and a pattern receiver coupled to the level detector for receiving the detected pattern, where the received pattern includes a position indicator whose ends are vertically aligned with vertical edges of the user-selected area. In addition, the display system further includes a pixel counter coupled to the pattern receiver for measuring a set of horizontal positions of the indicator ends with respect to a reference point, a pattern analyzer calculating a set of horizontal positions of vertical edges of a video control area on the basis of the positions of the indicator ends, and a video preamplifier adjusting at least one of video parameters of the video control area.

Abstract: Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.

Abstract: A frame buffer stores X pixels per line and Y lines and is read using a burst of B pixels. The un-rotated image is rotated by 90 degrees for display by writing and reading pixels from a line buffer. The line buffer stores a block of B*Y pixels. The frame buffer is logically divided into X/B blocks that are B pixels wide. Blocks are read from the frame buffer from the bottom line to the top with a burst of B pixels per line. An offset locate pixels to read in the line buffer. The offset is B for the first block, and increases by a factor of B for each block read, but wraps around modulo B*Y?1. Pixels for a next block are written into the line buffer to locations vacated as pixels are read out. The increasing offset re-orders the pixels for the rotated display order.

Abstract: Image data and/or On-Screen Display (OSD) data is generated for display on a display having rows of pixels by repeatedly combining a portion of the OSD data and a portion of the display data in a display driver chip without storing more than the portion of the display data and/or the portion of the OSD data in the display driver chip at any time. The driver chip memory thereby may be reduced.

Abstract: Apparatus for controlling a digital television display, the apparatus comprising a main processor 4, a main memory 5 coupled to said main processor 4 via address and data busses, the main memory 5 being arranged to store at least temporarily video data for display, and on-screen display graphics for overlaying on video data. Mixing means 15 is provided for mixing video data read from the main memory 5 under the control of the main processor 4, with on-screen display graphic data. At least one line buffer 13a,13b is provided for storing a line of on-screen display graphic data. Hardware processing means 9 is arranged to compose a line of on-screen display graphic data in the line buffer 13a,13b by reading appropriate on-screen display graphic data from said main memory 5 and writing it to the line buffer, and for providing the composed line of data to said mixing means 15.

Abstract: It comprises a main CPU, a main memory for storing the programs, display data and other data, a data processing circuit for performing a processing to convert the display data in the main memory to the data format for the display, a display memory section for storing the converted display data, an output processing circuit for performing a processing to output the display data on the screen, a DMA for performing a data access to the main memory, a program memory, a data memory, a display processor for interpreting the commands/data described in the program memory and the data memory and transferring the display data according thereto, and a sync signal generating circuit.

Abstract: In an active matrix type display device including two source line side drivers for driving a plurality of pixel TFTs, one gate line side driver, two line memories respectively including at least first and second memories, and a controller for controlling the first and second line memories, storing and transmitting of picture data of the two line memories are switched to transmit the data to the two source line side drivers at the same time.

Abstract: An image processing circuit comprising plural line buffers is provided. Each line buffer stores pixel data of plural pixels as line data. A first image processing part performs a first image processing task on original image data provided from the exterior by using the line data stored in at least one of the line buffers. A second image processing part performs a second image processing task on the processed image data from the first image processing part by using the line data stored in at least one of the line buffers. A line buffer selector selectively connects the first image processing part and the second image processing part to any number of line buffers. An output path selector selects one of an output path that skips the second image processing task and an output path that performs the second image processing task.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

Abstract: In response to operational instructions for changing an image quality parameter accepted in an operation unit, an image signal for displaying at least two identical images based on an inputted image signal on an image plane is generated. Further, an image quality adjusting processing is performed based on an image quality parameter before adjusting image quality with respect to a part of the generated signal for displaying an identical image, and another image quality adjusting processing is performed based on an image quality parameter after adjusting image quality with respect to another part of the generated signal for displaying another identical image.

Abstract: A method and apparatus for automatically tuning the output line rate thereof and a display controller provided with the same. The display controller of the present invention provides a display controller having a line buffer, an input means, an output means, a status detector, and an auto-tune control means. The input means is employed to write line data into the line buffer at an input line rate, and the output means is employed to read the written line data from the line buffer at an output line rate. The status detector is coupled to the input means and the output means for generating a status signal indicating whether the input line rate and the output line rate are unbalanced. The auto-tune control means is used to adjust the output line rate in response to the status signal so as to balance the input line rate and the output line rate.

Abstract: The invention provides a semiconductor device of low power consumption and low cost. A semiconductor device 50 is basically constituted of a semiconductor substrate 1 and an external signal processing substrate 8. The semiconductor substrate 1 is provided with a memory unit 3, a data driver 4, an element array 2, a scanning circuit 35 and a clock generator 36. When successively outputting an identical data signal to the element array 2 over a plurality of times, the data signal retained in the memory unit 3 is utilized.