Abstract: Described is a display system for increasing the legibility of the space limited text displays of small electronic devices. The display system couples the existing Rapid Sequential Visualization Presentation (RSVP) technology with a mathematically calculated color scheme to indicate the position of a sequentially presented word relative to the complete sentence that comprises the word.

Abstract: A method and equipment implementing the method for processing digital image information. The image information consists of a bit stream comprising a first set of successive source values, for which a corresponding output value can be determined. In the method it is read a source value, and it is determined an output value corresponding to the source value. Further, it is determined a residual part corresponding to the difference between the source value and the output value; it is calculated the sum of said residual part and the next source value; said sum is used as the next source value as a response to said sum being lower than or equal to a predetermined threshold value. The invention provides a fast colour dithering method for such solutions in which the processing time of an image is desired to be the shortest possible.

Abstract: A data conversion apparatus for converting index data to real data and an image generation apparatus for converting index texture data to real texture data by the data conversion to make it possible to suitably carry out texture mapping.

Abstract: An encoder receives a video input that includes initial video data and encodes the initial video data as encoded video data, such that the encoded video data comprises fewer bytes than the initial video data. The encoded video data is transmitted through a computer network to a decoder that receives the encoded video data and reconstructs an image representative of the video input for viewing on a display. A sensor senses at least one of viewer information representative of at least one of a location and movement of a viewer, and display information identifying the display. Viewer data representative of the at least one of the viewer information and the display information is transmitted to the encoder to modify the method of encoding the initial video data.

Abstract: The present invention provides an apparatus and method for providing extra bits for post image processing, thereby to increase the image bit depth and compensate the loss of image accuracy. The present invention operates on multiple least insignificant bits of the post-pixel memory device and the pre-pixel memory device to generate compensation bits. The compensation bits can be appended to the rightmost bit positions of the current pixel. With the compensation bits, the image bit depth can be increased. Consequently, the image will be processed more accurately after post processing. Moreover, since the extended bitstream preserves the complete bits of the original pixel, therefore the accuracy of the original image will not be affected by the compensation bits.

Abstract: A method and system for capturing live video signal data using bufferless data compression is disclosed. Live video signal data is vertically scaled. A 4:2:2 to 4:2:0 color format conversion is performed simultaneous with the vertical scaling step. A one-dimensional bufferless discrete cosine transform is performed on the scaled live video signal data to create a plurality of scaled DCT coefficients. Each of the plurality of scaled DCT coefficients are then Huffman coded. Each of the Huffman encoded DCT coefficients may then be sent via a USB interface to a USB bus.

Abstract: A graphics processor displays pixels in an image at non-uniform resolution, using a maximum resolution in the interior of a surface in the image, and a lower resolution at edges. Higher color resolution in the interior eliminates color aliasing that would otherwise be caused if the interior were displayed at the lower resolution. Lower resolution at the edges is not noticeable to the human eye, and allows the graphics processor to use one or more low resolution color signals in generating the displayed image, thereby reducing hardware (e.g. memory locations required to store such signals, and lines required to route such signals). One such processor (not necessarily a graphics processor) includes a resolution reducer and a resolution enhancer that respectively reduce and enhance the resolution of a signal. Specifically, the resolution reducer reduces the resolution of a high resolution signal to generate a low resolution signal.

Abstract: The color of a pixel is represented in a pixel storage word, wherein color coordinate data and intensity data are coded separately in two fields of the pixel storage word, the color field and the intensity field. This permits a range of colors to be represented in a relatively small number of bits. In one embodiment of the invention, each of the three color coordinates of an input color is coded separately. The coded color components are concatenated and placed in a coded color field of the pixel storage word. In another embodiment of the invention, the color coordinate data is encoded as a color index, a binary value which maps to color coordinate data according to a predefined color table. Intensity data is also encoded with a binary value. The coded intensity can represent the intensity directly, or can be an index to intensity data stored in a predetermined intensity table.

Abstract: A method and a system for a fast and reliable color reduction from multiple bit color representations to 4 bit color representations. The method for color reduction in a computer system having a three color model for color representation of a pixel, each color being represented by a multiple bit pattern, reduces the color to a four bit value by analysing the first bit of each of said three multiple bit patterns to determine tone; assigning a value to the first bit of said four bit value, based on said determined tone; and assigning the remaining three bits of said four bit value by utilising one pre-determined bit from each of said three multiple bit patterns.

Abstract: A display device having a pixel section is provided, in which a plural number of pixel TFTs are arranged in a matrix shape; a source driver and a gate driver for driving the plural number of TFTs; a processing circuit for converting externally inputted m-bit digital video data into 2m−n pieces of n-bit digital video data (where m and n are both positive integers greater than or equal to 2, and m>n); and a D/A converter circuit for converting the n-bit digital video data into analog video data, and for outputting the n-bit digital video data to the source driver. The display device is characterized in that the processing circuit randomly outputs the 2m−n pieces of n-bit digital data to the D/A converter circuit, and in that a one-frame image is formed by displaying 2m−n subframes formed from the n-bit digital video data.

Abstract: A method and apparatus for dithering for color computer display systems includes the addition of a noise component to each of the color components of each pixel in a pseudo-random manner. The noise component is preferably different for each color component. Taking the image as a whole, the noise component repeats on a regular basis but is preferably selected so as not to repeat on adjacent pixels. The image is divided into squares of pixels and the same noise component is added to each of the same relative pixels from square to square. The preferred square of pixels is four pixels wide by four pixels high. The value of the noise component is chosen such that the most significant bit alternates both horizontally and vertically from pixel to pixel within the square of pixels.

Abstract: In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored within three quad words in a manner that reduces the required hardware from prior approaches and fully utilizes video memory.

Abstract: A liquid crystal display panel driving device includes a first signal level detection unit for detecting a level of an input image signal, a memory unit for delaying the input image signal by an arbitrary constant time period, a second signal level detection unit for detecting a level of a signal output from the memory unit, and a corrected-image-signal calculation unit for correcting the input image signal based on an output from the first signal level detection unit, an output from the second signal level detection unit, and the arbitrary constant time period, and for outputting the resultant image signal.

Abstract: In one embodiment of the present invention, a 10-bit encoded video word is received and stored as two five-bit representations. One of the stored five-bit representations is selected by a multiplexor and provided to a parallel-to-serial converter. The parallel-to-serial converter receives control signals from a multiphase clock. Specifically, the multiphase clock provides a five-phase multi-phased clocks in order to control the parallel-to-serial converter. The serial-to-parallel converter provides a 10-bit serial representation of the 10-bit encoded input.

Abstract: In an operation of an address period for addressing cells of a display device, such as a plasma display panel, comprising a plurality of cells of three kinds, red (R), green (G), blue (B), which are arranged on a plane for forming a display surface thereof, in which each of said cells comprising: a pair of transparent electrodes provided in parallel to each other; an address electrode being positioned opposing the pair of transparent electrodes; luminescence medium provided on the address electrode; and a discharge space being defined between the pair of transparent electrodes and said fluorescence medium on the address electrode, wherein the address discharge is conducted by applying an address voltage to the address electrode, and the address voltage applied is determined depending upon the each kind of the cells, R, G and B.

Abstract: Picture data composed of a color palette storage address and palette number data is read from memory. On the basis of the color palette storage address, a color palette is taken from among one or more color palettes stored in the memory. The picture data is colored according to the extracted color palette for each piece of the palette number data.

Abstract: The image data transferring apparatus of this invention determines that the change in the image is very small when a change in the image is not detected during a given time period, for example, and generates transmission data which causes image data displaying a full color image of, for example, 24 bits per pixel to be displayed in the receiving side in a relatively small number of frames in a unit time for transmission. Conversely, the image data transferring apparatus transmits reduced color data which is reduced from 24 bits per pixel to 4 bits per pixel in a relatively large number of frames in a unit time to the receiving side when it is determined that many changes are included in the image.

Abstract: In response to a change in the color depth of a computer system's display device, the invention dynamically changes the color depth of existing objects in system memory to match the changed color depth of the device. As a result open applications need not be shut down and then reopened to change the color depth of objects already in system memory. The dynamic changing is accomplished through a number of functions calls between an application, the operating system and a display driver. In one embodiment of the invention, copies with the changed color depth are made at one time of all objects in system memory and the original objects discarded. The copies are then transferred to screen memory (if the display device is a video display terminal) for display as they are requested. In another embodiment of the invention, copies with the changed color depth are made selectively as the objects are transferred to the screen memory.

Abstract: A signal processing apparatus for linear interpolation capable of performing operations to obtain suitable original data even when an interpolation coefficient &agr; is 1.0, wherein a correction term selects A when &agr;=0×FF (&agr;=1.0) and selects B when the bit is 0. The selected data becomes an element of addition by being shifted for the number of bits of &agr;. A product summation operation term uses the upper 8 bits of the result of multiplication of 8 bits×8 bits and shifts the 8-bit result of operation 8 bits to the left so as to enable further addition of the product summation operation term. An adder adds the shifted correction term, the partial products out—0 to out—7, and the product summation operation term and outputs the upper 8 bits as the result of the operation.

Abstract: A method and apparatus for multisample dithering is provided. For the method of the present invention, a graphics pipeline generates a series of b-bit color sample values for each pixel that is to be processed. Each color sample is defined to include one or more omitted values. The omitted values allow the color sample values to have a range that exceeds the range that would normally be associated with the b-bits of each color sample value. The extended range of the color sample values allows the color sample values to be summed to exactly reconstruct all color values. At the same time, the values in the color samples are close to exact values. This means that constructed color values are close to their correct values.

Abstract: In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored within three quad words in a manner that reduces the required hardware from prior approaches and fully utilizes video memory.

Abstract: A system and method are provided for driving a digital display adapted to depict a first number of bits per color field during each frame. In use, a second number of bits is displayed which is greater than the first number of bits. This is accomplished by alternating the display of the bits between frames. To this end, additional bits of color are displayed without increasing the number of bits per color field during each frame.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: An encoder capable of making a processing time shorter, wherein the position of a first “1” bit seen from the MSB of digital data is output as a first bit encoded data and the second “1” bit is output as the second bit encoded data. A predetermined calculation is performed in parallel on the upper 8 bits of the digital data in the valid detector, the priority encoder, and the first valid bit mask unit, while a predetermined calculation is performed in parallel on the lower 8 bits in another priority encoder and another first valid bit mask unit.

Abstract: The present invention relates to a process for converting the representation of a video image between two coding systems with the aid of two respective sets of parameters, in which each set of parameters is deduced from the other by means of a matrix transformation. For each parameter of the set to be converted from the first coding system to the second coding system, a breakdown (11A, 11B, 11C; 12A, 12B, 12C) is selected in the parameters of the second coding system representing the value of the parameter in the matrix transformation. The breakdowns of each of the parameters to be converted are added and may then be shifted and reorganized. Each of the parameters of the two coding systems have ranges of authorized values. In the conversion process, the values of the parameters to be converted and/or the values of the converted parameters that are outside the corresponding ranges of values are clipped.

Abstract: A non-linear digital video compression circuit and method. The video compression circuit includes a source of digital video data signal, wherein the digital video data has M-bits of information for each of a Y, U, and V value per pixel. Y represents a luminance component, and U and V each represent portions of a two-dimensional chromaticity component. The circuit also includes a compression lookup table having an M-bit input coupled to the source of digital video data, and an N-bit compressed digital video data output, where N is less than M. The compression lookup table includes a non-linear compression transformation for at least one of Y, U and V. In one embodiment, the compression lookup table includes a non-linear compression transformation that provides a different conversion for Y than for U or that provides a different conversion for Y than for V.

Abstract: A method and apparatus for dithering for color computer display systems includes the addition of a noise component to each of the color components of each pixel in a pseudo-random manner. The noise component is preferably different for each color component. Taking the image as a whole, the noise component repeats on a regular basis but is preferably selected so as not to repeat on adjacent pixels. The image is divided into squares of pixels and the same noise component is added to each of the same relative pixels from square to square. The preferred square of pixels is four pixels wide by four pixels high. The value of the noise component is chosen such that the most significant bit alternates both horizontally and vertically from pixel to pixel within the square of pixels.