Involving Both Line Number And Field Rate Conversion (e.g., Pal To Ntsc) Patents (Class 348/443)
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Publication number: 20090079866Abstract: A data interpolation apparatus at intermediate pixels between upper and lower pixels. An upper oblique correlation is calculated between data of an immediate upper pixel and a corresponding lower pixel positioned downward in a maximum correlation direction with respect to the immediate upper pixel. A lower oblique correlation is similarly calculated between data of an immediate lower pixel and a corresponding upper pixel. An interpolation signal is obtained by mixing an oblique pixel sum and a vertical pixel sum, while changing mixing ratio based on a comparison of a vertical correlation, and the upper and lower oblique correlation. When the interpolation signal is constituted without the vertical pixel sum, an interpolation signal with respect to intermediate pixels immediate upward/downward of the corresponding lower/upper pixel is generated by excluding a vertical sum that includes data of the corresponding upper and/or lower pixels.Type: ApplicationFiled: July 11, 2008Publication date: March 26, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Toshiyuki Namioka
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Patent number: 7508447Abstract: The design of a video processing core designed for processing video signals of a specific video format requires a high expense. It is therefore desirable to be able to use such a video processing core for other video formats as well.Type: GrantFiled: January 12, 2005Date of Patent: March 24, 2009Assignee: Sony Deutschland GmbHInventors: Jörg Tappermann, Alexander Scholz, Gil Golov, Alfried Dilly
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Patent number: 7489257Abstract: Presented herein is a system that enables a vehicle operator to record continuous images of surrounding traffic activity, wherein the vehicle is equipped with a video camera 20 for continuously recording the vehicle surroundings. The system further comprises a marking switch 42 that enables the vehicle operator, upon viewing a possible traffic violation, to trigger a marking module 40; a marking module 40 that identifies and marks, in real-time, at least one location of the video recording that relates to the at least one possible traffic violation committed by at least one other vehicle operator; a portable storage device 30; an editing module 50 for preparing recorded segments for transmission, which include at least one recording portion that appears before the added mark and at least one recording portion that appears after the added mark; and a communication module 60 for transmitting the prepared recording segments to a designated server.Type: GrantFiled: September 11, 2006Date of Patent: February 10, 2009Inventor: Doron Izakov
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Patent number: 7453519Abstract: This imaging device includes an imaging element, a field rate conversion processing section, and a frame rate conversion processing section. The imaging element converts an image of a photoelectric subject photographically, and outputs a picture image signal which consists of frames at a first frame rate. The field rate conversion processing section converts the picture image signal at the first frame rate into a television signal at a second frame rate which is smaller than the first frame rate. The frame rate conversion processing section converts the picture image signal at the first frame rate into a cinema film signal at a third frame rate which is smaller than the first frame rate, and which is different from the second frame rate.Type: GrantFiled: March 25, 2005Date of Patent: November 18, 2008Assignee: Olympus CorporationInventors: Akihiro Kubota, Shinzo Matsui
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Patent number: 7446818Abstract: An apparatus and related method for detecting film mode using motion estimation. In the method, a pixel region in each field is sequentially chosen as a target pixel region in a target field to be processed with a motion estimation operation.Type: GrantFiled: January 19, 2005Date of Patent: November 4, 2008Assignee: Realtek Semiconductor Corp.Inventor: Po-Wei Chao
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Patent number: 7428008Abstract: When an image signal, which was picked up in a 24p image format and temporarily recorded on a temporary recording device, is read in a 60i image format, the image signal is subjected to a 2:3:2:3 pull-down conversion process so that it becomes possible to omit compressing/expanding processes. At this time, the reading operation is controlled on the basis of the figure of time codes so that the pull-down conversion system at the time of a joining image-pickup process is maintained. In this case, by properly switching controlling methods among a plurality of pull-down controlling methods, it is possible to achieve an image conversion system capable of providing an optimal image conversion process in accordance with desired image-pickup purposes and editing processes.Type: GrantFiled: March 17, 2003Date of Patent: September 23, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ichiro Okamoto, Akihira Sakai
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Patent number: 7425990Abstract: To realize a motion compensation device capable of more appropriately compensating the movement of a video signal subjected to double-speed conversion. A motion vector between an image of a current field in a double-speed-converted video signal and an image of a reference field that is one frame or two frames later is detected, the pixels of the current field are shifted based on the motion vector and the pixels of the reference field are shifted in an opposite direction based on the motion vector. Then simple averaging or weighted average according to the shift amount is performed on the pixels of the current field and the pixels of the reference field to compensate the current field, thereby being capable of compensating the movement between fields so as to be much smoother than conventional cases.Type: GrantFiled: May 12, 2004Date of Patent: September 16, 2008Assignee: Sony CorporationInventors: Takaya Hoshino, Kazuhiko Nishibori, Toshio Sarugaku, Masuyoshi Kurokawa
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Publication number: 20080211965Abstract: The present invention is generally directed to automated methods and systems for converting image streams having a first frame rate to a second frame rate without the need for user intervention. Embodiments of the present invention obviate the effects of processing of a telecine process. In one embodiment, where frames are encoded by a single video field, a statistical analysis of the differences between adjacent frames reveals a telecine pattern, thereby identifying which frames to remove. In another embodiment, where frames are encoded by even and odd video fields, which are interleaved to produce the frame, a statistical analysis of the differences between adjacent fields reveals the telecine pattern, identifies which frames to remove, and identifies frames that are candidates for re-interleaving.Type: ApplicationFiled: April 2, 2008Publication date: September 4, 2008Applicant: RealNetworks, Inc.Inventor: Alan Francis Lippman
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Patent number: 7411617Abstract: In image-data recording processing performed when a video output conforms to the PAL system, a display-signal processing section receives image data having a frame rate of 30 Hz recorded in a memory, through a bus, converts the image data to image data having an NTSC frame rate of 29.97 Hz by a frame-rate conversion method in which thinning out is performed according to the ratio of frame rates, and outputs it to a display section and a codec-IC interface. The display-signal processing section also converts to image data having a PAL frame rate of 25 Hz, and outputs it to a video-output interface. In other words, image data is processed at a frame rate not related to the output, and then converted to image data having a frame rate suited for the output, and output. This invention can be used in digital cameras.Type: GrantFiled: August 18, 2003Date of Patent: August 12, 2008Assignee: Sony CorporationInventors: Tsutomu Kume, Shinya Ishii, Tokuichiro Yamada
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Patent number: 7408589Abstract: Provided is a video signal processing circuit capable, in a scale conversion, of rendering a circuit scale small and alleviating a deterioration of a vertical resolution. A vertical scaler is provided with a function of increasing the number of scanning lines of an input video signal. An increasing rate thereof is adjacent to 1.0. In a case that the number of unit output lines is M, the number of unit input lines is N, and the increasing rate is ?, a condition of 0<?<2 is satisfied. That is, ? is adjacent to 1.0. A number-of-a-plurality-of-time reading-out circuit performs a reading-out by a 3-time clock toward the input video signal. In addition, the number-of-a-plurality-of-time reading-out circuit is configured in such a manner as not to select the video signal read out by an address overtaking. A horizontal scaler interpolates the number of dots of a horizontal direction according to the number of horizontal dots of a liquid crystal panel.Type: GrantFiled: April 21, 2005Date of Patent: August 5, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Masami Ebara, Toru Sasaki
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Patent number: 7375764Abstract: A method for managing vertical format converter line memories includes writing a number of first input video lines into the VFC line memories, writing an additional video line into the VFC line memories, and reading respective pixels of the first input video lines and the additional input video line from the VFC line memories in parallel. The reading of respective pixels is commenced prior to completion of the writing of the additional video line. A digital video receiving system includes a somewhat similarly configured video processor.Type: GrantFiled: May 12, 2003Date of Patent: May 20, 2008Assignee: Thomson LicensingInventors: Michael Dwayne Knox, Guenter Anton Grimm
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Patent number: 7369179Abstract: The present invention is generally directed to automated methods and systems for converting image streams having a first frame rate to a second frame rate without the need for user intervention. Embodiments of the present invention obviate the effects of processing of a telecine process. In one embodiment, where frames are encoded by a single video field, a statistical analysis of the differences between adjacent frames reveals a telecine pattern, thereby identifying which frames to remove. In another embodiment, where frames are encoded by even and odd video fields, which are interleaved to produce the frame, a statistical analysis of the differences between adjacent fields reveals the telecine pattern, identifies which frames to remove, and identifies frames that are candidates for re-interleaving.Type: GrantFiled: March 23, 2004Date of Patent: May 6, 2008Assignee: RealNetworks, Inc.Inventor: Alan Francis Lippman
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Publication number: 20080100740Abstract: Methods for adjusting digital video signals, performed by an image generating device of a portable media player, are disclosed. A first signal adjustment unit reduces a resolution of a video frame to generate a reduced video frame by alternately dropping half of the scan lines of the video frame, and repeatedly drops scan lines after at least two scan lines until reaching the last scan line. The content of a first video frame is adjusted to a second video frame in response to a second signal adjustment unit before passing to the display module by the image generating device. The display module is directed to prevent adjustment of the second video frame by the first signal adjustment unit for generating a display video frame. The second video frame is adjusted by the second signal adjustment unit and output to the display module.Type: ApplicationFiled: October 24, 2007Publication date: May 1, 2008Applicant: MEDIATEK INC.Inventors: Tzu-Shiun LIU, Hua WU
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Patent number: 7327397Abstract: The present invention provides an image signal processing apparatus and a method thereof which shifts positions of each detected pixel in image signals generated by performing double-speed conversion, wherein a difference value in pixel signal level between a detected pixel in a current field and a detected pixel at the same position in a field which comes one frame behind the current field is calculated, to specify a first field, a motion vector for a field which comes one frame or two frames behind the current field is detected with respect to the detected pixel in the current field, interpolation pixel data for the detected pixel is calculated based on the detected pixel in the current field and the each pixel in the field which comes one frame or two frames behind the current field, the interpolation pixel data is disposed in the pixel position obtained by shifting the position of the detected pixel in the current field in a direction along the motion vector, in a field subsequent to the first field, andType: GrantFiled: December 13, 2002Date of Patent: February 5, 2008Assignee: Sony CorporationInventors: Koji Aoyama, Makoto Kondo, Kazuhiko Nishibori
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Publication number: 20080007649Abstract: A video processing system applies sub-frame processing to video data to generate both a first sequence of sub-frames of video data and a second sequence of sub-frames of video data. The first sequence of sub-frames of video data and the second sequence of sub-frames of video data are defined by metadata. The processing circuitry generates a third sequence of sub-frames of video data by combining the first sequence of sub-frames of video data with the second sequence of sub-frames of video data. Adaptive video processing circuitry receives encoded source video data, raw source video data, similar display metadata, target display metadata, and/or target display information. The adaptive video processing circuitry processes its input information to produce one or more outputs that include tailored metadata, encoded target display video data, target display video data, and DRM/Billing Signaling.Type: ApplicationFiled: July 20, 2006Publication date: January 10, 2008Applicant: Broadcom Corporation, a California CorporationInventor: James D. Bennett
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Publication number: 20080007651Abstract: A distribution server includes a communication interface, storage, and processing circuitry. The processing circuitry retrieves a full screen sequence of video and sub-frame metadata relating to the full screen sequence of video. The processing circuitry sub-frame processes the sequence of full screen video using the sub-frame metadata to produce a plurality of sub-frames of video. The processing circuitry assembles the plurality of sub-frames of video to produce an output sequence for a client system. The distribution server may also receive, store, and distribute the sub-frame metadata and/or the video for subsequent use by a video processing system.Type: ApplicationFiled: August 18, 2006Publication date: January 10, 2008Applicant: Broadcom Corporation, a California CorporationInventor: James D. Bennett
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Publication number: 20080007650Abstract: A removable storage media is received by and interacts with both a first video player system and a second video player system. The first video player system has a first video display that has a first display characteristic and the second video player system has a second video display that has a second display characteristic, the first display characteristic being different from the second display characteristic. The removable storage media includes a plurality of storage locations and stores a sequence of full frames of video data, first sub-frame metadata, and second sub-frame metadata. The first sub-frame metadata is generated and the second sub-frame metadata are used to process the full frames of video data to correspond to the first video display and the second video display, respectively.Type: ApplicationFiled: August 18, 2006Publication date: January 10, 2008Applicant: Broadcom Corporation, a California CorporationInventor: James D. Bennett
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Patent number: 7271840Abstract: Method for determining entropy of a pixel of a real time streaming digital video image signal, particularly applicable for identifying the origin of, and processing, in real time, pixels of interlaced, non-interlaced, or de-interlaced, streaming digital video image signals, and for correcting errors produced during editing of streaming digital video image signals. Based upon the fundamental aspect of determining the degree or extent of randomness or disorder, or entropy, and determining the fluctuation thereof, of each pixel relative to inter-local neighborhoods and intra-local neighborhoods of selected pixels originating from the streaming digital video image input signal. Automatically detects and identifies original mode of the video input signal (film movie, video camera, or graphics). Independent of type of mode conversion used for generating the original video input signal, and not based upon an ‘a priori’ type of pattern recognition method.Type: GrantFiled: October 31, 2002Date of Patent: September 18, 2007Assignee: Intel CorporationInventor: Yosef Segman
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Patent number: 7256836Abstract: There is provided an image processing method capable of improving the picture quality. The image processing method comprises: incorporating input frame pictures to be displayed on a display device, on the basis of an input picture signal and an input synchronizing signal which is synchronized with the input picture signal; recording the incorporated input frame pictures in an input frame memory; and producing output frame pictures from input frame pictures, which have been recorded in the input frame memory, by producing an interpolated picture or inserting a black raster picture or thinning out the frame pictures, between input frame pictures corresponding to a picture information of the input frame picture to be displayed, on the basis of the picture information and the input synchronizing signal and an output synchronizing signal.Type: GrantFiled: October 22, 2004Date of Patent: August 14, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Goh Itoh, Haruhiko Okumura
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Patent number: 7250979Abstract: A format converting apparatus and method for performing a resolution conversion, frame rate conversion, scanning method conversion, aspect ratio conversion, chroma format conversion, color space conversion, gamma correction, and geometric correction in one chip are disclosed. A digital TV can process various video signal standards such as the digital TV signal, the analog TV signal, the computer video signal, and the component signal as well as other video signals of more wide range in a same block. More especially, since all format conversion is performed in one chip, new additional input signal does not make addition of the hardware so that the cost can be reduced.Type: GrantFiled: August 14, 2003Date of Patent: July 31, 2007Assignee: LG Electronics Inc.Inventor: Seung Jong Choi
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Patent number: 7236207Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).Type: GrantFiled: January 22, 2003Date of Patent: June 26, 2007Assignee: Broadcom CorporationInventors: Sherman (Xuemin) Chen, Alexander G. MacInnis
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Patent number: 7221404Abstract: To enable a satisfactory suppression of overemphasized component after converting the number of scanning lines of video signal, when the video signal is converted in the number of scanning lines and a high-frequency component at least in a vertical direction of the converted video signal is emphasized, signals delayed by a plurality of stages of time equal to or more than a time required for converting the number of scanning lines are obtained by a delay circuit 18, and an appropriate delay signal is selected from among the plurality of delay signals by a selection circuit 19. The selected delay signal is compared with the emphasized video signal in emphasized-component detector circuits 16a, 16b and the overemphasized component is detected. Processing to suppress the emphasis is performed by suppressor circuits 13a, 13b with respect to a portion where the overemphasized signal component is detected.Type: GrantFiled: August 15, 2003Date of Patent: May 22, 2007Assignee: Sony CorporationInventors: Seiko Imai, Toshio Sarugaku, Naoki Kaneko, Takaya Hoshino
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Patent number: 7218355Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.Type: GrantFiled: November 25, 2003Date of Patent: May 15, 2007Inventors: Qinggang Zhou, Clyde H. Nagakura, Sheng-Fu Wu, Andrew K. Chan
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Patent number: 7206025Abstract: Device and method for converting a format of a video signal in a digital TV receiver is provided. Format conversion can be carried out at one chip of a format converting device, inclusive of conversion of resolution, frame rate, scanning method, aspect ratio, color space, chroma format, and gamma correction. Therefore, the digital TV receiver is made to convert a wide range of video signals inclusive of, not only a digital TV broadcasting signal, but also analog TV broadcasting signal, and computer video signal, at one chip of system block. Moreover, the digital TV receiver is made to provide a variety of standards of format converted video signals, not only to the connected display, but also to other general video signal processing devices.Type: GrantFiled: March 23, 2001Date of Patent: April 17, 2007Assignee: LG Electronics Inc.Inventor: Seung Jong Choi
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Patent number: 7158186Abstract: A video display system is disclosed. The video display system comprises a display generator for providing a display timing signal and a frame rate converter for receiving input video data, input video timing, and for providing output video data. The system includes a control logic for receiving a frame rate indication signal, the video input timing and the display timing signal. The control logic changes the display frame rate of the display generator in accordance with the native frame rate of the program, and in such a way as to maintain a stable image throughout.Type: GrantFiled: May 27, 2003Date of Patent: January 2, 2007Assignee: Genesis Microchip Inc.Inventors: Steve Selby, Peter Dean Swartz
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Patent number: 7098959Abstract: A first motion vector is estimated by using a first frame and a second frame that follows the first frame. A support frame is generated from at least either the first or the second frame by using the first motion vector. The support frame is divided into a plurality of small blocks. Motion vector candidates are estimated by using the first and second frames, in relation to each of the small blocks. A small block on the first frame, a small block on the second frame and the small blocks on the support frame are examined. The small block on the first frame and the small block on the second frame correspond to each of the motion vector candidates. A second motion vector is selected from the motion vector candidates, and points the small block on the first frame and the small block on the second frame which have the highest correlation with each of the small blocks on the support frame. An interpolated frame is generated from at least either the first or the second frame by using the second motion vector.Type: GrantFiled: September 9, 2003Date of Patent: August 29, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Nao Mishima, Goh Itoh
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Patent number: 7034889Abstract: A signal processing unit for a digital TV system comprises a first device which acts on a video signal with graphical picture elements and text characters. A second device performs frame-rate conversion on the output of the first device. The output of the second device drives a display driver.Type: GrantFiled: June 28, 2001Date of Patent: April 25, 2006Assignee: Infineon Technologies AGInventors: Bernd Burchard, Ralf Schwendt
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Patent number: 7015975Abstract: The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selectedType: GrantFiled: July 17, 2001Date of Patent: March 21, 2006Assignee: Texas Instruments IncorporatedInventors: Hiroshi Miyaguchi, Takao Kojima
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Patent number: 7006112Abstract: A method for scaling an image frame by an off-screen technology is provided. An image frame consisting of n rows and m columns of data is stored into a storage device. The image frame is divided into a plurality of image portions. Then, the plurality of image portions are picked in sequence to a frame buffer register. An image scaling operation is performed for each picked image portion, and then the scaled image portion is cleared from the frame buffer register.Type: GrantFiled: November 21, 2002Date of Patent: February 28, 2006Assignee: Via Technologies, Inc.Inventors: Pingo Chia, Titan Sun
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Patent number: 7002564Abstract: The invention describes a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input vertical refresh rate and displays the image data at a vertical refresh rate that is a predetermined fraction of the input vertical refresh rate.Type: GrantFiled: March 6, 2002Date of Patent: February 21, 2006Assignee: Pixelworks, Inc.Inventor: Robert Y. Greenberg
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Patent number: 6970110Abstract: A data compression algorithm which computes from a given probability density, in continuous or histogram form, a “probability centrifuge” probability density and also the Fisher information of the density. The density preserves Shannon entropy of the original density and the Fisher information represents the minimum Fisher information obtainable by “lateral” adiabatic reduction. The data compression algorithm can alternately be used to perform a “vertically” adiabatic reduction, a “radial” adiabatic reduction, or a “sectoral” adiabatic reduction. Said algorithm may provide alternate information for applications such as image reconstruction and protein folding analysis.Type: GrantFiled: February 15, 2005Date of Patent: November 29, 2005Inventor: Dennis G. Collins
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Patent number: 6891572Abstract: A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.Type: GrantFiled: May 8, 2001Date of Patent: May 10, 2005Assignee: Sony CorporationInventor: Nobuo Ueki
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Patent number: 6839089Abstract: There is provided a signal processing device in which its structure is simplified and a source subjected to a pull-down processing is detected at high precision. The signal processing device includes a comparison portion and a detection portion in which fields constituting a signal source are successively inputted, two fields are compared with each other, and it is judged whether or not there is a motion between the two fields, and a logic block for shifting a state on the basis of a judgement result as to whether or not there is a motion in the detection portion and for controlling judgement characteristics of the detection portion on the basis of the shifted state.Type: GrantFiled: June 27, 2001Date of Patent: January 4, 2005Assignee: Sony CorporationInventor: Muzaffar Husain Bin Fakhruddin
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Patent number: 6836293Abstract: There is provided an image processing method capable of improving the picture quality. The image processing method comprises: incorporating input frame pictures to be displayed on a display device, on the basis of an input picture signal and an input synchronizing signal which is synchronized with the input picture signal; recording the incorporated input frame pictures in an input frame memory; and producing output frame pictures from input frame pictures, which have been recorded in the input frame memory, by producing an interpolated picture or inserting a black raster picture or thinning out the frame pictures, between input frame pictures corresponding to a picture information of the input frame picture to be displayed, on the basis of the picture information and the input synchronizing signal and an output synchronizing signal.Type: GrantFiled: June 21, 2001Date of Patent: December 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Goh Itoh, Haruhiko Okumura
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Patent number: 6798458Abstract: In an image signal converter (ICp1) converting a component video signal (Scv) of an interlaced scanning format for image display on a display device for an image signal of a progressive scanning format (Scv, p) for image display on the display device, an up-converter (11) converts the component video signal (Scv) of the interlaced scanning format into the one of the progressive scanning format. A scanning format determination part (4, 14, 15) determines based on a luminance signal (Y) included in the component video signal (Scv1, Scv2) whether the component video signal (Scv1, Scv2) is of the interlaced or progressive scanning format. Based on the determination result of the scanning format determination part (15), an output destination selector (3B, 15A) selects an output destination of the component video signal (Scv1, Scv2).Type: GrantFiled: May 31, 2000Date of Patent: September 28, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toyoaki Unemura
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Publication number: 20040160526Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.Type: ApplicationFiled: November 25, 2003Publication date: August 19, 2004Applicant: VIma Microsystems CorporationInventors: Qinggang Zhou, Clyde H. Nagakura, Sheng-Fu Wu, Andrew K. Chan
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Publication number: 20040091170Abstract: Two images are analyzed to compute a set of motion vectors that describes motion between the first and second images. A motion vector is computed for each pixel in an image at a time between the first and second images. This set of motion vectors may be defined at any time between the first and second images, such as the midpoint. The motion vectors may be computed using any of several techniques. An example technique is based on the constant brightness constraint, also referred to as optical flow. Each vector is specified at a pixel center in an image defined at the time between the first and second images. The vectors may point to points in the first and second images that are not on pixel centers. The motion vectors are used to warp the first and second images to a point in time of an output image between the first and second images using a factor that represents the time between the first and second image at which the output image occurs.Type: ApplicationFiled: November 3, 2003Publication date: May 13, 2004Inventors: Katherine H. Cornog, Garth A. Dickie, Peter J. Fasciano, Randy M. Fayan, Robert A. Gonsalves
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Patent number: 6727958Abstract: In a method and apparatus for displaying resized pictures on an interlaced target display system, the contents of an input video source are initially read and decoded to obtain original input picture data and title format information that indicates scan format of the original input picture data. According to the scan format of the original picture data and the identified television system specification of the interlaced target display system, a resizing operation is then performed to resize the original input picture data and obtain resized frames having a frame size sufficient for division into even and odd fields with field size characteristics that comply with the television system specification of the interlaced target display system.Type: GrantFiled: August 20, 1999Date of Patent: April 27, 2004Assignee: Winbond Electronics Corp.Inventor: Rong-Fuh Shyu
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Patent number: 6724433Abstract: The present invention is generally directed to automated methods and systems for converting image streams having a first frame rate to a second frame rate without the need for user intervention. Embodiments of the present invention obviate the effects of processing of a telecine process. In one embodiment, where frames are encoded by a single video field, a statistical analysis of the differences between adjacent frames reveals a telecine pattern, thereby identifying which frames to remove. In another embodiment, where frames are encoded by even and odd video fields, which are interleaved to produce the frame, a statistical analysis of the differences between adjacent fields reveals the telecine pattern, identifies which frames to remove, and identifies frames that are candidates for re-interleaving.Type: GrantFiled: December 6, 2000Date of Patent: April 20, 2004Assignee: RealNetworks, Inc.Inventor: Alan Francis Lippman
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Patent number: 6707502Abstract: An interlaced input picture signal having a field frequency of 50 Hz is supplied. A class detecting circuit detects a class corresponding to a pattern of a level distribution of input pixels in the vicinity of an output pixel to be generated. A predictive coefficient set corresponding to the class is read from a predictive coefficient memory. Sum-of-product calculating circuits calculate data of an output picture signal using a linear estimating expression of predictive taps (pixels of an input picture signal) and predictive coefficient sets. The sum-of-product calculating circuits output pixel values M and S of an output picture signal having a field frequency of 50 Hz. The pixel values M and S that are output from the sum-of-product calculating circuits are converted into a signal having a frequency of 60 Hz by respective field memories. A selector alternately selects outputs of the field memories and generates an output picture signal (having a field frequency of 60 Hz).Type: GrantFiled: February 12, 2001Date of Patent: March 16, 2004Assignee: Sony CorporationInventors: Tetsujiro Kondo, Yasushi Tatehira, Masashi Uchida, Masaaki Hattori, Takeshi Miyai
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Patent number: 6697119Abstract: A data rate conversion apparatus of the present invention is a data rate conversion apparatus, comprising: an information input device for receiving frame information at a first data rate; an information storage memory including a plurality of buffers for storing the frame information; a write control device for selecting one of the buffers to which the frame information is to be written, and writing the frame information to the selected buffer; a read control device for selecting one of the buffers from which the frame information is to be read, and reading the frame information from the selected buffer; and an information output device for outputting the frame information, which is read by the read control device, at a second data rate which is different from the first data rate.Type: GrantFiled: January 30, 2001Date of Patent: February 24, 2004Assignee: Sharp Kabushiki KaishaInventor: Wataru Tachibana
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Patent number: 6670994Abstract: A home entertainment appliance includes a computer system and a television system. A video monitor or television monitor of the home entertainment system shows a sequence of video frames generated in the appliance based upon at least one received sequence of interlaced video fields each containing a number of scan lines. A video system of the appliance receives a first field, temporarily stores the first field in an input buffer, and then in a loop, while video fields are being received, performs various other steps. The other steps include receiving a next field, compensating the field in the input buffer, deinterlacing the received field with the compensated field in the input buffer, temporarily storing the received field, merging the received field and the compensated field into a video frame of the second sequence, and providing the video frame of the second sequence to a subsequent device.Type: GrantFiled: December 16, 2002Date of Patent: December 30, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christopher Voltz, Drew S. Johnson
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Patent number: 6661470Abstract: A method for displaying a moving picture having a proper tone by changing a combination of subfields constituting a field of the moving picture, the subfields each having a different weight of luminance, a motion vector indicating a moved direction of the image and a moved quantity thereof is detected from image data, new image data for providing a tone equivalent to a tone to be received by a retina to the retina when the image moves is generated corresponding to the detected motion vector, and the combination of subfields is determined based on the generated new image data.Type: GrantFiled: September 27, 1999Date of Patent: December 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidehiko Kawakami, Hideaki Kawamura, Kazuo Tomida, Yoshio Watanabe, Hiroaki Fukushima, Masaki Tokoi
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Patent number: 6658147Abstract: The invention improves the appearance of freehand drawn lines and shapes in an electronic document by first recognizing freehand drawn lines and shapes and generating a line made up of sequential straight line segments for the freehand drawn line when the line does not form a closed line and generating a multiple straight-line-segment shape when the line forms a closed line. If a multiple segment shape is being reshaped, a basic shape is selected from reference ideal shapes as the basic shape of the multiple segment shape. The basic shape is adjusted to provide a specific shape as an improved shape for the freehand drawn shape. The recognition of the freehand drawn lines and shapes is accomplished by comparing source segments of a source freehand drawn line to a straight line and substituting a straight line segment for a source segment if the deviation between the source segment and the straight line is below a predetermined value.Type: GrantFiled: April 15, 2002Date of Patent: December 2, 2003Assignee: Parascript LLCInventors: Boris Gorbatov, Ilia Lossev
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Patent number: 6636187Abstract: A display has a panel, and first and second electrodes. The first and second electrodes define a matrix of cells on the panel. The second electrodes, which correspond to lines of the cells, are scanned to select the cell lines one by one. The first electrodes are driven to set display data for a selected one of the cell lines. The display also has a sequence setting unit for setting sequences of scanning the second electrodes, and a sequence selection unit for selecting one of the sequences that minimizes the current and power consumption of a first-electrode driver without deteriorating the quality of the displayed images.Type: GrantFiled: October 29, 1998Date of Patent: October 21, 2003Assignee: Fujitsu LimitedInventors: Masaya Tajima, Junichi Okayasu, Kiyoshi Takata, Katsuhiro Ishida, Takashi Fujisaki, Yoshimasa Awata, Nobuyoshi Kondo, Shinsuke Tanaka, Naoki Matsui, Fumitaka Asami
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Patent number: 6611530Abstract: A video communication system that uses multiple streams to carry digital video. The use of multiple streams ensures that errors in one or more of the multiple streams do not prevent reconstruction of remaining ones of the multiple streams. This enables an error free display of the digital video at a reduced frame rate during the loss of a subset of the streams. In addition, the multiple streams provide past and future frames that may be used to recover lost frames and thereby recover the lost stream.Type: GrantFiled: September 21, 1999Date of Patent: August 26, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: John G. Apostolopoulos
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Patent number: 6597402Abstract: An interlaced television signal is derived from an interlaced 625 line, nominally 50 Hz field rate television signal, the derived television signal having perceived reduced line structure and reduced flicker. The field rate and the number of lines of the derived television signal are increased with respect to the field rate and the number of lines of the original television signal, such that perceived flicker and line structure in the derived television signal is reduced. The increase in the field rate and the increase in the number of lines in the derived television signal results in a horizontal scanning rate that does not substantially exceed twice the horizontal scanning rate of the original television signal while minimizing undesirable motion artifacts.Type: GrantFiled: May 10, 2000Date of Patent: July 22, 2003Assignee: Sage, Inc.Inventors: Donald S. Butler, Xu Dong, Jack J. Campbell
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Publication number: 20030086016Abstract: A home entertainment appliance includes a computer system and a television system. A video monitor or television monitor of the home entertainment system shows a sequence of video frames generated in the appliance based upon at least one received sequence of interlaced video fields each containing a number of scan lines. A video system of the appliance receives a first field, temporarily stores the first field in an input buffer, and then in a loop, while video fields are being received, performs various other steps. The other steps include receiving a next field, compensating the field in the input buffer, deinterlacing the received field with the compensated field in the input buffer, temporarily storing the received field, merging the received field and the compensated field into a video frame of the second sequence, and providing the video frame of the second sequence to a subsequent device.Type: ApplicationFiled: December 16, 2002Publication date: May 8, 2003Inventors: Christopher Voltz, Drew S. Johnson
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Patent number: 6560280Abstract: In a video system incoming video having a given frame size is sent over a video transmission system that supports a different frame size. When a transmitting terminal in the transmission system receives the incoming video, the terminal does not scale the video to fit the transmitted frame size. Instead, the video compression encoder only encodes and sends the data associated with the incoming video. The encoder does not encode or send the rest of the standard transmitted frame. At a receiving terminal in the transmission system, all of the received data is decoded. However, because the decoded data will correspond to the original incoming frame size, this data, rather than the entire transmitted frame, is scaled to match the size of the display or the target window.Type: GrantFiled: February 2, 1998Date of Patent: May 6, 2003Assignee: Vcon Ltd.Inventors: Yair Shachar, Yaron Menczel
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Patent number: RE40074Abstract: An interlaced television signal is derived from an interlaced 625 line, nominally 50 Hz field rate television signal, the derived television signal having perceived reduced line structure and reduce flicker. The field rate and the number of lines of the derived television signal are increased with respect to the field rate and the number of lines of the original television signal, such that perceived flicker and line structure in the derived television signal is reduced. The increase in the field rate and the increase in the number of lines in the derived television signal results in a horizontal scanning rate that does not substantially exceed twice the horizontal scanning rate of the original television signal while minimizing undesirable motion artifacts.Type: GrantFiled: July 21, 2005Date of Patent: February 19, 2008Assignee: Genesis Microchip Inc.Inventors: Donald S. Butler, Xu Dong, Jack J. Campbell