Abstract: The present invention relates to a digital retro-directive system and method thereof for receiving incoming signals from a transmitting source by means of at least two antennas and transmitting outgoing signals back, substantially, simultaneously, towards said transmitting source through said at least two antennas irrespective of the location of one antenna with respect to another and without calculating phase differences between said outgoing signals.

Abstract: A deinterlacing apparatus includes a buffer to receive a plurality of consecutive fields of an interlaced video and a field combination module coupled to the buffer to deinterlace the interlaced video in accordance with cadence of the interlaced video. The deinterlacing apparatus also includes a cadence detection module to detect the cadence by (1) causing each of the fields to be combined with its preceding field into a frame and with its subsequent field into another frame to obtain a plurality of combined frames, (2) determining a comb factor of each of the combined frames to obtain a sequence of comb factors of the combined frames, and (3) determining if the sequence of comb factors of the combined frames follows a pre-determined repeating pattern. A cadence detection method is also described.

Abstract: A video input section acquires a video signal formed of a plurality of frames. A frame separator separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals. A plurality of parallel processors perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator. A frame combiner combines the separated video signals on which the plurality of parallel processors have performed the video processing.

Abstract: A method for identifying state of macro block of de-interlacing computing and an image processing apparatus are provided, the method is as follows. A video frame is divided into a plurality of regions, where each of the regions includes a plurality of macro blocks. Then, a basic threshold corresponding to each of the regions is provided according to a position of each of the regions in the video frame, and a first macro block is identified to be a first type macro block or a second type macro block according to the basic threshold corresponding to one of the regions where the first macro block of the macro blocks locates. Then, a corresponding de-interlacing computing step is performed on the first macro block according to an result that the first macro block is identified as the first type macro block or the second type macro block.

Abstract: A method for de-interlacing interlaced video includes receiving a first video field and a second video field of an interlaced video frame, generating a first video frame from the first video field and a first synthesized video field, where video data of the first synthesized video field is based exclusively on video data of the first and second video fields, generating a second video frame from the second video field and a second synthesized video field, where video data of the second synthesized video field is based exclusively on the video data of the first and second video fields, and outputting two de-interlaced video frames for every received interlaced video frame. The first (second) synthesized video field is generated by combining image data from the second (first) video field with image data from corresponding lines of an up-scaled first (second) field generated by a scaler.

Abstract: A video recording device includes: a first identification block that reads video information from a first recording medium in which video information on an analog television broadcast is stored, and identifies the broadcasting format of the read video information; a recording execution block that records the video information, which is read from the first recording medium, in a second recording medium other than the first recording medium; a second identification block that when the video information is recorded in the second recording medium by the recording execution block, identifies the broadcasting format of the video information to be recorded in the second recording medium; and a format decision block that decides whether the broadcasting format identified by the second identification block agrees with the broadcasting format identified by the first identification block.

Abstract: A field pair correlation acquisition part obtains a correlation for six or more fields which are continuous in time series for each field pair formed of two adjacent fields having the same attribute. A first determination part determines an input image as a 2:2 pull-down image based on a determination condition, the determination condition being that a pattern in which the correlation of each of the field pairs of one attribute changes along with a time direction matches a pattern in which the correlation of each of the field pairs of the other attribute changes along with the time direction.

Abstract: An image processing method for converting the frame frequency of a video signal includes a first step for subjecting a video signal having a first frame-frequency to three-times-repeat output and two-times-repeat output of a frame to convert the video signal having the first frame-frequency into a video signal having a second frame-frequency holding a relation of 2:5 as to the first frame-frequency; and a second step for converting the video signal having said second frame-frequency converted in said first step into a video signal having a third frame-frequency holding a relation of 1000:1001 or 1001:1000 as to the second frame-frequency, wherein the second step performs the conversion such that the difference of the number of frames after conversion becomes one or less between a frame group based on the three-times-repeat output frame in the first step, and a frame group based on the two-times-repeat output frame in the first step.

Abstract: To provide a three-dimensional Y/C separating circuit that has a high responsibility to a motion in a video signal and can reduce a memory capacity, a three-dimensional Y/C separating circuit has a 2-frame memory 14 that delays a color signal by an inversion period thereof to produce a delayed composite video signal, a luminance motion detecting part that produces a first frame correlation signal by a subtraction processing between the delayed composite video signal and a composite video signal, an adding circuit 23 that produces a mixed video signal by an addition processing between the delayed composite video signal and the composite video signal, a frame memory 24 that delays the mixed video signal by one frame period, a subtracting circuit 25 that produces a second frame correlation signal by a subtraction processing between the mixed video signal and the mixed video signal delayed by one frame period, a determining circuit 26 that determines a motion from the first and second frame correlation signals an

Abstract: A 2:3 pulldown sequence detecting system includes a history data table that stores a correspondence between each input field and a determination result of whether each input field is a repeated field and a threshold value table that stores threshold values. The system compares pixels of each (or a first) field that forms an interlaced image with pixels of a third field one frame before the first field to calculate a difference absolute value, uses the threshold values to determine a distribution bias of the difference absolute value, detects, from the interlaced image, a repeated field candidate that occurs once in a five field cycle and fields other than the repeated field, and determines, based on a regularity of repeated field occurrence, whether each repeated field candidate is the repeated field. If any repeated field candidate is not the repeated field, the system controls the threshold values.

Abstract: A method for converting frames that can display smooth moving images is provided. A memory (16) to which image data of frames in the NTSC format is written is provided. A memory controller (14) for retrieving image data of an odd field and an even field from the memory (16) every odd field period and even field period in the frame period of the PAL format is provided. An interpolating circuit (76) is provided. The interpolating circuit (76) mixes the image data of the odd field retrieved by the memory controller (14) and image data of a next odd field at a predetermined ratio to output as image data of an odd field in the frame period of the PAL format, and mixes the retrieved image data of the even field and image data of a next even field at a predetermined ratio to output as image data of an even field in the frame period of the PAL format. A coefficient-generating circuit (73) for changing the mixing ratios in the interpolating circuit (76) every field period of the PAL format is provided.

Abstract: To provide a three-dimensional Y/C separating circuit that has a high responsibility to a motion in a video signal and can reduce a memory capacity, a three-dimensional Y/C separating circuit has a 2-frame memory 14 that delays a color signal by an inversion period thereof to produce a delayed composite video signal, a luminance motion detecting part that produces a first frame correlation signal by a subtraction processing between the delayed composite video signal and a composite video signal, an adding circuit 23 that produces a mixed video signal by an addition processing between the delayed composite video signal and the composite video signal, a frame memory 24 that delays the mixed video signal by one frame period, a subtracting circuit 25 that produces a second frame correlation signal by a subtraction processing between the mixed video signal and the mixed video signal delayed by one frame period, a determining circuit 26 that determines a motion from the first and second frame correlation signals an

Abstract: A circuit for converting the format of image data, the motion of the image data being smooth, includes a memory (16) to which moving image data in the NTSC format is written; a memory controller (14) retrieving respective signals, from the memory (16), required for producing image data of an odd field and an even field in the PAL format; line-interpolating circuits (73) and (74) converting retrieved image data into first image data and second image, respectively, both image data having the line frequency of the PAL format; a frame-interpolating circuit (75) outputting the image data of the odd field in the PAL format by mixing image data of the odd field of the first image data and image data of the odd field of the second image data at a predetermined mixing ratio, and outputting the image data of the even field in the PAL format by mixing image data of the even field of the first image data and image data of the even field of the second image data at a predetermined mixing ratio; and a coefficient-generatin

Abstract: Device and method for converting a format of a video signal in a digital TV receiver is provided. Format conversion can be carried out at one chip of a format converting device, inclusive of conversion of resolution, frame rate, scanning method, aspect ratio, color space, chroma format, and gamma correction. Therefore, the digital TV receiver is made to convert a wide range of video signals inclusive of, not only a digital TV broadcasting signal, but also analog TV broadcasting signal, and computer video signal, at one chip of system block. Moreover, the digital TV receiver is made to provide a variety of standards of format converted video signals, not only to the connected display, but also to other general video signal processing devices.

Abstract: An apparatus and method to delay a field of video by one row in a two field frame to reduce DC build-up or stick caused by textual image.

Abstract: A digital camera with video input is disclosed. An image sensor is provided to capture an image and convert the captured image into R/G/B image signals the are processed by a video signal processing unit for being converted into pixel data having a first format. A TV decoder converts input analog video signals into pixel data having a second format. A scaling unit performs aspect ratio processing and zoom/pan function to pixel data. A TV interface unit converts pixel data having the second format into pixel data having the first format for being selectively output to the scaling unit directly and output to the scaling unit after transferring to the video signal processing unit for performing edge enhancement. A compressing and storage unit performs compress operation to the pixel data output from the video signal processing unit and the scaling unit. An USB unit converts pixel data after being compressed into serial data for output.

Abstract: In a method and apparatus for displaying resized pictures on an interlaced target display system, the contents of an input video source are initially read and decoded to obtain original input picture data and title format information that indicates scan format of the original input picture data. According to the scan format of the original picture data and the identified television system specification of the interlaced target display system, a resizing operation is then performed to resize the original input picture data and obtain resized frames having a frame size sufficient for division into even and odd fields with field size characteristics that comply with the television system specification of the interlaced target display system.

Abstract: A display has a panel, and first and second electrodes. The first and second electrodes define a matrix of cells on the panel. The second electrodes, which correspond to lines of the cells, are scanned to select the cell lines one by one. The first electrodes are driven to set display data for a selected one of the cell lines. The display also has a sequence setting unit for setting sequences of scanning the second electrodes, and a sequence selection unit for selecting one of the sequences that minimizes the current and power consumption of a first-electrode driver without deteriorating the quality of the displayed images.

Abstract: An image processing apparatus includes a decoding circuit block decoding a coded image input signal specified by NTSC system with a frame rate of the NTSC system and writing a decoded image signal in an image memory as image data, and a display-image producing circuit block producing a display image data by reading the image data from the image memory with a frame rate specified by PAL system, thereby achieving the frame rate transformation from the NTSC system to PAL system, and at this time, carrying out the skipping for display at every one extent field.

Abstract: A color system determination circuit for use with an input video signal having a frequency component is disclosed. The circuit includes a color trap filter for attenuating the frequency component in the input video signal with the color trap filter providing a color burst output signal, a comparator for comparing the color burst output signal of the color trap filter and the frequency component of the input video signal, a maximum value detector which receives the color burst output signal of the color trap filter and a color burst sampling signal and detects a maximum value of the color burst output signal of the color trap filter during a period of the color burst sampling signal, and another maximum value detector which receives the video signal and the color burst sampling signal and detects a maximum value of the video signal during the period of the color burst sampling signal.

Abstract: A video signal processor includes a decoder supplied with a playback signal formatted in accordance with the standards of National Television System Committee and producing a digital video signal with a vertical synchronous frequency and a horizontal synchronous frequency satisfying a standard of Phase Alternation by Line Color Television System, an encoder connected to said decoder and producing said analog video signal with a color sub-carrier frequency satisfying another standard of said Phase Alternation by Line Color Television System and a signal generator supplying a clock signal and a color carrier signal regulating the horizontal synchronous frequency and the color sub-carrier frequency to the relation expressed asfsc={(1135/4)+(1/521)}f.sub.Hwhere fsc is said color sub-carrier frequency and f.sub.H is said horizontal synchronous frequency, and a moving picture reproduced from the analog video signal is free from color difference due to a dot crawling interference.

Abstract: By selecting the number of apertures per vertical row in the shadow mask of a color cathode ray tube to be in the range between 615 and 650, such a cathode ray tube can be used both in a PAL, an NTSC system and a MUSE system without the occurrence of disturbing Moire effects. In a second embodiment the number of apertures per row ranges between 425 and 450.

Abstract: An interpolation method and apparatus for converting pixels according to image formats, prevents deterioration of picture quality by performing a bilinear conversion which uses a larger number of pixels than does the conventional interpolation method which uses only two pixels. When a ratio between an interpolation point and a vertical line of unconverted pixels is .DELTA.1, a ratio between the interpolation point and a horizontal line of unconverted pixels is .DELTA.2, and eight unconverted pixels A1-A4 and B1-B4 on two lines adjacent to the interpolation position are used along with a coupling coefficient .alpha., a final interpolation signal I is generated according to the following equations:I1=(1-.DELTA.1)(1-.DELTA.2)A1+(1-.DELTA.1).DELTA.2A2+.DELTA.1(1-.DELTA.2)A3 +.DELTA.1.DELTA.2A4;I2=(1-.DELTA.1)(1-.DELTA.2)B1+(1-.DELTA.1).DELTA.2B2+.DELTA.1(1-.DELTA.2)B3 +.DELTA.1.DELTA.2B4; andI=.alpha.I1+(1-.alpha.)I2.

Abstract: To avoid color defects in the motion-compensated luminance signal, which defects occur in non-motion-compensative time-interpolation of the color signal, a method includes the steps of generating a second color difference signal from a first color difference signal supplied at a first field repetition frequency by way of field repetition, the second color difference signal having a second field repetition frequency which is doubled with respect to the first field repetition frequency, generating a third, time-averaged color difference signal from the second color difference signal by time-averaging of two consecutive fields, generating a fourth, spatially high-resolution color difference signal by a spatially high-resolution interpolation of two consecutive fields from the second color difference signal, forming a fifth color difference signal to be supplied as a linear combination of the third and the fourth color difference signals by means of coefficients which are complementary with respect to a constant,

Abstract: An NTSC/PAL video signal conversion apparatus employing a ITU-R BT.

Abstract: A scanning line converting apparatus for converting between NTSC and PAL formats includes a plurality of line memories, an arithmetic circuit and a picture memory. Switches in the lines connecting these elements permits the order of connection to be shifted between first and second states. When converting from the PAL system to the NTSC system, 5 lines are formed by varying the mutual signal ration of 2 lines for every 6 lines, while, when converting from the NTSC system to the PAL system, 6 lines are formed by varying the ratio of 2 lines for every 5 lines, thereby making it possible to convert the lines of one field of different broadcasting methods when actually scanning the picture tube. The ratios used in computations performed by the arithmetic circuit are related to horizontal synchronizing signals and to vertical blanking signals, while they are also related to constants which are furnished by a percent block. A method for converting between different broadcasting formats is also described.

Abstract: A digital video signal converting apparatus for converting a first digital video signal having a first resolution to a second digital video signal having a second resolution higher than the first resolution, comprises; block segmentation circuit for converting the first digital video signal into a block format, memory having a mapping table stored therein and having address terminals to which the first digital video signal in a block format is supplied and output terminals from which the second digital video signal in block format is output, and block separation circuit for converting the second digital video signal in a block format into a digital video signal in a raster scan order, wherein the mapping table in the memory is generated by training utilizing a plurality of images the training step being performed by generating first and second digital video signal corresponding to each of the plurality of images, converting each of the first and second digital video signals into a block format, and selecting

Abstract: The system for converting a 50 Hz, 312.5 lines per field video composite input signal into a 60 Hz, 262.5 lines per field video composite output signal includes an A/D converter for converting the entire video input signal into a digital video composite signal. The digital video composite signal is stored in a dual port, FIFO, random access field memory. Write cycle commands are generated by gate array logic (GAL) circuits based upon a color subcarrier signal typical of the 60 Hz, 262.5 line output signal, and a horizontal and vertical field signal based upon the 50 Hz input signal. Read commands for the RAM are generated by the GAL based upon an independently generated 60 cycle (Hz) signal. The GAL also deletes between 15 or 30 video lines from the top of each field based upon a timing relationship from a vertical blanking signal, or in the case of the VCR, the head switch signal and a line count generated from the horizontal sync signal of the video composite input signal.

Abstract: A color television system conversion apparatus converts a television signal of a first television system into a television signal of a second television system by converting the carrier frequency of the chrominance signal of the first television system into the carrier frequency of the second television system. The carrier frequency converted chrominance signal is converted into a digital signal in response to the clock of the carrier frequency of the second television system. The digital chrominance signal is digitally decoded into two color difference signals of the first color television system. The two decoded color difference signals are converted so as to have the number of lines and the number of fields of the second television system through extraction and interpolation processes. The converted color difference signals are encoded digitally into a luminance signal of the second television system.