Abstract: A signal processing device includes an A-D converter and a controller. The A-D converter converts an analog signal to a digital signal in which portions where the amplitude exceeds a predetermined range are clipped. A counter of the controller calculates, for the digital signal, a number of clipped samples for each predetermined number of period samples. A frequency converter performs frequency conversion of the digital signal. An LPF removes high frequency components of the digital signal. A rate converter converts a sampling rate of the A-D converter. A digital amplifier amplifies and outputs the digital signal. An amplification factor adjuster multiplies a preset amplification factor of the digital amplifier by an amplification factor adjustment coefficient based on a ratio of the number of regular samples to the number of period samples, to adjust the amplification factor.

Abstract: An impedance readout circuit receives an input signal from a pixel, or an array of pixels. The circuit includes an amplifier to amplify the input signal and detects a DC component of the input signal. The circuit establishes an AC sampling voltage at the output of the amplifier enabling a filter of the circuit to determine an AC current component of the amplifier output. The AC current component is inversely proportional to the output impedance of the pixel.

Abstract: An image processing apparatus includes: a normal interpolated image generation unit to generate an image that is interpolated between a plurality of original images reproduced along time series, the image being a normal interpolated image, based on each of the plurality of original images; a high-frequency area extraction unit to extract a high-frequency area having a spatial frequency higher than a predetermined value in each of the plurality of original images; a high-frequency area interpolated image generation unit to generate an image that is interpolated between the plurality of original images, the image being a high-frequency area interpolated image, based on a change in position of the high-frequency area along with an elapse of time on the time series and on each of the plurality of original images; and a combination unit to execute combining processing to combine the normal interpolated image and the high-frequency area interpolated image.

Abstract: To provide a video signal processing apparatus capable of generating video signals that enable displaying and recording of a high-quality picture. A video signal processing apparatus according to an embodiment of the present invention includes a decoder decoding an input TS to generate a video signal having a field frequency fv of 60 Hz or a video signal having a field frequency fv of 59.94 Hz, and a converter converting the respective video signals into NTSC video signals having a color subcarrier the phase of which is inverted for each frame.

Abstract: A system and method transmits data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: The present invention provides a method and a device that use two different clock frequencies to encode video. The method and device would allow videos taken by an electronic device with input clock frequency at 26 MHz, to be encoded for playing back on TV. An exemplary method of using a 26 MHz clock to encode luminance and chrominance data of digital video data is provided. The method includes re-sampling the luminance and the chrominance data to extend a first number of data per line to a second number of data per line, and modulating the re-sampled chrominance data in the input clock domain by color subcarrier signals driven by an input clock. The method also includes combining the modulated re-sampled chrominance data and the re-sampled luminance data, and converting the combined modulated re-sampled chrominance data and re-sampled luminance data into analog signals. In one embodiment, the first number is 1652 and the second number is 1652 4/9.

Abstract: The present invention provides a method and a device that use two different clock frequencies to encode video. The method and device would allow videos taken by an electronic device with input clock frequency other than 27 MHz, to be encoded by using two clock frequencies for playing back on TV. An exemplary method capable of using two clock frequencies to encode digital video data captured by a video-capturing device is provided. The method includes re-sampling luminance and chrominance data in a re-sampling module to convert the luminance and the chrominance data in a 27 MHz clock domain to be in an input clock domain other than 27 MHz of an input clock of the video-capturing device. The method also includes modulating re-sampled chrominance data in the input clock domain by color subcarrier signals driven by the input clock.

Abstract: The present invention relates to a device for digital display of a video image using time-division modulation. This device is intended to display a video image during a video frame comprising a plurality of consecutive subfields distributed within at least two separate identical time segments. According to the invention, the pixels of the video image change state at most once during each time segment and the video image to be displayed is saved in the image memory in the form of information identifying, for each subfield, the pixels changing state.

Abstract: Digital broadcasting receiver, and method for compensating a color reproduction error therein, the digital broadcasting receiver including a channel decoder, a TP part for demultiplexing a TP stream from the channel decoder for being provided with a PCR (Program Clock Reference), and receiving a receiver side STC (System Time Clock), and providing a PCR jitter which is a difference between the PCR and an STC value, an STC compensating part for providing the STC value to the TP part from a system clock, and varying the system clock so that the PCR value and the STC value are identical, to generate a reference system clock in which the PCR jitter value becomes ‘0’, a decoder for receiving the reference system clock from the STC compensating part, and decoding a received picture, a display clock generator for providing a display clock generated by receiving the reference system clock as singular system clock, a video format and display processor for receiving the reference system clock and the display clock, and

Abstract: HDTV and NTSC compatible image communication is done in a single NTSC channel bandwidth. Luminance and chrominance image data of a scene to be transmitted is obtained. The image data is quantized and digitally encoded to form digital image data in HDTV transmission format having low-resolution terms and high-resolution terms. The low-resolution digital image data terms are transformed to a voltage signal corresponding to NTSC color subcarrier modulation with retrace blanking and color bursts to form a NTSC video signal. The NTSC video signal and the high-resolution digital image data terms are then transmitted in a composite NTSC video transmission. In a NTSC receiver, the NTSC video signal is processed directly to display the scene. In a HDTV receiver, the NTSC video signal is processed to invert the color subcarrier modulation to recover the low-resolution terms, where the recovered low-resolution terms are combined with the high-resolution terms to reconstruct the scene in a high definition format.

Abstract: One of an output picture signal with a field double speed of AABB type and an output picture signal with a field double speed of ABAB type is selectively generated with selection signals SL1 and SL2. In the AABB type, among first, second, third, and fourth output fields, the vertical pixel position of the second output field is the same as the vertical pixel position of the first output field. In addition, the vertical pixel position of the fourth output field is the same as the vertical pixel position of the third output field. In the ABAB type, among first, second, third, and fourth output fields that are chronologically successive, the vertical pixel position of the second output field deviates from the vertical pixel position of the first output field. In addition, the vertical pixel position of the third output field deviates from the vertical pixel position of the second output field.

Abstract: A frequency converter is disclosed, which improves processing time and reduces hardware costs, in converting input data sampled at a first frequency into output data compatible with a system operating at a second frequency. The frequency converter has first and second coefficient generators for calculating first and second coefficient values, respectively. The frequency converter uses an interpolator for interpolating input data using the first and second coefficient values into the output data. In addition, a dual-port memory stores the output data in accordance with the first frequency and outputs the stored data in accordance with the second frequency.

Abstract: A color system determination circuit for use with an input video signal having a frequency component is disclosed. The circuit includes a color trap filter for attenuating the frequency component in the input video signal with the color trap filter providing a color burst output signal, a comparator for comparing the color burst output signal of the color trap filter and the frequency component of the input video signal, a maximum value detector which receives the color burst output signal of the color trap filter and a color burst sampling signal and detects a maximum value of the color burst output signal of the color trap filter during a period of the color burst sampling signal, and another maximum value detector which receives the video signal and the color burst sampling signal and detects a maximum value of the video signal during the period of the color burst sampling signal.

Abstract: For purposes of simple construction and universal application, a circuit arrangement for frequency conversion of a color signal to a second carrier frequency, this color signal being present in picture lines and including a color burst and a chrominance information signal modulated on a chrominance sub-carrier of the first carrier frequency, the circuit arrangement being switchable in a mode for conjugate-complex formation in which it generates an output signal in which, additionally to the frequency conversion, the color signal has a phase position in accordance with the PAL standard, which alternates from picture line to picture line, and which color signal is present in a conjugate-complex form in every second picture line, is characterized in thatthe color signal modulated on the first carrier frequency is converted to a third carrier frequency by a first mixer (1), this third carrier frequency being higher than the first and lower than the second carrier frequency,a second mixer (20) is provided by which

Abstract: A received 4-2-0 format, 2-1 interlaced digital component video signal is upconverted to a 4-2-2 format, 2-1 interlaced digital component video signal and a vertical chrominance bandwidth expansion enhancement signal is combined with the chrominance components in order to more closely simulate the wider bandwidth vertical chrominance resolution of the original 4:2:2 format signal from which the 4:2:0 format signal was derived. In a first embodiment, the vertical chrominance enhancement signal is derived from vertical transitions in the luminance component of the 4:2:0 format signal. In a second embodiment, the vertical chrominance enhancement signal is derived from vertical transitions in the luminance component of the 4:2:0 format signal when such vertical transitions are present and, in the absence of a luminance transition, the vertical chrominance enhancement signal is derived from the sampling-rate-reduced chrominance components of the 4:2:0 format signal.

Abstract: A system and method for eliminating flicker in an interlaced video-display image using an input-video processor, a feature-video processor, a frame buffer, an RGB-output processor, an output-video processor, a control processor, and a synchronized-clock doubler. An input video signal is processed as processed component video information and written to a video memory at a horizontal-scan rate and a vertical-scan rate. Based on the input video signal, a vertical-scan synchronization pulse and a horizontal-scan synchronization pulse are generated and then harmonically doubled. The processed component video information is read from the video memory, responsive to the harmonically doubled synchronization pulses, at a harmonically doubled horizontal-scan rate and a harmonically doubled vertical-scan rate, reading in an interlaced format, with each frame being contiguously read twice in a proper odd-even order as when normally read to generate four fields of video information per frame which may be interlaced.

Abstract: A buffer occupancy control method is provided in order to properly control a buffer occupancy of a decoder. The intial time delay indicated in data received by the buffer is extended and the capacity of the buffer is expanded according to the additional amount of data inserted during the extended initial time delay, thereby preventing the buffer from overflowing and underflowing. In particular, when a bitstream encoded with a frame rate of 24 Hz is decoded according to a display field frequency of 60 Hz, excellent images can be regenerated without requiring additional components.

Abstract: An image-processor system for compensating for accumulated phase-and-gain errors incurred during transmission of a video signal over a communications channel. The image-processor system comprises an initial-video processor, an input-video processor, a feature-video processor, a frame buffer, an RGB-output processor, an output-video processor, and a control processor. The initial-video processor generates a composite video signal. The input-video processor converts the composite video signal into digital-component signal information. The feature-video processor processes the digital-component signal information as processed component video information. The frame buffer re-establishes broadcast timing standards in the processed component video information to generate time-base corrected digital information. The RGB-output processor decodes the time-base corrected digital information into RGB analog and digital outputs. The analog RGB outputs are output directly.