Abstract: A method for deinterlacing interlaced video using a graphics processor includes receiving at least one instruction for a 2D/3D engine to facilitate creation of an adaptively deinterlaced frame image from at least a first interlaced field. The method also includes performing, by the 2D/3D engine, at least a portion of adaptive deinterlacing based on at least the first interlaced field, in response to the at least one instruction to produce at least a portion of the adaptively deinterlaced frame image. Once the information is deinterlaced, the method includes retrieving, by a graphics processor display engine, the stored adaptively deinterlaced frame image generated by the 2D/3D engine, for display on one or more display devices. The method also includes issuing 2D/3D instructions to the 2D/3D engine to carry out deinterlacing of lines of video data from interlaced fields. This may be done, for example, by another processing device, such as a host CPU, or any other suitable processing device.

Abstract: When an input signal is signal-converted and is output, the copyright of a signal to be signal-converted is reliably protected. In an additional information detection/determination section, digital watermark information, CGMS information, etc., which are superposed on or added to an input luminance signal, are detected, and it is determined whether or not a signal which is to be signal-converted in a signal conversion section should be output on the basis of the detected additional information. When additional information for prohibiting or limiting copying has been superposed on or added to the input luminance signal, a switching circuit for output control is turned off so that the signal which is signal-converted in the signal conversion section is not output to the outside.

Abstract: A method for detecting an edge and generating an interpolated edge pixel at a target pixel position between two lines of an interlace scan image first determines gradient intensities in the horizontal and vertical directions and then calculates the angle of the edge by comparing the gradient intensities. The interpolated pixel value is calculated from samples in the interlace scan image that lie along the identified angle and are proximate to the target pixel position. The method represents the gradient strengths and the difference between them as bit strings; locates the most significant non-zero bit in the larger gradient value; divides the value of the corresponding bit position in the difference string, and a predetermined number of following positions, by increasing powers of 2; sums the results; subtracts the sum from 1.0 and uses the inverse tangent function to calculate the angle of the edge.

Abstract: A scan line conversion circuit is provided for simultaneously carrying out three-dimensional motion adaptive sequential scan conversion and scan line conversion. The scan line conversion circuit comprises an FIFO memory into which the video signal is input; a sequential scan conversion circuit section for converting an interlace signal sent from the FIFO memory to a non-interlace signal; an address generator into which a vertical enlargement ratio and a synchronous signal are input to generate an address as a spatial position after scan line conversion; a memory control unit for generating a memory control signal based on the address sent from the address generator; a coefficient generator for generating a coefficient for performing scan line conversion; a plurality of first multipliers for multiplying sequentially scan converted signals, sent from the sequential scan conversion circuit section, by respective coefficients; and an adder for adding signals output from the multipliers together.

Abstract: A video signal interpolation can adapt an image of input video signal to voluntary aspect ratios widely. The invention also allows a display device to uniformly line-sequential scan and uses at least two line-memories (LM1, LM2) which are applied with an input digital video signal and controls writing and reading for these line-memories to generate a video signal subjected to vertical interpolation from a reading output of the line-memories. In the control, any one of the line-memories are circularly selected, and a sample sequence of the input digital video signal is sequentially written into the selected line-memory at its sample rate while sequentially reading out samples of the written sequence at a constant rate which is higher than the sample rate and which is according to a desired ratio of interpolation (vertical expansion ratio), wherein, when one of the line-memories is in writing operation, the other one of the line-memories is repeatedly read out.

Abstract: A class code of a subject pixel of an HD signal is obtained from pixel data of a class tap extracted from an SD signal. In a memory bank, coefficient data for a generating equation, including parameters for adjusting image quality, for generating elements of a summation matrix for obtaining coefficient data for an estimate equation are stored on a class basis. A summation matrix is generated in accordance with the coefficient data stored in the memory bank and the values of the parameters as specified by a user operation, generating coefficient data for the estimate equation for each class in accordance with the values of the parameters, which is stored in a memory. A calculation circuit calculates pixel data of the subject pixel of the HD signal by the estimate equation from pixel data of the prediction tap extracted from the SD signal and from coefficient data associated with the class code, supplied from the memory.

Abstract: Moving pictures are reproduced from a stored moving-picture signal and output at a set reproduction speed. The stored moving-picture signal is reproduced in accordance with the set reproduction speed to obtain first interlaced pictures. The first interlaced pictures are converted to obtain first progressive pictures. Moving pictures to be displayed are selected from the first progressive pictures per frame in accordance with the set reproduction speed to obtain second progressive pictures. Scanning lines of the second progressive pictures are decimated so that the number of remaining scanning lines of the second progressive pictures after decimation is equal to the number of scanning lines of interlaced pictures to be displayed, thus outputting second interlaced pictures. The first interlaced pictures are output when the set reproduction speed is the first reproduction speed whereas the second interlaced pictures are output when the set reproduction speed is the second reproduction speed.

Abstract: To enable a satisfactory suppression of overemphasized component after converting the number of scanning lines of video signal, when the video signal is converted in the number of scanning lines and a high-frequency component at least in a vertical direction of the converted video signal is emphasized, signals delayed by a plurality of stages of time equal to or more than a time required for converting the number of scanning lines are obtained by a delay circuit 18, and an appropriate delay signal is selected from among the plurality of delay signals by a selection circuit 19. The selected delay signal is compared with the emphasized video signal in emphasized-component detector circuits 16a, 16b and the overemphasized component is detected. Processing to suppress the emphasis is performed by suppressor circuits 13a, 13b with respect to a portion where the overemphasized signal component is detected.

Abstract: Errors in interpolation when using diagonal interpolation can be reduced, thereby high-quality intra-field interpolation can be achieved. A further upper data line (41) and an upper data line (42) are inputted into an upper diagonal correlation detection portion (21), and the upper data line (42) and a lower data line (43) are inputted into a lower diagonal correlation detection portion (22). The lower diagonal correlation detection portion (22) determines correlation of pixels on actual data lines above and below an interpolation point in a left diagonal direction, a central direction and a right diagonal direction around the interpolation point. The upper diagonal correlation detection portion (21) determines correlation of pixels on actual data lines above and below an auxiliary interpolation point, which is secondarily set, in a left diagonal direction, a central direction and a right diagonal direction around, for example, the auxiliary interpolation point.

Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Abstract: A method for line average de-interlacing decodes a picture to form macro blocks (MBs), calculates line average values to form a threshold, produces de-interlacing flags by comparing the line average values and the threshold, realizes Temporal Extension action and performs Devour action. The Temporal Extension action determines if the current de-interlace flag is set as WEAVE, determines if the flags in the same position in other flag buffers are set as BOB and sets the de-interlace flags as BOB2. The Devour action determines if the de-interlace flag is BOB. If positive, it calculates the amount of BOB data within a predetermined area around the current MB, determines if the result is smaller than the BOB threshold and sets the de-interlace flag as WEAVE. Otherwise, it calculates the amount of the WEAVE data, determines if the result is smaller than the WEAVE threshold and sets the de-interlace flag as BOB2.

Abstract: An information signal processor that is well suitable for use in conversion of an SD signal into an HD signal. The pixel data set corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets and values of picture quality adjusting parameters h and v. A tap selection circuit selectively extracts the data sets xi from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal using the data sets xi and the coefficient data sets Wi. It is thus possible to save on the storage capacity of the memory.

Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Abstract: This specification discloses a method that uses three-dimensional image interpolation algorithm implemented in an image player to solve the problem of frame rate conversions between output contents and the image player. It aims to achieve high resolutions and high frame rates. The disclosed method adjusts the frame resolution and frame rate of the received image data according to the playing format of the image player. That is, the pixel values contained in a frame are interpolated to generate several interpolated pixel values in order to fit with the frame resolution. The interpolated frame is then stored. The next two consecutive frames are further extracted. The central position is determined according to the frame playing frequency. The corresponding pixel values of the two consecutive frames are used to produce several interpolated pixel values. The interpolated pixel values form an interpolated frame, which is then saved.

Abstract: Disclosed is a video signal processing apparatus comprising a plurality of line memories to which in sequence input video signal data is written on a line-by-line basis; a timing controller for controlling a timing to write video signal data to the plurality of line memories and a timing to read video signal data from the plurality of line memories; a computation output portion for computing video signal data read from the plurality of line memories and outputting video signal data differing in resolution which is determined by a pixel count in the horizontal direction and a line count in the vertical direction; and a line controller which vary the pixel count in specified lines of video signal data obtained from the computation output portion, depending on a conversion rate of the video signal data resolution.

Abstract: A data processing apparatus is capable of executing a plurality of signal processes. The data processing apparatus switches processes of a pre-processing portion, a data processing portion, and a post-processing portion with a control signal supplied from a function controlling portion corresponding to a command supplied from the outside. Thus, the data processing apparatus executes for example processes for increasing the resolution, generating a picture dedicated for a right eye and a picture dedicated for a left eye, generating a luminance signal and color difference signals, changing the aspect ratio, generating pictures having difference resolutions, and converting the frame rate for input data corresponding to a request and outputs picture data generated as the processed result to an external device (for example, a displaying device and a record and reproduction device).

Abstract: An output pixel datum is produced from input pixel data by a method wherein the brightness levels of several input pixels closely associated coordinate-wise with the output pixel, are examined to determine whether a relatively less complex graphics-optimized scaling procedure, or a relatively more sophisticated video-optimized scaling procedure, should be carried out. In the second case, directional interpolation is performed with a plurality of directions, e.g., being considered to determine the direction of minimum brightness level gradient. A plurality of intermediate pixels, e.g., four, are produced, which are aligned perpendicularly to the minimum brightness level gradient direction, their brightness levels being determined from relevant input pixels using linear interpolation. The output pixel brightness level is determined from the intermediate pixels through the use of an appropriate filtering technique, e.g., polyphase FIR filtering.

Abstract: A video input processor is provided to process different input video format, including RGB, RGB Bayer, YUV 4:2:2 interlaced and progressive video data. The video input processor also uses an advanced algorithm to efficiently convert video data in RGB color space to YUV color space. The video input processor further enables multi-functions such as video image scaling, video image filtering before the video data are output for further video compression.

Abstract: The invention relates to a method for interpolating a pixel from an intermediate line of a first field of a sequence of interlaced fields.

Abstract: An image conversion unit (100) for converting an input image into an output image includes a first computing device (104) for computing a first weighted sum of a first group of pixel values, the first group of pixel values corresponding to pixels of the input image; a second computing device (102) for computing a second weighted sum of a second group of interpolated values, the second group of interpolated values being computed by interpolation for spatial locations which are not present at the sampling grid of the input image; a combining device (106) for computing a third sum by combining the first weighted sum and the second weighted sum; and a clipping device (108) for clipping the third sum between a minimum value and a maximum value, the minimum value and the maximum value being derived from pixel values of the input image.

Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Abstract: Provided is a progressive scan method used in a display using adaptive edge interpolation. According to the progressive scan method, a final edge direction that satisfies a first edge-determination condition and a second edge-determination condition is detected by performing interpolation for 7×3 pixel windows, using code determination and a comparison of a standard deviation based on differences between luminances of pixel data divided by an edge boundary. As a result, directional edge interpolation is carried out in a region of a low gradient below 45° and to 27° at the minimum, and simple intra-field linear interpolation can be performed in a high-frequency texture region. Subsequently, it is possible to remove high-frequency noise introduced in edge dependent interpolation or unnatural screen display due to zigzagged edges, thereby improving the quality of a display.

Abstract: A double-rate signal achieved by subjecting a video signal to double-rate conversion is supplied to a scan line number converter. In the converter, the portion of the effective scan lines of the double-rate signal is written into a frame memory on the basis of a signal achieved by multiplying horizontal and vertical synchronous signals based on the double-rate signal. In the effective scan line section of HDTV signal, the video signal written in the frame memory is read out on the basis of horizontal and vertical reference signals based on'the HDTV signal. Out of the effective scan line section of the HDTV signal, a pedestal level signal written in a memory is read out on the basis of the horizontal and vertical reference signals based on the HDTV signal, thereby achieving HDTV signal whose vertical scan line number is equal to 1125 lines.

Abstract: The present invention provides an on-screen graphics (OSD) subsystem for overlaying OSD graphic images onto analog or digital video source signals. The OSD system has a video graphics bypass path and graphics bypass switch for directing an analog video channel around the OSD subsystem during time intervals when the OSD subsystem is not required to insert graphics into the source signal.

Abstract: The scan conversion apparatus of the present invention comprises a video signal discriminating circuit for discriminating the kind of input video signal based on an interlaced scanning system; a telecine scan conversion circuit for converting input video signal into a video signal based on a progressive scanning system by processing suited for telecine video signal; a scan conversion circuit for converting input video signal into a video signal based on a progressive scanning system suited for signals other than telecine video signal; and a selector which selects and delivers the output from the telecine scan conversion circuit and the output from the scan conversion circuit in accordance with the result of discrimination executed by the video signal discriminating circuit.

Abstract: A method of controlling brightness of a user-selected area on a monitor screen is disclosed. First, a starting point of a topmost line of a displayed image is determined as a new reference point. Then a line pattern being included in one of image lines of the displayed image is detected. The pattern includes an indicator whose ends are horizontally aligned with vertical edges of the user-selected area. Next, horizontal distances of the vertical edges with respect to the reference point, and a highlight area is identified using the measured horizontal distances. Finally, a brightness gain of the identified highlight area is amplified.

Abstract: An image data conversion processing device including an issue unit, plural line storing units, and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the number of lines of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.

Abstract: The present invention relates to interpolating a pixel in an image that includes a number of pixels arrayed in matrix-like fashion, to each of which a video information value is assigned, in which method a gradient for the video information value is determined at, at least, a first and a second pixel adjacent to the pixel to be interpolated and, in the formation of the interpolated video information value, a greater weight is accorded to the video information value of the adjacent pixels whose associated gradient is smaller.

Abstract: A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed.

Abstract: A method and computer program product for reformatting at least a portion of a digital source image. The digital source image has a number of pixels defining an original format which is to be converted to a destination image in a new format having a number of pixels. The number of pixels of the new format is greater than the number of pixels in the original format. A gradient is estimated at a point within a window which encompasses a plurality of intensity values from the source image. A polynomial is then used to determine a value for the point in the new format within the window. The polynomial is based in part upon the gradient. Values are then determined for additional points in the destination image by selecting a new window and repeating the acts of estimating a gradient and using a polynomial to determine a value.

Abstract: The arrangements and procedures of this invention adaptively process video data. Specifically, at least first and second fields of an interlaced frame are deinterlaced to form intermediate progressive first and second frames. The first intermediate progressive frame includes scanlines of a first temporal instant. The second intermediate progressive frame includes scanlines of a second temporal instant. The first and second temporal instants are different from one another. The first and second intermediate progressive frames are independently resampled to form respective first and second resampled frames. Scanlines from the first and second resampled frames are interleaved to generate a resampled interlaced frame.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case where a SD signal is converted into a HD signal. A space class and a movement class are detected from the tap pixel data, which is selectively extracted from the SD signal, correspond to a target position in the HD signal. In a memory bank 135, a coefficient seed data in each class and term selection information are stored. In the coefficient production circuit 136, coefficient data Wi in each class is produced according to a production equation containing the term selected by term selection information, using the coefficient seed data in each class and the values of parameters h, v for image adjustment. In a calculation circuit 127, pixel data at the target position in the HD signal is obtained from the prediction tap data xi and the coefficient data Wi, by use of an estimated equation.

Abstract: A line buffer unit stores the pixel values of image data for respective lines in synchronism with pixel clocks and a horizontal sync signal. An output counter generates a coordinate value to specify a pixel position in second image data based on the count value of predetermined clocks and the horizontal sync signal, and a data request unit converts the generated coordinate value into a pixel position in input image data on the basis of the set scale value. The pixel values of pixels required for arithmetic operations are acquired from the line buffer unit based on this pixel position, and an arithmetic unit calculates the pixel value of a pixel corresponding to the coordinate value. When the arithmetic unit is not ready to execute the arithmetic operation of the pixel value, generation of the coordinate value by the counter is stopped until the arithmetic unit is ready to execute the operation.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal, Vin, is converted into an output image signal, Vout that has different format and/or size therefrom. A class code, CL, is obtained from tap data extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal Vin (525i signal) is converted into an output image signal Vout (such as 1080i signal, XGA signal, or 525i signal for obtaining an image to be displayed in a different magnification). A class code CL is obtained from tap data selectively extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout. A coefficient production circuit produces coefficient data for each class, which is used at the time of calculating the pixel data at the target position, based on the coefficient seed data for each class and position information h, v about the target position generated in a position information generation circuit.

Abstract: An interlaced to progressive scan video converter which identifies object edges and directions, and calculates new pixel values based on the edge information. Source image data from a single video field is analyzed to detect object edges and the orientation of those edges. A 2-dimensional array of image elements surrounding each pixel location in the field is high-pass filtered along a number of different rotational vectors, and a null or minimum in the set of filtered data indicates a candidate object edge as well as the direction of that edge. A 2-dimensional array of edge candidates surrounding each pixel location is characterized to invalidate false edges by determining the number of similar and dissimilar edge orientations in the array, and then disqualifying locations which have too many dissimilar or too few similar surrounding edge candidates.

Abstract: A method and apparatus are provided for displaying progressive material on an interlaced display where the number of lines of the source frame is equal to or less than the number of lines in a display field, where such lines in the display field are derived from all of the lines of the source frame.

Abstract: A scan line conversion circuit is provided for simultaneously carrying out three-dimensional motion adaptive sequential scan conversion and scan line conversion. The scan line conversion circuit comprises an FIFO memory into which the video signal is input; a sequential scan conversion circuit section for converting an interlace signal sent from the FIFO memory to a non-interlace signal; an address generator into which a vertical enlargement ratio and a synchronous signal are input to generate an address as a spatial position after scan line conversion; a memory control unit for generating a memory control signal based on the address sent from the address generator; a coefficient generator for generating a coefficient for performing scan line conversion; a plurality of first multipliers for multiplying sequentially scan converted signals, sent from the sequential scan conversion circuit section, by respective coefficients; and an adder for adding signals output from the multipliers together.

Abstract: The present invention relates to an image signal conversion apparatus or the like preferably applied, for example, when a SD signal (525i) is converted into a HD signal (525p or the like). In the image signal conversion section (110), the SD signal is converted into the HD signal, and the image is displayed on the display section (111). A class code CL indicating a class of a subject pixel of the HD signal is obtained by detecting a space class and a motion class from tap pixel data corresponding to the subject pixel of HD signal which is selectively fetched from a SD signal. The controller (101) loads coefficient data of each class according to the selected resolution into the coefficient memory (134) from the information memory bank (135) when the user selects the resolution.

Abstract: A method for deinterlacing interlaced video using a graphics processor includes receiving at least one instruction for a 2D/3D engine to facilitate creation of an adaptively deinterlaced frame image from at least a first interlaced field. The method also includes performing, by the 2D/3D engine, at least a portion of adaptive deinterlacing based on at least the first interlaced field, in response to the at least one instruction to produce at least a portion of the adaptively deinterlaced frame image. Once the information is deinterlaced, the method includes retrieving, by a graphics processor display engine, the stored adaptively deinterlaced frame image generated by the 2D/3D engine, for display on one or more display devices. The method also includes issuing 2D/3D instructions to the 2D/3D engine to carry out deinterlacing of lines of video data from interlaced fields. This may be done, for example, by another processing device, such as a host CPU, or any other suitable processing device.

Abstract: A display control apparatus and a display control method are provided in which a resolution of an input image signal is judged, a change in the image signal is detected, and the image signal is adaptatively interpolated in accordance with the judgement and detection results. A resolution of an input image signal is judged, either a first display mode or a second display mode is selected for the display of the image signal, and the image signal is adaptatively interpolated in accordance with the judgement and selection results. Alternatively, either a computer input signal or a television input signal is input, a resolution of the input signal is judged, and the input signal is adaptatively interpolated in accordance with the selected input and judgement results.

Abstract: A image displaying and controlling apparatus for displaying a computer graphics image in square-shaped pixels in an MPEG2 image format in rectangular-shaped pixels at a regular roundness. A graphics processor block produces the data of 640×480 pixels, two-line data of which are stored in two 1H buffers, and are multiplied respectively by weights output by a weight control circuit through a line conversion circuit. As a result, data of 640×432 are produced. A delay circuit delays a vertical synchronizing signal output by the graphics processor block by 14H. A phase comparator circuit compares the 14H delayed vertical synchronizing signal in phase with a vertical synchronizing signal output by an MPEG2 video decoder. The timing of the generation of the vertical synchronizing signal at the graphics processor block is set to be earlier by 14H than the timing of the generation of the vertical synchronization signal of the MPEG2 video decoder.

Abstract: An adaptive filter is adjustable for performing scaling operations. During a scaling operation, the adaptive filter stores scaled data in a memory such that more data samples may be retrieved during a subsequent scaling operation. The size of a finite impulse response filter used during the subsequent scaling operation may be adjusted to access the additional data samples.

Abstract: An apparatus and a method for converting image signals from an interlaced scanning format to a progressive scanning format are disclosed. Additionally, an apparatus and a method for changing a vertical scanning rate of progressively scanned image signals are also disclosed. Field motion estimator estimates field motions between a current field and reference fields to find an optimal reference field. Then a field motion compensator restores a missing line of the current field using information given from the optimal reference if the optimal reference field unevenly matches to the current field. Otherwise, a linear interpolator restores the missing line of the current field by linearly interpolating lines located adjacent to the missing line in the current field. Furthermore, a frame motion estimator estimates frame motions between adjacent frames using the progressively scanned image signals and field motions estimated in the field motions estimator.

Abstract: A video signal processing apparatus processes input video signals. A video signal source supplies the input video signals carrying at least a first video signal that is an interlaced signal having 480 effective scanning lines and a second video signal that is an interlaced signal having 1080 effective scanning lines. A video signal processor converts at least the first and the second video signals into a third video signal that is a progressive signal having 1440 effective scanning lines, thus outputting the third video signal. The output third video signal may be converted into a fourth video signal that is an interlaced signal by a progressive-to-interlace converter, thus outputting the fourth video signal.

Abstract: A binarizer binarizes a video signal VD1 inputted from an A/D converter and a video signal VD2 outputted from a line memory using an average luminance value LU fed from a detection window video signal processor as a threshold value, to output a binary pattern BI. A reference pattern generator generates a plurality of reference patterns RA. A first pattern matching angle detector compares the binary pattern BI with each of the plurality of reference patterns RA, to output the angle of the reference pattern RA which matches with the binary pattern BI as angle information PA. A detected isolation point remover 4 outputs angle signal AN when the angle information PA has continuity.

Abstract: An effective pixel area calculating circuit (11) detects position information indicating the position of a target pixel in a frame. A lacking pixel creating circuit (12) determines the class of the target pixel from a plurality of classes in accordance with the position information, then selects a plurality of pixels from an input image signal as a prediction tap, and carries out arithmetic processing based on conversion data obtained in advance by learning for each class and the prediction tap, thus outputting an output image signal of higher quality than the input image signal.

Abstract: In a video-processing unit comprising a processing means, memory means and a memory manager, an output of the processing means is coupled to the memory manager for storing of the processed data from the processing means in the memory means to allow execution of different processes in video-processing unit by a single processing means.

Abstract: A method and circuit for converting the image format of three-dimensional electronic images produced with line polarization wherein, given that television pictures are transmitted with different line resolution and displayed on devices whose line resolution does not coincide with the line resolution of the transmitted images, lines are not only respectively inserted or skipped, but also transposed with one another.

Abstract: An improved interpolation method in which a threshold value used for determining a pixel value of a pixel generated by interpolation according to a context which is a state value of adjacent pixels. In the interpolation method, the ambiguity between the interpolation value and the threshold value is removed by using the context, thereby reducing the blocking and smoothing phenomena in the restored binary image.