Abstract: A display control device includes a detector, a frequency adjusting signal generator, a clock generator and an output timing generator. The detector compares an input field reference signal with an output field reference signal to determine a time difference signal. The frequency adjusting signal generator outputs a frequency adjusting signal. The clock generator outputs a clock according to the frequency adjusting signal. The output timing generator generates an output field synchronization signal according to the clock. The clock generator adjusts the frequency of the clock according to the frequency adjusting signal.

Abstract: An image signal processor and a method for processing an image signal thereof are disclosed. When the image signal processor executes an automatic chroma gain control (ACC), the image signal processor adjusts a variable rate of ACC gain according to a size of an input color signal to reduce a time for processing the ACC. Even if a difference between the size of the input color signal and the size of a reference color signal is large, the ACC is rapidly processed. As a result, transient phenomenon disappears from a screen.

Abstract: Color information decoding on a composite video signal that includes modulated color information for an analog television receiver. A first burst locked oscillator (BLO) operates in a first loop gain, and a second BLO operates in second loop gain and is operatively connected to the first BLO. The first loop gain is higher than the second loop gain. A method includes receiving, in a first burst accumulator, mixed down color information directly from a first phase detector without filtering the mixed down color information, converting the composite video signal to a burst gate signal, accumulating one or more of the burst gate signal, and calculating a frequency offset for the second BLO in the first BLO expedite the calculating of the frequency offset and to compensate for the second BLO operating in the second loop gain.

Abstract: A video signal converting device is capable of converting an analog composite signal into a proper digital signal with a small delay even if the analog composite signal contains much jitter. The video signal converting device has a sampling clock output unit for outputting a sampling clock signal having a frequency which is 4n times the frequency of a burst signal contained in the analog composite signal (n represents a positive integer of 2 or greater), and an analog-to-digital converting unit for converting the analog composite signal into a digital signal based on the sampling clock signal output from the sampling clock output unit.

Abstract: A synchronization separation circuit extracts a synchronization timing signal from a video signal, and a burst gate pulse generator generates a timing pulse signal for gating a color burst signal period. In the color burst signal period restricted by the timing pulse signal, a first counter counts up cycles of a color burst signal at a first timing as a rising edge of the color burst signal and a second counter counts up cycles of the color burst signal at a second timing as a falling edge of the color burst signal. A color burst determination circuit receives count values to determine presence/absence of a color burst signal superimposed on the video signal.

Abstract: A digital signal gating method and apparatus of a preprocessor in a detection system wherein the detection system includes a central processing unit, a main memory and a receiver, whereby the apparatus and method bifurcate received digital signals, delays them along a first path while subjecting the digital signals along a second path to detection, delay, and thresholding and thereby generates a gating signal from the second path so that digital signals of the first path, including pre-threshold amplitudes, may be recorded.

Abstract: A simulated burst gate signal and a video synchronization key are generated. A video decoder generates a horizontal sync pulse which is programmed to envelop a color burst, thereby simulating a burst gate signal. The offset to the horizontal sync pulse due to simulating a burst gate signal may be compensated at a video memory subsystem receiving the horizontal sync signal, in order to determine when active pixels are provided by the video decoder. Alternatively, counter circuitry external to the video decoder may be used to generate a simulated burst gate signal by counting the number of pixel clock cycles between the horizontal sync pulse and the color burst. Unlike a burst gate signal generated within a video decoder for use with color separation circuitry in the video decoder, a simulated burst gate signal allows for use of color separation circuitry external to the video decoder. Detecting a color burst using external color separation circuitry is thus also disclosed.

Abstract: Systems and methods are disclosed for supporting a pull data flow scheme in an A/V decoder. One method relates to processing data using an A/V decoder comprising receiving the data from a data stream and recovering a system time reference from the received data. The received data is processed using a clock asynchronous to the system time reference and pulled into an output device using a system adapted to support a pull data flow. The processed data is output using a time reference locked to the system time reference.

Abstract: A method of transferring sets of video line data and macroblock data, comprising the steps of determining a macroblock period and a video line period longer than the macroblock period, dividing each set of video line data to be transferred within the video line period into two or more portions according to the difference between the determined macroblock period and video line period, aligning a burst transfer of each of the portions of the divided set of video line data and each set of macroblock data to the macroblock period, and initiating the burst transfer of the sets of video line data and macroblock data at macroblock period intervals.

Abstract: A color signal reproducing circuit having A/D converter 101, sync separator 102, YC separator 103, gain controller 105, multipliers 106 and 107, low-pass filters 108 and 109, burst-period cumulative adders 110 and 111, SINCOS generator 112, clock generator 113, and ramp-wave generator 114. The simple structure allows a color signal reproducing circuit to be used commonly in a different television systems without changing its clock frequency considerably in accordance with broadcasting systems and also achieves YC separation and color signal demodulation from analog composite signal with a higher degree of precision.

Abstract: A color system determination circuit for use with an input video signal having a frequency component is disclosed. The circuit includes a color trap filter for attenuating the frequency component in the input video signal with the color trap filter providing a color burst output signal, a comparator for comparing the color burst output signal of the color trap filter and the frequency component of the input video signal, a maximum value detector which receives the color burst output signal of the color trap filter and a color burst sampling signal and detects a maximum value of the color burst output signal of the color trap filter during a period of the color burst sampling signal, and another maximum value detector which receives the video signal and the color burst sampling signal and detects a maximum value of the video signal during the period of the color burst sampling signal.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: A burst gate pulse generator circuit generates a burst gate pulse signal representative of a time period during which a burst signal is present within a composite video signal without requiring external components. Each period of the composite video signal includes a horizontal synchronization signal pulse, a burst signal and a video information signal. A pair of integrated capacitors are discharged during the horizontal synchronization pulse. The capacitors are charged at different rates by two current sources after the horizontal synchronization pulse. A first amount of charge across a first capacitor rises above a predetermined threshold level in a first time period. The burst gate pulse signal is activated when the first amount of charge rises above the predetermined threshold level. This occurs before the burst signal is present within the composite video signal. A second amount of charge across a second capacitor rises above the predetermined threshold level in a second time period.

Abstract: A clock generation circuit for a digital video processing apparatus which has a simple structure and can be stably worked in both luminance and color signal systems. A color burst phase error signal indicative of phase difference of a color burst signal is produced on the basis of two color difference signals, a sampling clock signal is generated in accordance with the color burst phase error signal, the sampling clock is divided in order to produce a chrominance subcarrier signal, and the phase of the chrominance subcarrier signal is adjusted in accordance with the color burst phase error signal.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: In a color signal processing circuit capable of processing a PAL/NTSC color television signal, in order to prevent an image deterioration caused by chromatization when a PAL signal is received in an NTSC signal receiving mode, there is provided a gate control signal generating circuit for alternately generating gate control signals "GA" and "GK", one for one horizontal period and the other for a next one horizontal period, in response to application of a phase inverting pulse "R" which inverts in polarity every one horizontal period.

Abstract: A burst separator and slicer circuit separates the burst signal from an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization signal, a burst signal and a video information signal. A burst gate pulse signal representing the presence of the burst signal within the input composite video signal is received by the burst separator and slicer circuit. During the burst period, when the burst gate pulse is active, the burst signal is extracted from the input composite video signal and converted to a square waveform. A differential pair and comparator circuit monitors the input composite video signal and compares it to a constant level reference voltage signal. A constant high voltage level is output when the burst signal is greater than the constant level reference signal. A constant low voltage level is output when the burst signal is less than the constant level reference signal.

Abstract: A color burst gate pulse forming circuit has a first counter, a second counter, a logic circuit, and a decoding circuit. The first counter counts a chrominance subcarrier supplied in a form of a clock. The second counter starts counting said chrominance subcarrier in synchronization with a horizontal synchronizing signal, and resets itself in a period longer than half a horizontal scanning period and shorter than one horizontal scanning period. The logic circuit controls the operating period of the first counter based on an output from the second counter and said horizontal synchronizing signal. The decoding circuit decodes a count output from the first counter, and outputs color burst gate pulses based on a predetermined count output.

Abstract: A black and white detector circuit monitors a burst signal separated from a composite video signal in order to determine when the composite video signal includes color video information or black and white video information. An output signal is generated which is active when color information is included and inactive when black and white information is included. The burst signal will oscillate above and below a first threshold value during a burst period if color information is included, and will remain constant if black and white information is included. When the burst signal oscillates above and below the first threshold value for a predetermined period of time, an output signal is activated and will remain active until the burst signal remains constant during a burst period. A current source is enabled when the burst signal rises above the first threshold value. The current source builds up a first level of charge on a first capacitor during the burst period.

Abstract: The invention relates to a digital multistandard decoder for composite video signals. The multistandard decoder according to the invention can selectively process NTSC or PAL video signals and there is no need to know the corresponding signal standard beforehand.

Abstract: An input signal is inputted to an A/D converter through an amplifier and is converted into a digital input signal. A vertical synchronizing pulse and a horizontal synchronizing pulse are taken out of the output signal of the amplifier by means of a TV synchronizing separator and inputted to a trigger gate and selector circuit. A delay timer and a timing control circuit are operated by a selected synchronizing pulse, and the data applied with A/D conversion are stored in a memory in accordance with a set delay time and sampling synchronization. The stored data are read by means of a CPU circuit. The state of a burst signal is decided by the CPU circuit, and separation of eight fields is performed by combining that state with a set state of the TV synchronizing separator.

Abstract: In a video processing system, a burst signal generating circuit receives a discontinuous burst signal and generates a continuous burst signal by using a phase locked loop. In the conventional video processing system, it is difficult to select a loop gain and loop bandwidth for generating a burst signal, since the performance characteristics of a phase locked loop are directly influenced by the presence of a sample and hold circuit in the phase locked loop. In order to solve this problem, in processing a digital video, a discontinuous burst signal is detected, and then during a burst signal, the phase locked loop operates by the discontinuous burst signal detected so that the continuous burst signal may be generated. When the burst signal is not present, the phase locked loop operates by a constant error value according to the continuous burst signal shifted 90 degrees in phase. Thereby, the continuous burst signal is generated.

Abstract: A method of driving a CCD semiconductor delay line capable of providing a good delay characteristic without externally supplying a clock signal. An intermittent reference signal is extracted from the color burst signal of an inputted television signal. Using the intermittent reference signal, a continuous reference signal is generated by a phase locked loop. The continuous reference signal drives a CCD semiconductor delay line to delay the television signal.

Abstract: A color signal demodulation circuit demodulates a color signal in correspondence with different chrominance subcarrier frequencies. The input color signal is delayed by .pi./2 using a so-called Hilbert transformer and the carrier signal for use in the demodulation is generated from a carrier generator. The input color signal and the carrier signal are selectively multiplied and added so as to demodulate a color difference signal of the desired baseband, to thereby correspond to the chrominance subcarriers having different frequencies while simplifying the hardware. A method for demodulating the chrominance signal, which method is particularly adapted to the demodulation circuit is also detailed.

Abstract: A color signal reproducing circuit comprising a phase correction device receiving a gain-controlled composite color signal, detecting color burst signal in a composite color signal and correcting phase of the color burst signal by using a 3.58 MHz signal, first gate for receiving the gain-controlled composite color signal and passing only a color signal when a color burst pulse in the delayed horizontal synchronizing signal applied from the delay device is at a low level, and mixer for mixing the phase-corrected color burst signal and the color signal from the first gate to produce a phase-corrected composite color signal.

Abstract: A level detection circuit includes a multiplier and an adder for computing the sums of square values of a burst signal. A maximum value holding circuit holds a maximum value of the sums of the squared values of the burst signal. A counter counts sampling clocks. A multiplier, an adder and a 1/2 processing circuit compute a half value of the sum of two consecutive count values, and a delay circuit, a latch circuit and a comparator generate a first one of the two consecutive count values as a level of the burst signal when an output of the 1/2 processing circuit becomes larger than the output of the maximum value holding circuit. The invention enables level detection by finding a square value using a small circuit.

Abstract: A CCD television camera has a head part separated from the rest of the camera. The camera head part contains a CCD imaging device and is connected by only a single line coaxial cable to a main part containing a DC power source, a line flag output circuit, and a one H-alternate switch. The coaxial cable may be up to several hundred meters in length. Respective ends of the coaxial cable are connected to the head and main parts through hydrid coils to facilitate sending of DC power current and an accurately controlled sinusoidal clock frequency signal from the main part to the camera head part, and the sending of video signals over the same single cable line from the camera head part to the main part. The hybrid coils are tuned for resonance with the clock frequency and a PLL circuit, including the coaxial cable, regulates the clock frequency to adjust for different lengths of cable.

Abstract: A magnetic recording-reproduction apparatus records and reproduces a wide-band video signal without a color burst signal. For this purpose, a two-step phase resetting operation is conducted on the FM carrier at the front porch and the horizontal sync pulse of the video signal so as to permit those phases to coincide with reference phases. A synchronizing panel clock generator generates the first reference signal with the first FM frequency corresponding to a peak level of the horizontal sync pulse and the second reference signal with the second FM frequency corresponding to a front porch level. In this case, the reference signals are phase-synchronous with each other at the leading edge of the horizontal sync pulse, and each of the FM frequencies is set to be an integer multiple of the horizontal scanning frequency.

Abstract: A method of and apparatus for regulating color in a color broadcasting receiver is disclosed and is composed of a tuner, a demodulator, and a burst level detector for detecting the color burst level of a video signal output from the demodulator and outputting the color burst level as a corresponding control voltage signal. A color controller is disclosed for controlling the color by emphasizing or attenuating the high band components of the video signal output from the demodulator in accordance with the control voltage level from the burst level detector, so that it is possible to receive video signals without much change in color regardless of the variation of the voltage standing wave ratio (VSWR) that varies according to changes in the connection between the broadcast antenna and RF cable.

Abstract: A broadcasting signal detecting circuit of a SECAM system can easily determine whether the received broadcasting is from a PAL or SECAM system in accordance with the existence of a color burst at the position of a delayed burst gate pulse, using the fact that within the back porch of the horizontal sync signal, the color burst loading period is different.