Abstract: A circuit for discriminating between received signals and a method therefor are provided. The circuit includes a detector for detecting a peak signal based on the degree of correlation between a received signal and a reference signal and a generator for generating a discrimination signal showing that the received signal is a high definition signal if the peak signal is detected in a predetermined period and showing that the received signal is a signal of an analog broadcasting method if the peak signal is not detected in the predetermined period. This can prevent the improper operation of a receiver by automatically determining whether the received signal according to a channel selection is a high definition digital signal or an analog broadcast signal.

Abstract: An image signal processor is provided which accurately detects duplicate fields of a telecinema signal. The image signal processor includes a duplicate field detecting means for detecting duplicate fields of the telecinema signal and a duplicate field removing means for removing the duplicate fields. The duplicate field detecting means uses a threshold value for detecting a duplicate field and a threshold value for detecting a non-duplicate field to improve the accuracy of detection.

Abstract: A field synchronization system of a field detect circuit adaptable for use with non-standard output digital data of forward looking infrared (FLIR) sensors. Timing signals and digital data from a FLIR sensor are utilized and there is outputted a vertical and horizontal signal output. A bypass circuit allows for the optional bypass of frame grabber generated field index circuitry so that an external field index signal is utilized.

Abstract: Images of film that has been developed are captured by image sensing. The original digital image data is converted to reduced digital image data representing images that are reduced in size and stored on a user's disk, and the original digital image data is stored on a laboratory recording medium together with an identification code identifying the roll of film. The identification code is applied to the film and to the user's disk on which the reduced digital image data has been stored. The original digital image data is read out of the laboratory recording medium and photographs of the images represented by this data are printed. Image data, information IX1 per each roll of film and information IX2 per each frame are read from photographic film having information recording zones, and the image data and information are recorded on a user's disk. A video component and an audio component are also recorded on the user's disk in advance.

Abstract: A video frame detector circuit used in synchronizing one video signal with another video signal. The video frame detector of the present invention is able to automatically detect a start of frame portion of any video composite synchronization signal connected to it without requiring programming. The start of frame commences with the least frequent vertical field, or if all fields are equally frequent, a deterministic process is used to promote one of the fields to be the start of the frame. Since the video frame detector circuit of the present invention does not require programming to recognize various video signal formats, it readily adapts to different video signal conditions with little or no manual intervention. The video frame detector contains a number of memory stores for storing previously detected video patterns obtained from a composite synchronization signal. Once a current pattern is ascertained from the composite synchronization signal, it is compared against the stored patterns.

Abstract: A digital television (DTV) receiver receives a data signal that is divided into a plurality of segments each separated by a known data segment sync sequence. The receiver includes a data segment sync signal detector that receives the data signal and filters the signal to provide a filtered data signal. The detector computes the difference between samples of the filtered data signal and an average expected filtered signal value that is representative of a nominal filtered signal value in the middle of the segment sync sequence. The detector then computes the absolute value of the computed difference, and the resultant absolute value is summed with a sampled value from the previous segment and the summed value is stored into an accumulator. The process is repeated for several segments. The location of the data segment sync sequence within the segment is determined by comparing the summed values to determine the smallest summed value, which represents the center of the segment sync sequence.

Abstract: A system and method for synchronizing a decoded, interlaced-field data stream with an interlaced field display. A system for displaying an MPEG encoded data stream includes an MPEG decoder which converts the encoded data stream into a sequence of frames. Each frame has an associated top field, bottom field, top-field-first flag, and repeat-first-field flag. The system also includes a display processor which receives the flags and determines a field display sequence for each frame which conforms to an overall display sequence which strictly alternates between top and bottom fields. This strict alternation in enforced even when the decoded field sequence does not adhere to a strict alternation. The system achieves this result with a worst-case temporal distortion of one field by inserting or omitting a 3:2 pulldown frame at each broken alternation point.

Abstract: A field decision unit capable of solving a problem involved in a conventional field decision unit in that an internal synchronizing signal can be erroneously synchronized with the equalizing pulses of a video signal owing to noise because the output halt period of a phase comparator is set rather short considering that this will facilitate the synchronization of the internal synchronizing signal with the video signal when starting the system or the like, and hence an incorrect field decision can be made. The present field decision unit includes an output controller which sets output halt pulses with a longer output halt period in a particular interval consisting of the synchronizing cycles containing the equalizing pulses and a synchronizing cycle previous thereto, and which employs output halt pulses with a shorter output halt period outside the particular interval as in the conventional system.

Abstract: A field identification signal generating circuit for a receiver for receiving a high-definition signal, and a method therefor. According to the method, a first correlation value is calculated, between the high-definition signal and a first reference signal the same as a first known signal. A timing control signal, synchronized with a second known signal whose phase is alternately inverted in every field, is output when the first correlation value is greater than or equal to a predetermined value. A second correlation value is calculated, between the high-definition signal and a second reference signal the same as the second known signal. Information on the polarity of the second correlation value is output. A field identification signal is generated on the basis of the polarity information on the second correlation value which is synchronized with the timing control signal. Therefore, the field identification signal generating circuit can be realized with simple hardware.

Abstract: A digital pulse filtering circuit for processing composite sync signals is provided. The digital pulse filtering circuit can determine the polarity of an input composite sync signal composed of a horizontal sync signal and a vertical sync signal. The horizontal sync signal is a first periodic pulse train having a first pulse width, while the vertical sync signal is a second periodic pulse train having a second pulse width. The digital pulse filtering circuit includes a horizontal sync filter for filtering out all pulses in the input composite sync signal that have a pulse width less than the pulse width of the horizontal sync signal; and a vertical sync filter, coupled to receive the output of said horizontal sync filter, for filtering out all pulses in the output of said horizontal sync filter that have a pulse width less than the pulse width of the vertical sync signal. The output of said indicating the polarity of the input composite sync signal.

Abstract: A horizontal synchronizing signal is applied as a reference signal and a voltage-controlled oscillator outputs a display clock signal on the basis of the frequency of the horizontal synchronizing signal. The frequency of the display clock signal is frequency-divided in accordance with a frequency-dividing value selected from among a plurality of frequency-dividing signals stored in advance, the difference in frequency between the frequency-divided display clock signal and the horizontal synchronizing signal and the phase difference between them are obtained by a phase comparator, and the frequency of the signal outputted by the voltage-controlled oscillator is decided in dependence upon the frequency difference. In an interval in which a vertical synchronizing signal turns off and the frequency of the horizontal synchronizing signal fluctuates, the reference signal and the horizontal synchronizing signal input to the phase comparator are held fixed to prevent a fluctuation in the outputted display clock.

Abstract: A transmitted high definition television signal is represented by a packetized datastream configured as a sequence of data fields with a non-uniform data rate due to different types of different duration non-data overhead information. Each data field is prefaced by a Field Sync overhead segment followed by 312 packetized data segments each with associated overhead information. At a transmitter, a transport processor forms data packets with associated headers and exhibits uninterrupted operation at a constant uniform data rate, while supplying a packetized datastream to a network which constructs sequential data fields by inserting the non-data overhead information into the datastream. The transport processor is advantageously operated at a constant uniform data rate without having to modify the original data field structure to accommodate the needs of the data field construction network.

Abstract: An apparatus for detecting a field sync signal in a HDTV includes a sign bit selector for selecting only a sign bit from a received HDTV signal; a correlation portion for determining the correlation value of the selected sign bit and a predetermined reference signal; a detector for comparing the correlation value with a threshold value, to thereby determine a field sync timing signal; and a generator for generating a field sync signal which has a logic "HIGH" level during one field sync segment interval in response to the field sync timing signal. Here, only one MSB of input data is selected and then correlation with the reference signal is determined. Accordingly, a field sync signal which has a logic "HIGH" level during one field segment interval in each field can be accurately detected, and thus a hardware structure is simplified.

Abstract: A method and device for performing source transitions in a video system which performs entropy encoding such that a transition occurs only after the fields which define a frame picture have been received by the encoder. The method and device also provides arrangement for ensuring that initially after the switch to the second program source consecutive fields of information from the second program source which will be encoded as a frame picture are provided.

Abstract: An auxiliary video information decoder for decoding information such as closed caption data in a video signal identifies a desired horizontal line of video in a video signal. A reference pulse in a synchronizing signal is detected followed by the generation of first and second window pulse signals occurring at predetermined delays after detection of the reference pulse. A pulse occurring in the synchronizing signal during the window pulses indicates the start of the desired horizontal line interval. A field identification signal may also be generated. Features for improving noise and phase error immunity when identifying a video line are provided.

Abstract: A synchronizing device is described. The synchronizing device detects a video frame. The synchronizing device determines a duration of a first signal state of a video signal, determines a duration of a second signal state of the video signal and compares the duration of a first signal state with the duration of a second signal state.

Abstract: A video data transmitter includes: chrominance-data multiplexer which multiplexes parallel data obtained by digitizing a chrominance signal Pb, which is a component signal of an analog HDTV video signal, with parallel data obtained by digitizing a chrominance signal Pr; a word multiplexer which multiplexes parallel data obtained by digitizing a luminance signal Y, which is a component signal of analog HDTV video signal, with the output data of the chrominance-data multiplexer, and a parallel-to-serial converter which converts the parallel data output from the word multiplexer. A video data receiver includes a serial-to-parallel converter which converts received serial data into parallel data and a word separator which separates the output data of the serial-to-parallel converter into parallel data in the Y channel and parallel data in the Pb/Pr channel.

Abstract: Jitter of an overlay display with respect to the primary display of a television receiver is avoided by assuring that the vertical and horizontal blanking signal components are sufficiently time spaced by preventing the number of clock pulses occurring between the horizontal and vertical components of the blanking signal from going below a selected number. The number of clock pulses between the negative going transition of the vertical blanking signal and the positive going transition of the first horizontal blanking signal is tracked and when the number of pulses fails to exceed a reference value the number of pulses is changed to effectively shift the transitions with respect to one another.

Abstract: A sync stripper circuit receives from a medical imaging modality a composite video signal with a horizontal sync frequency within one of first, second, third or fourth frequency ranges. The sync stripper circuit includes a circuit for stripping the composite sync signal from the received signal; horizontal sync detection circuit for detecting the horizontal sync signal from the stripped composite sync signal; a vertical sync detection circuit for detecting the vertical sync signal; an F1/F2 field detection circuit for detecting the F1/F2 field from the stripped composite sync signal; and a control circuit for controlling the horizontal sync detection circuit, the vertical sync detection circuit and the F1/F2 field detection circuit to operate in the selected one of said first, second, third or fourth frequency ranges of the received composite video signal. A serrating signal circuit inserts a horizontal signal into the vertical sync signal if serrating signals are absent therein.

Abstract: Audio frame synchronization for embedded audio demultiplexers counts the number of audio samples for each video frame of a digital video signal. The pattern of audio samples per video frame for an audio frame is detected to identify an audio frame boundary, the pattern being a function of the respective video and audio standards for the digital video signal. For example in one embodiment the number of audio samples for consecutive video frames are compared, and when there is equality between consecutive video frames the audio frame boundary is detected.

Abstract: An ODD/EVEN signal, showing whether odd fields or even fields of the image are displayed on a screen, is supplied to each unit operating for data transmission. In accordance with the ODD/EVEN signal, a CPU monitors a current condition of the display image so that data transmission and processing, and use of a data bus, are controlled with exact timing. Consequently, each unit in the apparatus may operate effectively.

Abstract: The field decision circuit includes: a field information generating circuit for outputting one of a plurality of signals as a first field information for each field in response to a pulse signal; a comparator for outputting a comparison result indicating whether the first field information agrees with second field information from an external circuit for each field; a memory for storing a predetermined number of comparison results over the predetermined number of fields; an evaluation circuit for outputting an evaluation result obtained by evaluating whether the predetermined number of comparison results satisfy a predetermined relationship; and a correction circuit for supplying the pulse signal to the field information generating circuit in accordance with the evaluation result.

Abstract: A method for determining which of similar video fields may be excised to enhance video signal compression evaluates parameters of four successive fields denoted 0, 1, 2, and 3. Accumulated differences d(0, 2) and d(1,3) of corresponding pixels in successive frames are generated. In addition a determination is made whether fields 1 and 2 exhibit interlace characteristics. If they do not exhibit interlaced characteristics, a comparison is made of d(0, 2) and d(1, 3). If d(0, 2) is less than d(1, 3) by a predetermined amount, field 2 is excised from the signal stream and a code is generated to condition a receiver to display two of the remaining four fields in a three field interval. Subsequently the latter two fields of the set of 0, 1, 2 and 3 fields, and the next two occurring fields are similarly analyzed.

Abstract: A frame synchronizing apparatus is disclosed which includes a serial-parallel converter for converting input serial data into parallel data of a plurality of channels; a plurality of intra-channel synchronization detecting circuits each for detecting a synchronization pattern and a pseudo-synchronization pattern in one channel, and generating a channel synchronization detect signal and a pseudo-synchronization detect signal in one channel; a plurality of bit-shift error pattern detecting circuits each for detecting a bit-shift error pattern in one channel, and generating a bit-shift error pattern signal in one channel; a synchronization/bit-shift error detecting circuit for detecting a synchronization between channels and specifying the amount of erroneously shifted bits, and generating a frame synchronization detect signal and bit-shift error detect signals; and a bit-shift signal generating circuit for calculating the number of erroneously shifted bits in the serial-parallel converter based on the bit-shift

Abstract: A receiver is provided for receiving a digital data stream over a communication path. The digital data is arranged as a sequence of frames, each frame including a plurality of lines of data. The beginning of each frame is indicated by a frame synchronization word; the beginning of each line is indicated by a horizontal synchronization byte. The data is interleaved by an encoder prior to transmission. The decoder contains circuitry for locating the horizontal and frame synchronization data and contains circuitry for deinterleaving the digital data. Both the synchronization locating circuitry and the deinterleaving circuitry require access to a memory, but not at the same time. Therefore, a single memory is used with the synchronization recovery circuitry and deinterleaving circuitry alternately addressing the memory.

Abstract: First and second field type detectors for first and second video signals have outputs indicating whether the video signals have first or second field types. The first video signal is synchronized with the second video signal for a combined display by a synchronous field memory and an asynchronous multiple line memory. The field type of the second video signal is changed when necessary to match the field type of the first video signal to maintain interlace integrity in the combined display. A field type changing circuit, which controls the synchronizing, has a first mode of operation which delays writing a current field of the first field type by one horizontal line period, a second mode of operation which advances writing a current field of the second field type by one horizontal line period and a third mode of operation which maintains a current field type.

Abstract: In a method of controlling a picture signal processing mode, first and second motion vectors are determined (ME, D.sub.T) for first and second fields, and a picture signal processing mode control signal is obtained by comparing (D.sub.T, -, COMP-R) the first and second motion vectors. The control signal may be transmitted along with, for example, a HDTV signal to give an indication to a TV receiver whether the signal originated from movie-film or from non-movie-film or be generated within the receiver.

Abstract: A circuit for detecting odd and even numbered fields of a video signal includes a first counter circuit for counting a clock pulse input to detect a vertical synchronous pulse interval of the video signal, a second counter circuit for counting the clock pulse upon detection of the vertical synchronous pulse interval to generate a window signal and a counting signal having a predetermined pulse width, and an output circuit responsive to horizontal synchronous pulses and the window signal to generate a first logic state remaining for a next vertical synchronous pulse interval or generate a second logic state remaining for the next vertical synchronous pulse interval, whereby the output circuit maintains the first logic state for the odd field and the second logic state for the even field.