Abstract: A vertical synchronous signal separation circuit is disclosed wherein the circuit includes a vertical synchronous pulse removal circuit for delaying original horizontal and vertical synchronous signals separated from a composite video signal by a predetermined time period in response to a reference clock signal and logically combining the original horizontal and vertical synchronous signals with the delayed horizontal and vertical synchronous signals to remove vertical synchronous pulses therefrom, a clock generator for logically combining an output signal from the vertical synchronous pulse removal circuit with the reference clock signal to generate a clock signal, an edge detector for detecting edges of the output signal from the vertical synchronous pulse removal circuit and outputting the detected edges as a reset signal, and a vertical synchronous signal extractor for extracting a stable vertical synchronous signal from the original horizontal and vertical synchronous signals in response to the clock sig

Abstract: Apparatus for extracting a target signal from a composite signal. The apparatus makes use of the composite signal to generate a DC power supply, whereupon no external power supply is needed for the apparatus to operate.

Abstract: The apparatus of the invention includes an edge detection circuit, a divide-by-N circuit and a latch. The edge detection circuit, responsive to an edge of the input signal, generates a trigger signal of a first frequency. The divide-by-N circuit inputs the trigger signal and generates a latch signal of a second frequency. The second frequency is equal to the first frequency divided by N. The latch inputs the input signal, and responsive to the latch signal, latches the input signal and outputs a polarity value representative of the polarity of the input signal.

Abstract: An apparatus for separating vertical synchronizing signal components from image signals in a VCR of a double rotation head helical scanning system. The apparatus comprises a level detecting unit for detecting the level of an output signal from an amplifying unit, a comparing unit for comparing the output signal from the level detecting unit with a reference voltage (V.sub.1), a switching unit operable according to the output signal from the comparing unit, and a limiting unit for limiting an output signal from a demodulating unit to a predetermined limit voltage (V.sub.2) via the switching unit upon the operation of the switching unit. The apparatus achieves an accurate separation of vertical synchronizing signal components in all cases of using a combined head for a SP/LP mode and using a single head for a SP mode or a LP mode.

Abstract: Synchronization signals for a digital device are derived for an analog composite video source by computing during a "synch-up" phase the average duration of a low synchronization portion of the signal and the average duration of a high active portion of the signal over a predetermined number of lines separated by the synchronization portions. During subsequent operation, the duration of low times and high times as they are encountered in the unknown signal are compared with their respective average durations. If the duration of a low time is significantly longer than the average low time, a vertical synchronization signal is indicated, the vertical synchronization signal being about 20 times longer than the horizontal synchronization signal in a typical video format. Similarly, if the duration of a high time is significantly shorter than the average high time, a video half line is indicated.

Abstract: A composite synchronizing signal separation circuit in which separation of the composite synchronizing signal by a digital circuit is realized and such trouble as adjusting the time constant is not needed and a phase shift is reduced: a horizontal interruption receiving circuit 1 which is reset by a timing pulse signal at the time point of 3/4 from the starting time point of one horizontal synchronizing period, and separates and outputs a horizontal synchronizing signal HD from a composite synchronizing signal SYNC; a schedule counter circuit 2 which is reset by the horizontal synchronizing signal HD and outputs count value while counting up to a predetermined value in one horizontal synchronizing period; a timing decoding circuit 3 which decodes the count value and respectively outputs timing pulse signals at the time points of 1/4, 1/2 and 3/4 from the starting time point of one horizontal synchronizing period; and a vertical interruption receiving circuit 4 which samples the composite synchronizing signal