Abstract: In an embodiment, there is provided a video processing component comprising a compensation engine configured to generate pixels of a first video frame from a second video frame based at least in part on specified pixel motion; and an access buffer configured to store pixel data corresponding to pixels of the second video frame for reference by the compensation engine, wherein the pixel data is stored by the access buffer at different vertical resolutions depending on vertical distances of the pixels corresponding to the pixel data from a target pixel that is indicated by the compensation engine.

Abstract: Techniques are disclosed relating to video signal-to-noise ratio (VSNR) measurement. In one embodiment, an analog television signal receiver includes a measurement circuit configured to measure noise in a video signal over one or more intervals that correspond to a horizontal control signal of the video signal and a control unit configured to determine a VSNR based on the measurement. In another embodiment, a first noise calculation circuit is configured to determine first noise information from a video signal and a second noise calculation circuit is configured to determine second noise information from a video signal in a manner different from the first noise calculation circuit. A control unit may be configured to generate a VSNR based on one or both of the first noise information and the second noise information.

Abstract: An overflow suppression technique that is effective for avoiding degradation in image quality is provided. A fundamental waveform and detail is extracted out of an input RGB signal. A suppression gain generation unit 614 generates a suppression gain from the extracted fundamental waveform. Multipliers 612a and 612b multiply the detail and the fundamental waveform by the generated suppression gain, respectively. Then, an adder 626 combines them together for a mixed output. Alternatively, equalization processing is performed as follows. A low frequency component fundamental waveform is obtained as a result of the passing of an input RGB signal through a low pass filter 622. A suppression gain is generated from the low frequency component fundamental waveform. Then, the input itself is multiplied by the suppression gain to obtain an output.

Abstract: A slicer level calculator including a signal detector, a moving average calculator, a sync-tip voltage sample circuit, a blanking voltage sample circuit, a slicer level calculator, and a rear-end processor is disclosed. The signal detector determines whether an input video signal satisfies a low signal to noise ratio (SNR) criterion. If so, the first signal detector further enables a low SNR control signal. The moving average calculator obtains a moving average voltage level of the input video signal. The sync-tip voltage sample circuit, the blanking voltage sample circuit and the slicer level calculator obtain a sync-tip voltage level, a blanking voltage level, and a slicer voltage level, respectively. The rear-end processor selectively executes low-pass filtering operation on the slicer voltage level in response to the low SNR control signal.

Abstract: A slicer level calculator including a signal detector, a moving average calculator, a sync-tip voltage sample circuit, a blanking voltage sample circuit, a slicer level calculator, and a rear-end processor is disclosed. The signal detector determines whether an input video signal satisfies a low signal to noise ratio (SNR) criterion. If so, the first signal detector further enables a low SNR control signal. The moving average calculator obtains a moving average voltage level of the input video signal. The sync-tip voltage sample circuit, the blanking voltage sample circuit and the slicer level calculator obtain a sync-tip voltage level, a blanking voltage level, and a slicer voltage level, respectively. The rear-end processor selectively executes low-pass filtering operation on the slicer voltage level in response to the low SNR control signal.

Abstract: A microcontroller-based video AGC/sync regulator in which the parameters of various synchronizing signals of several different video formats are incorporated into a user program to generate signals to be processed by other sub circuits that correct and reinforce the AGC levels and sync signals of an incoming video signal is disclosed. The microcontroller-based video AGC/sync regulator is synchronized by the selection and isolation of a reference point of particular qualities that distinguishes itself from any other portion of the video signal. The reference points may be singular or plural in nature and are extracted from the video signal by means of a hybrid and specialized circuit or circuits, an auxiliary microcontroller and/or the system microcontroller. The microcontroller-based AGC/sync regulator is readily adapted for use as a decoder/encoder by altering the user program.

Abstract: A Sync On Green signal detection circuit includes a clamping circuit for clamping a voltage of a video graphics signal within a default range and then outputting a clamped input signal; a first PGA (programmable gain amplifier) for receiving and amplifying the clamped input signal by a first gain to generate a first gain signal; a first low-pass filter for receiving the first gain signal and then generating a first filtered signal; a second PGA for receiving and amplifying the clamped input signal by a second gain to generate a second gain signal, wherein the second gain is different from the first gain; a second low-pass filter for receiving the second gain signal and then generating a second filtered signal; a programmable voltage shifter for receiving and adjusting the first filtered signal and then outputting a level shifted signal; and a comparator for receiving the level shifted signal and the second filtered signal and then generating a comparison signal as a SOG signal.

Abstract: In one aspect a transmission system with a transmitter which can be connected to a video source and a receiver linked to the transmitter via at least four circuit pairs, to which receiver a playback device can be connected is provided. Data is usually exchanged digitally between a graphics card in a personal computer and an LCD display module. The personal computer transmits a digital R, G, B video signal to the LCD display module via a special, so-called DVI (Digital Video Interface) cable. This DVI cable is also provided to transmit so-called DDC (Display Data Channel) data, which particularly comprises specification information of the LCD display module. A transmission system is proposed, which simplifies a connection of an LCD display module to a personal computer and with which the DVI cable can be dispensed with.

Abstract: A synchronization signal detector includes a horizontal synchronization level detector, a synchronization signal extractor, a first filter circuit, and a synchronous separator. The horizontal synchronization level detector detects a horizontal synchronization detection level HL for detecting a horizontal synchronization signal from a video signal Din. The synchronization signal extractor outputs a limited signal D1 obtained by extracting only a signal within a limit range (HL?n) to (HL+m) that is set based on the horizontal synchronization detection level HL from the video signal Din. The first filter circuit removes a high frequency component of the limited signal D1 and outputs it. The synchronous separator detects a horizontal synchronization signal HS from the output signal of the first filter circuit.

Abstract: A television monitor display with video signal processing comprises a source (SM) of a video display signal (Y) including a sync component (S). A video processor (U1) is coupled to process the video display signal (Y). A sync separator (SS) is coupled to generate separated synchronizing signals (Sy) from the sync component (S) of the video display signal (Y). A video amplifier (100) is coupled to the sync separator (SS) and the video processor (U1) and generates an output video signal (Ys+) wherein a sync component (S+) of the output video signal is increased in amplitude in accordance with the separate synchronizing signals (Sy) coupled to the video amplifier (100).

Abstract: A Sync On Green signal detection circuit includes a clamping circuit for clamping a voltage of a video graphics signal within a default range and then outputting a clamped input signal; a first PGA (programmable gain amplifier) for receiving and amplifying the clamped input signal by a first gain to generate a first gain signal; a first low-pass filter for receiving the first gain signal and then generating a first filtered signal; a second PGA for receiving and amplifying the clamped input signal by a second gain to generate a second gain signal, wherein the second gain is different from the first gain; a second low-pass filter for receiving the second gain signal and then generating a second filtered signal; a programmable voltage shifter for receiving and adjusting the first filtered signal and then outputting a level shifted signal; and a comparator for receiving the level shifted signal and the second filtered signal and then generating a comparison signal as a SOG signal.

Abstract: The invention relates to a synchronization signal decoder and associated method for improving digital image display. A composite video stream includes a distortion compliant signal and a synchronization signal. A level shift circuit is adapted to shift a voltage level of the composite video stream such that the distortion compliant signal is readily distinguishable from the synchronization signal. A level shift disable circuit is adapted to disable the level shift circuit responsive to the composite video stream.

Abstract: A polyphase receiver comprises an RF front end (10 to 28) for receiving a wanted data signal modulated on a carrier signal and for producing quadrature related low IF signals, an image rejection filter formed by a polyphase filter (30) for filtering the quadrature related low IF signals, soft limiting means (36,38) for compressing the dynamic range of the filtered quadrature related IF signals and a signal demodulator (41) for recovering the data signal. The soft limiting means (36,38) has a characteristic which is substantially linear at signal levels 10 dB below a predetermined minimum wanted signal level, moves into compression for higher signal levels and hard limits at substantially 10 dB above the desired receiver sensitivity which avoids degrading the sensitivity of the receiver.

Abstract: A vertical synchronous signal detection circuit includes an analog-digital converter, an average calculation circuit and a compare circuit. The analog-digital converter receives a composite video signal and converts the video signal into a digital signal having a vertical synchronizing pulse. The average calculation circuit is coupled to receive the digital signal. The average calculation circuit calculates an average level of the vertical synchronizing pulse within a predetermined period. The compare circuit is connected to the average calculation circuit. The compare circuit compares a threshold level received thereto with the average level and outputs a synchronous detect signal when the average level falls below the threshold level.

Abstract: The invention concerns a method for determining the quality of a video and/or television image signal. In diversity reception installations comprising several receivers, it is necessary to establish a criterion for assessing the reception signals, so as to select the receiver with the best reception. In order to determine the quality of a television image, the interfering impulses appearing in a line after a horizontal synchronization impulse are detected then their parameters are evaluated. The invention is applicable to television receivers, video recorders, diversity reception installations, in particular for mobile installations.

Abstract: A technique for delivering analog video over fiber-to-the-home (FTTH) networks addresses a fundamental problem of the standard signal format, i.e., power budget constraint, by increasing the usable optical signal efficiency. In particular, a technique is provided for transmitting an efficient modified analog video which is compatible with existing receivers. More specifically, the synchronization portion of a standard NTSC video signal is reduced in amplitude during transmission, producing an appreciable increase in the allowable optical modulation index (OMI).

Abstract: A digital video vertical synchronization pulse detector for detecting a vertical synchronization pulse in a video signal is disclosed. The digital video vertical synchronization pulse detector includes a threshold device for comparing a first digital data stream generated from the video signal to a sync threshold. An integration device integrates the video signal in response to the threshold device to generate a second digital data stream. Upper and lower threshold devices compare the second digital data stream to upper and lower thresholds. A detection device responsive to the upper and lower threshold devices detects when the second digital data stream crosses the upper and lower thresholds. When the second digital data stream crosses the upper threshold, the detection device generates a first vertical sync pulse and when the second digital data stream crosses the lower threshold, the detection device is reset to enable generation of subsequent vertical sync pulses.

Abstract: A digital black clamp circuit for calibrating the black level of an image signal produced by an imaging device, such as a CCD sensor. The digital black clamp circuit comprises a source of a video signal having a first interval of black level pixels and a second interval of image pixels; a differential amplifier having first and second inputs and an output, wherein the source is coupled to one of the first and second inputs; an A/D converter coupled to the output of the differential amplifier; a digital signal processor coupled to the A/D for accumulating and averaging digital black level pixels; a D/A converter coupled to the digital signal processor; and a control for selectively uncoupling the D/A converter to the other of the first and second inputs of the differential amplifier during the first interval of the video signal; and for coupling the D/A converter to the other of the first and second inputs during the second interval of the video signal to clamp the image pixels to an average black level.