Abstract: A timing generator and method of developing drive signals which, when input sync signals are present, delivers the leading and trailing edges of the input pulses directly to a drive output and which generates a free-running signal when input sync pulses are not present.

Abstract: In a liquid crystal television, a display controller prevents burning of a liquid crystal panel due to irregularity in a synchronization signal. A counter of a liquid crystal display controller detects a period of a horizontal synchronization signal and a vertical synchronization signal. A comparator compares a count value with a predetermined minimum value Min and maximum value Max. When the count value is out of a range, a synchronization pulse generator generates a synchronization pulse at a time when the period falls within a predetermined range. A selector outputs an input synchronization signal when the period is within the range and outputs the synchronization pulse obtained from the synchronization pulse generator when the period is out of the range.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: Method and device for correcting errors in synchronization of operations of recovering sequences of ancillary data transmitted over the invisible lines of the VBI of a video signal including a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync used to synchronize the opening of time windows for recovery of the data. In the event of the absence of a horizontal synchronization pulse at the end of a period equal to H+.DELTA.H, where H is the period of the signal Hsync and .DELTA.H is a first predetermined lapse of time, an artificial synchronization pulse is generated, and the moment of opening of the window for recovering ancillary data to the moment of generation of the artificial synchronization pulses so as to cause the moment to coincide with the start of the sequence of ancillary data to be recovered.

Abstract: A counter control circuit of a counter for measuring a pulse period of a video synchronization signal includes a main control unit having a synchronization signal input Sync, and a control signal producing unit including a stop signal generator, a latch signal generator, and a start signal generator. The outputs of the stop, latch and start signal generators are supplied to the counter for controlling the counter to count clock pulses fed from a clock generator in response to receipt of a start signal and output a count value in response to receipt of a latch signal. The main control unit produces sequential control signals during the input of the video synchronization signal differentiated by the clock pulses. The counter control circuit allows the counter to measure a pulse period of an input synchronization signal in a stable state that results in an accurate count value, since the count operation is first stopped and the count value is latched by the clock signal.

Abstract: A control circuit (100) which receives horizontal synchronising pulses (265) and generates a horizontal drive output signal (455) for a cathode ray tube (CRT) display. The horizontal control circuit (100) generates two ramp signals. A first ramp signal (410) for horizontal position adjustment of an image on the CRT display, and a second ramp signal (440) for propagation delay compensation of a deflection circuit (155) coupled to the CRT display. The control circuit (100) also provides digital of control of the duty cycle of the horizontal drive signal (455).

Abstract: The invention pertains to a digital video horizontal synchronization pulse detector and processor comprising pulse detector for generating a timing pulse in response to each horizontal synchronization pulse. A sync position error device generates a time position error signal for each timing pulse relative to a corresponding window pulse. A window pulse generator generates the window pulses and limits the time position error signals to a maximum value. An acquisition device tracks when the timing pulses occur inside and outside the corresponding window pulses. An averaging device averages the time position error signals to generate an average error signal.

Abstract: Various video signals provide horizontal sync pulses for generating a horizontal drive signal only during a horizontal sync portion and part of the vertical sync portion of a video signal. The invention generates a horizontal drive signal in the absence of horizontal sync pulses through the use of a phase locked loop (PLL) connected in feedback to horizontal counter logic. The counter logic receives pulses from the phase locked loop and at a predetermined count generates a horizontal drive signal. During the horizontal sync portion of the video drive signal, the frequency of the phase locked loop is determined by a time difference between a second signal derived directly from a horizontal sync pulse and a first signal generated by a predetermined count. The horizontal drive signal is thus synchronized to the horizontal sync pulses.

Abstract: A synchronizing signal separator receives synchronizing signals from a remote source. A window generator opens a window for a period and a counter regenerates synchronizing signals detected when the window is open. Detection of an incoming synchronizing signal when the window is open causes a window counter to be stopped to reduce the window duration to approach a set minimum width. The window generator and the counter are controlled by a voltage controlled oscillator whose oscillation frequency varies according to a feedback signal derived from the sense of the phase error between an external counter of the window generator and the regeneration counter.